± 2g / 4g / 8g / 16g Tri-axis Digital
Accelerometer Technical
Reference Manual
PART NUMBER:
KX132-1211
Rev. 1.0
31-Jul-2019
36 Thornwood Dr.
–
Ithaca, NY 14850
© 2019 Kionix
–
All Rights Reserved
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Page
15
of
73
WMI
– Watermark Interrupt bit indicates that user-defined buffer’s sample threshold (watermark) has
been exceeded when in FIFO or Stream modes. Not used in Trigger mode. This bit is
automatically cleared when buffer is read, and the content is below the watermark.
WMI = 0
– Buffer watermark has not been exceeded
WMI = 1
– Buffer watermark has been exceeded
DRDY
– Data Ready (DRDY) interrupt bit indicates that new acceleration data is available in output
data registers 0x08 to 0x0D. This bit is cleared when acceleration data is read or the interrupt
latch release register (INT_REL) is read.
DRDY = 0 - new acceleration data is not available
DRDY = 1 - new acceleration data is available
TDTS<1:0>
– Tap
TM
/Double-Tap
TM
Status bits. These bits are cleared when the interrupt latch
release register (INT_REL) is read.
TDTS1
TDTS0
Event
0
0
No Tap
0
1
Single-Tap
1
0
Double-Tap
1
1
undefined
Table 5:
Tap
TM
/Double-Tap
TM
Status Reporting Bits
TPS
– Tilt Position Status bit
TPS = 0
– Position has not changed
TPS = 1
– Position has changed
