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3-24
Programming and Parameters
PowerFlex 700S Phase II AC Drive User Manual -
Publication 20D-UM006G-EN-P – July 2008
145
Hardware Present
Indicates if optional hardware is installed.
146
FW TaskTime Sel
Sets the scan times for the drive firmware. Changing the firmware scan times will affect drive
performance. Faster scan times may allow for higher bandwidth of the internal regulators. To
achieve faster scan times some functions may need to be disabled. Only the most demanding
application may benefit from faster scan times. Typically, adjusting this parameter is not
needed, it is recommended you consult the factory before changing.
Default:
Options:
0 =
0 =
1 =
2 =
“0.5 /2 /8ms”
“0.5 /2 /8ms”
“0.5 /1 /8ms”
“0.25 /1 /8ms”
RW 16-bit
Integer
147
FW Functions En
Allows specific firmware functions to be disabled. When a bit is false, the associated function is disabled and all related parameters will be hidden. When a bit is
true, the associated function is enabled and all related parameters will be displayed.
Notes: Bits 18, 20, & 21 were changed to “Reserved” for firmware version 2.04. Bit 19 “MotinPlanner” and 24 “PhaseLockLp” were added for firmware version
3.01.
148
FW TaskTime Actl
Displays the actual firmware scan times selected by
change to the firmware scan time is accepted, the drive evaluates the change to ensure the
processor will not be overloaded. If there is risk of overloading the processor, the change will
not be accepted.
Default:
Options:
0 =
0 =
1 =
2 =
3 =
4 =
5 =
6 =
7 =
8 =
“0.5 /2 /8ms”
“0.5 /2 /8ms”
“0.5 /1 /8ms”
“0.25 /1 /8ms”
“0.25 /0.5 /8ms”
“0.1/0.5 /8ms”
“0.5/1 /2ms”
“0.25 /1 /2ms”
“0.25 /0.5 /2ms”
“0.1/0.5 /2ms”
RO 16-bit
Integer
149
FW FunctionsActl
Displays the actual state of the firmware functions. If activating requested functions could overload the processor, the change to
[FW Functions En] will
not be accepted.
Note: Bit 19 “MotinPlanner” and 24 “PhaseLockLp” were added for firmware version 3.01
150
Logic State Mach
Indicates the logical state of the drive.
Value 0- Stopped indicates zero speed has been detected and the speed and torque
regulators are disabled.
Value 8 “Slip Test” indicates that the Slip Frequency Auto Tune test is in progress.
Note: Value 8 “Slip Test” was added for firmware version 3.01. Values 9 “Finding Home” and
10 “Homing Done” were added for firmware version 3.03.
Default:
Options:
0 =
0 =
1 =
2 =
3 =
4 =
5 =
“Stopped”
“Stopped”
6 = “Test Done”
“Starting”
7 = “EnableHealth”
“Running”
8 = “Slip Test”
“Stopping”
9 = “Finding Home”
“Inertia Test”
10 = “Homing Done”
“MC Diag”
No.
Name
Description
Values
Linkab
le
R
ead-Wr
ite
Da
ta
T
ype
Options
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Dr
iv
eLog
ix
St
ahl F
dbc
k
Res
er
ved
Te
mpo
sonF
dbk
Res
olv
er Brd
MDI Brd
Heiden
hain
St
egmann
HiRs
2nd
Enc
ode
r
Res
er
ved
Res
er
ved
Saf
eOff Brd
Res
er
ved
Syn
chLink
Brd
Res
er
ved
Embed
dedENE
T
DPI Co
mm Brd
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
0 = False
1 = True
Options
Dv
lpmnt
D
eBug
Tr
en
ding
Re
ser
ved
P
eak
De
tec
t
Te
st
P
oi
nt
s
Re
ser
ved
Re
ser
ved
Ph
ase Lo
ck
Lp
Sy
nc Gene
r
P
osWt
ch/
Dt
ct
Re
ser
ved
Re
ser
ved
Mo
tinPlann
er
Re
ser
ved
Re
ser
ved
Po
si
tio
nC
tr
l
DI BitSw
aps
Digital Ou
ts
An
alog Out
s
An
alog In
s
PF
700S
Re
ser
ved
Re
ser
ved
Li
m/
Fun
c Gen
Pr
oc
ess
T
rim
Re
ser
ved
Sp
eed Reg
Vir
t Enco
der
F
rict
ionCo
m
p
Iner
tia Comp
Sp
d Ref Ctr
l
Sp
d Ref Sel
Default
1
1
0
1
1
0
0
0
1
1
0
0
0
0
0
0
1
1
1
1
1
0
0
1
1
0
1
1
1
1
1
1
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
0 = False
1 = True
Options
DvlpmntDeBu
g
Tr
ending
Rese
rv
ed
Pe
ak
D
et
ec
t
Te
st
P
oin
ts
Rese
rv
ed
Rese
rv
ed
Phas
e L
oc
kLp
Sync
Ge
ner
Po
sW
tc
h/
D
tc
t
P
osi
t Of
fs
et
P
osi
t Mo
tio
n
MotinP
la
nner
Po
si
t P
t2
P
t
P
osi
t D
ire
ct
P
os
it In
ter
p
DI BitS
w
ap
s
Digital Outs
Analog Out
s
Analog I
ns
Rese
rv
ed
Rese
rv
ed
Rese
rv
ed
Lim/Fu
nc Gen
Pro
ces
s T
rim
Rese
rv
ed
Speed
Re
g
Vir
t Enc
oder
Fr
ic
tio
nC
om
p
In
er
tia
Co
mp
Spd Ref
C
tr
l
Spd Ref
S
el
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
0 = False
1 = True