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Renesas Single-Chip Microcomputer SH7203, Hardware Manual

The Renesas Single-Chip Microcomputer SH7203 is a powerful hardware solution that offers exceptional performance and versatility. Unlock its full potential by downloading the free Hardware Manual, available at manualshive.com. Gain in-depth insights and guidance on utilizing the SH7203's capabilities effectively and efficiently.

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Section 19   Controller Area Network (RCAN-TL1) 

Rev. 0.50  May 18, 2006  Page 960 of 1588 

REJ09B0313-0050 

 

Normal Mode: 

RCAN-TL1 operates in the normal mode. 

Listen-Only Mode: 

ISO-11898 requires this mode for baud rate detection. The Error Counters 
are cleared and disabled so that the TEC/REC does not increase the values, 
and the CTxn (n = A, B, C) Output is disabled so that RCAN-TL1 does not 
generate error frames or acknowledgment bits. IRR13 is set when a 
message error occurs. 

Self Test Mode 1: 

RCAN-TL1 generates its own Acknowledge bit, and can store its own 
messages into a reception mailbox (if required). The CRxn/CTxn (n = A, 
B, C) pins must be connected to the CAN bus. 

Self Test Mode 2: 

RCAN-TL1 generates its own Acknowledge bit, and can store its own 
messages into a reception mailbox (if required). The CRxn/CTxn (n = A, 
B, C) pins do not need to be connected to the CAN bus or any external 
devices, as the internal CTxn (n = A, B, C) is looped back to the internal 
CRxn (n = A, B, C). CTxn (n = A, B, C) pin outputs only recessive bits and 
CRxn (n = A, B, C) pin is disabled. 

Write Error Counter:  TEC/REC can be written in this mode. RCAN-TL1 can be forced to 

become an Error Passive mode by writing a value greater than 127 into the 
Error Counters. The value written into TEC is used to write into REC, so 
only the same value can be set to these registers. Similarly, RCAN-TL1 
can be forced to become an Error Warning by writing a value greater than 
95 into them. 

RCAN-TL1 needs to be in Halt Mode when writing into TEC/REC 
(MCR1 must be "1" when writing to the Error Counter). Furthermore this 
test mode needs to be exited prior to leaving Halt mode.  

Error Passive Mode: 

RCAN-TL1 can be forced to enter Error Passive mode. 
Note: The REC will not be modified by implementing this Mode. 
However, once running in Error Passive Mode, the REC will increase 
normally should errors be received. In this Mode, RCAN-TL1 will enter 
BusOff if TEC reaches 256 (Dec). However when this mode is used 
RCAN-TL1 will not be able to become Error Active. Consequently, at the 
end of the Bus Off recovery sequence, RCAN-TL1 will move to Error 
Passive and not to Error Active. 

When message error occurs, IRR13 is set in all test modes. 

Summary of Contents for Single-Chip Microcomputer SH7203

Page 1: ...Revision Date May 18 2006 32 SH7203Group Hardware Manual Renesas 32 Bit RISC Microcomputer SuperHTM RISC engine Family SH7200 Series Preliminary SH7203 R5S72030W200FP Rev 0 50 REJ09B0313 0050 ...

Page 2: ...Rev 0 50 May 18 2006 Page ii of xxx ...

Page 3: ...s a total system before making a final decision on the applicability of the information and products Renesas Technology Corp assumes no responsibility for any damage liability or other loss resulting from the information contained herein 5 Renesas Technology Corp semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is po...

Page 4: ...ialization Note When power is first supplied the product s state is undefined The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin During the period where the states are undefined the register settings and the output state of each pin are also undefined Design your system so that it does not malfunction because of ...

Page 5: ...ii Input Output Pin iii Register Description iv Operation v Usage Note When designing an application system that includes this LSI take notes into account Each section includes notes in relation to the descriptions given and usage notes are given as required as the final part of each section 7 List of Registers 8 Electrical Characteristics 9 Appendix Product Type Package Dimensions etc 10 Main Rev...

Page 6: ... this LSI to the target users Refer to the SH 2A SH2A FPU Software Manual for a detailed description of the instruction set Notes on reading this manual In order to understand the overall functions of the chip Read the manual according to the contents This manual can be roughly categorized into parts on the CPU system control functions peripheral functions and electrical characteristics In order t...

Page 7: ... name 1 Overall notation 2 Register notation Rev 0 50 10 04 page 416 of 914 14 2 2 Compare Match Control Status Register_0 _1 CMCSR_0 CMCSR_1 14 3 1 Interval Count Operation 4 3 2 Binary numbers are given as B nnnn B may be omitted if the number is obviously binary hexadecimal numbers are given as H nnnn or 0xnnnn and decimal numbers are given as nnnn Examples Binary B 11 or 11 Hexadecimal H EFA0 ...

Page 8: ...icates whether the bit or field is readable or writable or both writing to and reading from the bit or field are impossible The notation is as follows R W R W R W The bit or field is readable and writable The bit or field is readable and writable However writing is only performed to flag clearing The bit or field is readable R is indicated for all reserved bits When writing to the register write t...

Page 9: ...rs 28 2 2 2 Data Formats in Memory 28 2 2 3 Immediate Data Format 29 2 3 Instruction Features 30 2 3 1 RISC Type Instruction Set 30 2 3 2 Addressing Modes 34 2 3 3 Instruction Format 39 2 4 Instruction Set 43 2 4 1 Instruction Set by Classification 43 2 4 2 Data Transfer Instructions 49 2 4 3 Arithmetic Operation Instructions 53 2 4 4 Logic Operation Instructions 56 2 4 5 Shift Instructions 57 2 4...

Page 10: ... Features 81 4 2 Input Output Pins 85 4 3 Clock Operating Modes 86 4 4 Register Descriptions 91 4 4 1 Frequency Control Register FRQCR 91 4 5 Changing the Frequency 94 4 5 1 Changing the Multiplication Rate 94 4 5 2 Changing the Division Ratio 95 4 6 Notes on Board Design 96 4 6 1 Note on Inputting External Clock 96 4 6 2 Note on Using an External Crystal Resonator 96 4 6 3 Note on Resonator 97 4 ...

Page 11: ...ions 118 5 7 When Exception Sources Are Not Accepted 119 5 8 Stack Status after Exception Handling Ends 120 5 9 Usage Notes 122 5 9 1 Value of Stack Pointer SP 122 5 9 2 Value of Vector Base Register VBR 122 5 9 3 Address Errors Caused by Stacking of Address Error Exception Handling 122 Section 6 Interrupt Controller INTC 123 6 1 Features 123 6 2 Input Output Pins 125 6 3 Register Descriptions 126...

Page 12: ...9 Data Transfer with Interrupt Request Signals 167 6 9 1 Handling Interrupt Request Signals as Sources for CPU Interrupt but Not DMAC Activating 168 6 9 2 Handling Interrupt Request Signals as Sources for Activating DMAC but Not CPU Interrupt 168 6 10 Usage Note 169 6 10 1 Timing to Clear an Interrupt Source 169 Section 7 User Break Controller UBC 171 7 1 Features 171 7 2 Input Output Pin 173 7 3 ...

Page 13: ...es 211 8 4 4 Notes 211 Section 9 Bus State Controller BSC 213 9 1 Features 213 9 2 Input Output Pins 216 9 3 Area Overview 218 9 3 1 Address Map 218 9 3 2 Data Bus Width and Pin Function Setting in Each Area 219 9 4 Register Descriptions 220 9 4 1 Common Control Register CMNCR 221 9 4 2 CSn Space Bus Control Register CSnBCR n 0 to 7 224 9 4 3 CSn Space Wait Control Register CSnWCR n 0 to 7 229 9 4...

Page 14: ...ess Registers SAR 379 10 3 2 DMA Destination Address Registers DAR 380 10 3 3 DMA Transfer Count Registers DMATCR 380 10 3 4 DMA Channel Control Registers CHCR 381 10 3 5 DMA Reload Source Address Registers RSAR 390 10 3 6 DMA Reload Destination Address Registers RDAR 391 10 3 7 DMA Reload Transfer Count Registers RDMATCR 392 10 3 8 DMA Operation Register DMAOR 393 10 3 9 DMA Extension Resource Se...

Page 15: ...RWER 478 11 3 17 Timer Output Master Enable Register TOER 479 11 3 18 Timer Output Control Register 1 TOCR1 480 11 3 19 Timer Output Control Register 2 TOCR2 483 11 3 20 Timer Output Level Buffer Register TOLBR 486 11 3 21 Timer Gate Control Register TGCR 487 11 3 22 Timer Subcounter TCNTS 489 11 3 23 Timer Dead Time Data Register TDDR 490 11 3 24 Timer Cycle Data Register TCDR 490 11 3 25 Timer C...

Page 16: ...nd Input Capture 597 11 7 11 Contention between Buffer Register Write and Input Capture 598 11 7 12 TCNT2 Write and Overflow Underflow Contention in Cascade Connection 598 11 7 13 Counter Value during Complementary PWM Mode Stop 600 11 7 14 Buffer Operation Setting in Complementary PWM Mode 600 11 7 15 Reset Sync PWM Mode Buffer Operation and Compare Match Flag 601 11 7 16 Overflow Flags in Reset ...

Page 17: ...nd Compare Match Processes of CMCNT 648 12 5 2 Conflict between Word Write and Count Up Processes of CMCNT 649 12 5 3 Conflict between Byte Write and Count Up Processes of CMCNT 650 Section 13 Watchdog Timer WDT 651 13 1 Features 651 13 2 Input Output Pin 653 13 3 Register Descriptions 654 13 3 1 Watchdog Timer Counter WTCNT 654 13 3 2 Watchdog Timer Control Status Register WTCSR 655 13 3 3 Watchd...

Page 18: ...AYAR 683 14 3 14 Month Alarm Register RMONAR 684 14 3 15 Year Alarm Register RYRAR 685 14 3 16 RTC Control Register 1 RCR1 686 14 3 17 RTC Control Register 2 RCR2 688 14 3 18 RTC Control Register 3 RCR3 690 14 4 Operation 691 14 4 1 Initial Settings of Registers after Power On 691 14 4 2 Setting Time 691 14 4 3 Reading Time 692 14 4 4 Alarm Function 693 14 5 Usage Notes 694 14 5 1 Register Writing...

Page 19: ...SCFTDR Writing and TDFE Flag 762 15 6 2 SCFRDR Reading and RDF Flag 762 15 6 3 Restriction on DMAC Usage 763 15 6 4 Break Detection and Processing 763 15 6 5 Sending a Break Signal 763 15 6 6 Receive Data Sampling Timing and Receive Margin Asynchronous Mode 763 15 6 7 Selection of Base Clock in Asynchronous Mode 765 Section 16 Synchronous Serial Communication Unit SSU 767 16 1 Features 767 16 2 In...

Page 20: ...ster 2 ICCR2 814 17 3 3 I2 C Bus Mode Register ICMR 816 17 3 4 I2 C Bus Interrupt Enable Register ICIER 818 17 3 5 I2 C Bus Status Register ICSR 820 17 3 6 Slave Address Register SAR 823 17 3 7 I2 C Bus Transmit Data Register ICDRT 823 17 3 8 I2 C Bus Receive Data Register ICDRR 824 17 3 9 I2 C Bus Shift Register ICDRS 824 17 3 10 NF2CYC Register NF2CYC 825 17 4 Operation 826 17 4 1 I2 C Bus Forma...

Page 21: ... 18 5 2 Note on Using Oversampling Clock 884 Section 19 Controller Area Network RCAN TL1 885 19 1 Summary 885 19 1 1 Overview 885 19 1 2 Scope 885 19 1 3 Audience 885 19 1 4 References 885 19 1 5 Features 886 19 2 Architecture 887 19 3 Programming Model Overview 890 19 3 1 Memory Map 890 19 3 2 Mailbox Structure 892 19 3 3 RCAN TL1 Control Registers 909 19 3 4 RCAN TL1 Mailbox Registers 930 19 3 5...

Page 22: ...Timing 1010 20 5 Interrupt Sources and DMAC Transfer Request 1011 20 6 Definitions of A D Conversion Accuracy 1012 20 7 Usage Notes 1013 20 7 1 Module Standby Mode Setting 1013 20 7 2 Setting Analog Input Voltage 1013 20 7 3 Notes on Board Design 1013 20 7 4 Processing of Analog Input Pins 1014 20 7 5 Permissible Signal Source Impedance 1015 20 7 6 Influences on Absolute Precision 1016 Section 21 ...

Page 23: ...gister FLECFIFO 1051 22 3 13 Transfer Control Register FLTRCR 1053 22 4 Operation 1054 22 4 1 Access Sequence 1054 22 4 2 Operating Modes 1055 22 4 3 Register Setting Procedure 1056 22 4 4 Command Access Mode 1057 22 4 5 Sector Access Mode 1062 22 4 6 ECC Error Correction 1064 22 4 7 Status Read 1065 22 5 Interrupt Sources 1067 22 6 DMA Transfer Specifications 1068 Section 23 USB 2 0 Host Function...

Page 24: ...ADDR 1118 23 3 24 USB Request Type Register USBREQ 1119 23 3 25 USB Request Value Register USBVAL 1120 23 3 26 USB Request Index Register USBINDX 1120 23 3 27 USB Request Length Register USBLENG 1121 23 3 28 DCP Configuration Register DCPCFG 1122 23 3 29 DCP Maximum Packet Size Register DCPMAXP 1124 23 3 30 DCP Control Register DCPCTR 1125 23 3 31 Pipe Window Select Register PIPESEL 1127 23 3 32 P...

Page 25: ... LDVTLNR 1218 24 3 14 LCDC Vertical Sync Signal Register LDVSYNR 1219 24 3 15 LCDC AC Modulation Signal Toggle Line Number Register LDACLNR 1220 24 3 16 LCDC Interrupt Control Register LDINTR 1221 24 3 17 LCDC Power Management Mode Register LDPMMR 1224 24 3 18 LCDC Power Supply Sequence Period Register LDPSPR 1226 24 3 19 LCDC Control Register LDCNTR 1228 24 3 20 LCDC User Specified Interrupt Cont...

Page 26: ...FCRL1 to PFCRL4 1310 25 2 11 IRQOUT Function Control Register IFCR 1324 25 2 12 SSI Oversampling Clock Selection Register SCSR 1325 25 3 Switching Pin Function of Port A 1327 25 4 Usage Notes 1328 Section 26 I O Ports 1329 26 1 Features 1329 26 2 Port A 1330 26 2 1 Register Descriptions 1330 26 2 2 Port A Data Register L PADRL 1330 26 3 Port B 1332 26 3 1 Register Descriptions 1332 26 3 2 Port B D...

Page 27: ...l Register 2 STBCR2 1366 28 2 3 Standby Control Register 3 STBCR3 1367 28 2 4 Standby Control Register 4 STBCR4 1369 28 2 5 Standby Control Register 5 STBCR5 1371 28 2 6 Standby Control Register 6 STBCR6 1373 28 2 7 System Control Register 1 SYSCR1 1375 28 2 8 System Control Register 2 SYSCR2 1377 28 2 9 System Control Register 3 SYSCR3 1378 28 2 10 Deep Standby Control Register DSCTR 1380 28 2 11...

Page 28: ...ng section numbers 1408 30 2 Register Bits 1431 30 3 Register States in Each Operating Mode 1479 Section 31 Electrical Characteristics 1483 31 1 Absolute Maximum Ratings 1483 31 2 Power on Power off Sequence 1484 31 3 DC Characteristics 1485 31 4 AC Characteristics 1493 31 4 1 Clock Timing 1494 31 4 2 Control Signal Timing 1498 31 4 3 Bus Timing 1501 31 4 4 UBC Trigger Timing 1536 31 4 5 DMAC Modu...

Page 29: ...Module Timing 1560 31 4 17 I O Port Timing 1562 31 4 18 H UDI Related Pin Timing 1563 31 4 19 AC Characteristics Measurement Conditions 1565 31 5 A D Converter Characteristics 1566 31 6 D A Converter Characteristics 1567 Appendix 1569 A Pin States 1569 B Package Dimensions 1575 Index 1577 ...

Page 30: ...Rev 0 50 May 18 2006 Page xxx of xxx ...

Page 31: ...stics This LSI has a floating point unit FPU and cache In addition this LSI includes on chip peripheral functions necessary for system configuration such as 64 Kbyte RAM for high speed operation 16 Kbyte RAM for data retention a multi function timer pulse unit 2 MTU2 a compare match timer CMT a realtime clock RTC a serial communication interface with FIFO SCIF a synchronous serial communication un...

Page 32: ...egisters Register bank for high speed response to interrupts RISC type instruction set upward compatible with SH series Instruction length 16 bit fixed length basic instructions for improved code efficiency and 32 bit instructions for high performance and usability Load store architecture Delayed branch instructions Instruction set based on C language Superscalar architecture to execute two instru...

Page 33: ...DI1 load constant 0 1 instructions Instruction execution time Latency FAMC FADD FSUB FMUL Three cycles single precision eight cycles double precision Pitch FAMC FADD FSUB FMUL One cycle single precision six cycles double precision Note FMAC only supports single precision Five stage pipeline Cache memory Instruction cache 8 Kbytes Operand cache 8 Kbytes 128 entry 4 way set associative 16 byte block...

Page 34: ... MPX I O interface are also available PCMCIA interface Outputs a chip select signal CS0 to CS7 according to the target area CS assert or negate timing can be selected by software SDRAM refresh Auto refresh or self refresh mode selectable SDRAM burst access Direct memory access controller DMAC Eight channels external request available for four of them Can be activated by on chip peripheral modules ...

Page 35: ...y PWM output mode Non overlapping waveforms output for 3 phase inverter control Automatic dead time setting 0 to 100 PWM duty value specifiable A D converter start request delaying function Interrupt skipping at crest or trough Reset synchronized PWM mode Three phase PWM waveforms in positive and negative phases can be output with a required duty value Phase counting mode Two phase encoder pulse c...

Page 36: ...uplex communication transmission and reception executed simultaneously Consecutive serial communication Two channels I 2 C bus interface 3 IIC3 Four channels Master mode and slave mode supported Serial sound interface SSI Four channel bidirectional serial transfer Support of various real audio formats Support of master and slave functions Generation of programmable word clock and bit clock Multi c...

Page 37: ...controller LCDC From 16 1 to 1024 1024 dots supported 8 bpp bit per pixel 640 480 max 16 bpp bit per pixel 400 240 max Supports 4 8 15 16 bpp color modes Supports 1 2 4 6 bpp gray scale modes TFT DSTN STN panels supported Signal polarity setting function 24 bit color pallet memory 16 of the 24 bits are valid R 5 G 6 B 5 Unified graphics memory architecture I O ports 82 I Os 16 inputs and 1 output ...

Page 38: ... 8 of 1588 REJ09B0313 0050 Items Specification On chip RAM 64 Kbyte memory for high speed operation 16 Kbytes 4 16 Kbyte memory for data retention 4 Kbytes 4 Power supply voltage Vcc 1 1 to 1 3 V PVcc 3 0 to 3 6 V Packages QFP3232 240Cu 0 5 pitch ...

Page 39: ...Section 1 Overview Rev 0 50 May 18 2006 Page 9 of 1588 REJ09B0313 0050 1 2 Product Lineup Table 1 2 Product Lineup Product Classification Product Code Package SH7203 R5S72030W200FP QFP3232 240Cu ...

Page 40: ...y controller FLCTL Port Flash memory I F I O D A converter DAC Port Analog output A D converter ADC Port Analog input ADTRG input Controller area network RCAN TL1 Port CAN bus I O Serial sound interface SSI Port Serial I O Audio clock input Serial communication interface with FIFO SCIF Port Serial I O Watchdog timer WDT Port WDTOVF output Realtime clock RTC Port RTC_X1 input RTC_X2 output Internal...

Page 41: ... CKE PC11 CASU BREQ AUDATA1 PC10 RASU BACK AUDATA0 PC9 CASL PC8 RASL Vcc PC7 WE3 DQMUU AH ICIOWR Vss PVss PC6 WE2 DQMUL ICIORD PVcc PC5 WE1 DQMLU WR CS0 RD PC4 WE0 DQMLL PC3 CS3 PC2 CS2 Vcc PC0 A0 CS7 AUDSYNC Vss PVss PC1 A1 PVcc A2 A3 A4 A5 A6 A7 A8 PVcc A9 PVss Vss A10 Vcc A11 A12 A13 A14 A15 A16 PVss A17 PVcc A18 A19 A20 PE2 A21 SCK0 PE3 A22 SCK1 PE0 BS RxD0 ADTRG CKIO Vcc Vss PVss PVcc XTAL EX...

Page 42: ...All the PVcc pins must be connected to the system power supply This LSI does not operate correctly if there is a pin left open PVss I Ground for I O circuits Ground pins for I O pins All the PVss pins must be connected to the system power supply 0 V This LSI does not operate correctly if there is a pin left open PLLVcc I Power supply for PLL Power supply for the on chip PLL oscillator Power supply...

Page 43: ...de To operate it in debugging mode apply a low level to this pin on the user system board RES I Power on reset This LSI enters the power on reset state when this signal goes low MRES I Manual reset This LSI enters the manual reset state when this signal goes low WDTOVF O Watchdog timer overflow Outputs an overflow signal from the WDT BREQ I Bus mastership request A low level is input to this pin w...

Page 44: ...s occurred enabling external devices to be informed of an interrupt occurrence even while the bus mastership is released Address bus A25 to A0 O Address bus Outputs addresses Data bus D31 to D0 I O Data bus Bidirectional data bus CS7 to CS0 O Chip select 7 to 0 Chip select signals for external memory or devices RD O Read Indicates that data is read from an external device RD WR O Read write Read w...

Page 45: ...Selects bits D31 to D24 when SDRAM is connected RASU RASL O RAS Connected to the RAS pin when SDRAM is connected CASU CASL O CAS Connected to the CAS pin when SDRAM is connected CKE O CK enable Connected to the CKE pin when SDRAM is connected CE1A CE1B O Lower byte select for PCMCIA card Connected to PCMCIA card select signals D7 to D0 CE2A CE2B O Upper byte select for PCMCIA card Connected to PCM...

Page 46: ...C0D I O MTU2 input capture output compare channel 0 The TGRA_0 to TGRD_0 input capture input output compare output PWM output pins TIOC1A TIOC1B I O MTU2 input capture output compare channel 1 The TGRA_1 and TGRB_1 input capture input output compare output PWM output pins TIOC2A TIOC2B I O MTU2 input capture output compare channel 2 The TGRA_2 and TGRB_2 input capture input output compare output P...

Page 47: ...CL3 to SCL0 I O Serial clock pin Serial clock I O pin I 2 C bus interface 3 IIC3 SDA3 to SDA0 I O Serial data pin Serial data I O pin SSIDATA3 to SSIDATA0 I O SSI data I O I O pins for serial data SSISCK3 to SSISCK0 I O SSI clock I O I O pins for serial clocks SSIWS3 to SSIWS0 I O SSI clock LR I O I O pins for word selection AUDIO_CLK I External clock for SSI audio Input pin of external clock for ...

Page 48: ...Flash memory serial clock Read enable Reads data at falling edge Serial clock Inputs outputs data in synchronization with the signal FCE O Flash memory chip enable Chip enable Enables the flash memory connected to this LSI FCDE O Flash memory command data enable Command latch enable Asserted at command output Command data enable Asserted at command output FRB I Flash memory ready busy Ready busy H...

Page 49: ...gnal may also be input to the USB_X1 pin USBAPVcc I Power supply for transceiver analog pins Power supply for pins USBAPVss I Ground for transceiver analog pins Ground for pins USBDPVcc I Power supply for transceiver digital pins Power supply for pins USBDPVss I Ground for transceiver digital pins Ground for pins USBAVcc I Power supply for transceiver analog core Power supply for core USBAVss I Gr...

Page 50: ...DISP O LCD current alternation LCD current alternating signal pin AN7 to AN0 I Analog input pins Analog input pins A D converter ADC ADTRG I A D conversion trigger input External trigger input pin for starting A D conversion D A converter DAC DA1 DA0 O Analog output pins Analog output pins AVcc I Analog power supply Power supply pins for the A D converter and D A converter AVss I Analog ground Gro...

Page 51: ...ebugging interface H UDI TRST I Test reset Initialization signal input pin AUDATA3 to AUDATA0 O AUD data Branch source or destination address output pins AUDCK O AUD clock Sync clock output pin AUDSYNC O AUD sync signal Data start position acknowledge signal output pin ASEBRKAK O Break mode acknowledge Indicates that the E10A USB emulator has entered its break mode Emulator interface ASEBRK I Brea...

Page 52: ...Section 1 Overview Rev 0 50 May 18 2006 Page 22 of 1588 REJ09B0313 0050 ...

Page 53: ...er Several instructions have R0 fixed as their only usable register R15 is used as the hardware stack pointer SP Saving and restoring the status register SR and program counter PC in exception handling is accomplished by referencing the stack using R15 31 0 R0 1 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP hardware stack pointer 2 Notes 1 R0 functions as an index register in the indexed r...

Page 54: ...egister functions as the base address of the exception handling vector area including interrupts The jump table base register functions as the base address of the function table area 31 0 1 T S 2 3 4 5 6 7 8 9 I 3 0 Q M 13 14 CS BO Status register SR 31 0 GBR Global base register GBR 31 VBR Vector base register VBR 0 31 TBR Jump table base register TBR 0 Figure 2 2 Control Registers 1 Status Regis...

Page 55: ... M R W 8 Q R W M Bit Q Bit Used by the DIV0S DIV0U and DIV1 instructions 7 to 4 I 3 0 1111 R W Interrupt Mask Level 3 2 All 0 R Reserved These bits are always read as 0 The write value should always be 0 1 S R W S Bit Specifies a saturation operation for a MAC instruction 0 T R W T Bit True false condition or carry borrow bit 2 Global Base Register GBR GBR is referenced as the base address in a GB...

Page 56: ...h MACH and multiply and accumulate register low MACL Store the results of multiply or multiply and accumulate operations Procedure register PR Stores the return address from a subroutine procedure Program counter PC Indicates the four bytes ahead of the current instruction 0 Figure 2 3 System Registers 1 Multiply and Accumulate Register High MACH and Multiply and Accumulate Register Low MACL MACH ...

Page 57: ... a RESBANK instruction in an interrupt processing routine This LSI has 15 banks For details see the SH 2A SH2A FPU Software Manual and section 6 8 Register Banks 2 1 5 Initial Values of Registers Table 2 1 lists the values of the registers after a reset Table 2 1 Initial Values of Registers Classification Register Initial Value R0 to R14 Undefined General registers R15 SP Value of the stack pointe...

Page 58: ...ytes 16 bit words or 32 bit longwords A memory operand of fewer than 32 bits is stored in a register in sign extended or zero extended form A word operand should be accessed at a word boundary an even address of multiple of two bytes address 2n and a longword operand at a longword boundary an even address of multiple of four bytes address 4n Otherwise an address error will occur A byte operand can...

Page 59: ...its of the destination register 20 bit immediate data is located in the code of a MOVI20 or MOVI20S 32 bit transfer instruction The MOVI20 instruction stores immediate data in the destination register in sign extended form The MOVI20S instruction shifts immediate data by eight bits in the upper direction and stores it in the destination register in sign extended form Word or longword immediate dat...

Page 60: ...ions Memory can be accessed in bytes words or longwords Byte or word data in memory is sign extended and handled as longword data Immediate data is sign extended for arithmetic operations or zero extended for logic operations It is also handled as longword data Table 2 2 Sign Extension of Word Data SH2 A CPU Description Example of Other CPU MOV W disp PC R1 ADD R1 R0 DATA W H 1234 Data is sign ext...

Page 61: ...ontents prior to the change Table 2 3 Delayed Branch Instructions SH 2A CPU Description Example of Other CPU BRA TRGET ADD R1 R0 Executes the ADD before branching to TRGET ADD W R1 R0 BRA TRGET 7 Unconditional Branch Instructions with No Delay Slot The SH 2A additionally features unconditional branch instructions in which a delay slot instruction is not executed This eliminates unnecessary NOP ins...

Page 62: ...but in a memory table The memory table is accessed by an immediate data transfer instruction MOV using the PC relative addressing mode with displacement With the SH 2A 17 to 28 bit immediate data can be located in an instruction code However for 21 to 28 bit immediate data an OR instruction must be executed after the data is transferred to a register Table 2 5 Immediate Data Accessing Classificati...

Page 63: ...28 bits an OR instruction must be used after the data is transferred to a register Table 2 6 Absolute Address Accessing Classification SH 2A CPU Example of Other CPU Up to 20 bits MOVI20 H 12345 R1 MOV B R1 R0 MOV B H 12345 R0 21 to 28 bits MOVI20S H 12345 R1 OR H 67 R1 MOV B R1 R0 MOV B H 1234567 R0 29 bits or more MOV L disp PC R1 MOV B R1 R0 DATA L H 12345678 MOV B H 12345678 R0 12 16 Bit 32 Bi...

Page 64: ...ndirect with post increment Rn The effective address is the contents of register Rn A constant is added to the contents of Rn after the instruction is executed 1 is added for a byte operation 2 for a word operation and 4 for a longword operation Rn Rn 1 2 4 Rn 1 2 4 Rn After instruction execution Byte Rn 1 Rn Word Rn 2 Rn Longword Rn 4 Rn Register indirect with pre decrement Rn The effective addre...

Page 65: ...disp 4 Register indirect with displacement disp 12 Rn The effective address is the sum of Rn and a 12 bit displacement disp The value of disp is zero extended Rn disp zero extended Rn disp Byte Rn disp Word Rn disp Longword Rn disp Indexed register indirect R0 Rn The effective address is the sum of Rn and R0 Rn R0 Rn R0 Rn R0 GBR indirect with displacement disp 8 GBR The effective address is the s...

Page 66: ...disp The value of disp is zero extended and is multiplied by 4 TBR TBR disp 4 TBR disp 4 4 disp zero extended Contents of address TBR disp 4 PC indirect with displacement disp 8 PC The effective address is the sum of PC value and an 8 bit displacement disp The value of disp is zero extended and is doubled for a word operation and quadrupled for a longword operation For a longword operation the low...

Page 67: ...f PC value and the value that is obtained by doubling the sign extended 8 bit displacement disp PC 2 disp sign extended PC disp 2 PC disp 2 disp 12 The effective address is the sum of PC value and the value that is obtained by doubling the sign extended 12 bit displacement disp PC 2 disp sign extended PC disp 2 PC disp 2 Rn The effective address is the sum of PC value and Rn PC Rn PC Rn PC Rn ...

Page 68: ...t bits to the left the upper bits are sign extended and the lower bits are padded with zero Sign extended imm 20 bits 00000000 31 27 8 0 imm 8 The 8 bit immediate data imm for the TST AND OR and XOR instructions is zero extended imm 8 The 8 bit immediate data imm for the MOV ADD and CMP EQ instructions is sign extended imm 8 The 8 bit immediate data imm for the TRAPA instruction is zero extended a...

Page 69: ...ormats Instruction Formats Source Operand Destination Operand Example 0 format xxxx xxxx xxxx xxxx 15 0 NOP nnnn Register direct MOVT Rn Control register or system register nnnn Register direct STS MACH Rn R0 Register direct nnnn Register direct DIVU R0 Rn Control register or system register nnnn Register indirect with pre decrement STC L SR Rn mmmm Register direct R15 Register indirect with pre d...

Page 70: ...ng Rm BRAF Rm mmmm Register direct nnnn Register direct ADD Rm Rn mmmm Register direct nnnn Register indirect MOV L Rm Rn mmmm Register indirect with post increment multiply and accumulate nnnn Register indirect with post increment multiply and accumulate MACH MACL MAC W Rm Rn mmmm Register indirect with post increment nnnn Register direct MOV L Rm Rn mmmm Register direct nnnn Register indirect wi...

Page 71: ... L Rm disp12 Rn nmd12 format xxxx dddd dddd dddd 15 0 xxxx mmmm xxxx nnnn 32 16 mmmmdddd Register indirect with displacement nnnn Register direct MOV L disp12 Rm Rn dddddddd GBR indirect with displacement R0 Register direct MOV L disp GBR R0 R0 Register direct dddddddd GBR indirect with displacement MOV L R0 disp GBR dddddddd PC relative with displacement R0 Register direct MOVA disp PC R0 ddddddd...

Page 72: ...imm Rn nnnn Register direct iii Immediate BLD imm3 Rn ni3 format xxxx nnnn xxxx 15 0 iii x nnnn Register direct iii Immediate BST imm3 Rn ni20 format iiii iiii iiii iiii 15 0 xxxx iiii xxxx nnnn 32 16 iiiiiiiiiiiiiiiiiiii Immediate nnnn Register direct MOVI20 imm20 Rn nnnndddddddddddd Register indirect with displacement iii Immediate BLD B imm3 disp12 Rn nid format xxxx dddd dddd dddd 15 0 xxxx xi...

Page 73: ...ransfer Peripheral module data transfer Structure data transfer Reverse stack transfer MOVA Effective address transfer MOVI20 20 bit immediate data transfer MOVI20S 20 bit immediate data transfer 8 bit left shit MOVML R0 Rn register save restore MOVMU Rn R14 and PR register save restore MOVRT T bit inversion and transfer to Rn MOVT T bit transfer MOVU Unsigned data transfer NOTT T bit inversion PR...

Page 74: ...erations DIV0S Initialization of signed one step division DIV0U Initialization of unsigned one step division DMULS Signed double precision multiplication DMULU Unsigned double precision multiplication DT Decrement and test EXTS Sign extension EXTU Zero extension MAC Multiply and accumulate double precision multiply and accumulate operation MUL Double precision multiply operation MULR Signed multip...

Page 75: ...ic right shift SHLD Dynamic logical shift SHLL One bit logical left shift SHLLn n bit logical left shift SHLR One bit logical right shift SHLRn n bit logical right shift Branch 10 BF Conditional branch conditional delayed branch branch when T 0 15 BT Conditional branch conditional delayed branch branch when T 1 BRA Unconditional delayed branch BRAF Unconditional delayed branch BSR Delayed branch t...

Page 76: ...nk entry STC Store control register data STS Store system register data TRAPA Trap exception handling 19 FABS Floating point absolute value 48 Floating point instructions FADD Floating point addition FCMP Floating point comparison FCNVDS Conversion from double precision to single precision FCNVSD Conversion from single precision to double precision FDIV Floating point division FLDI0 Floating point...

Page 77: ...t store from system register FPUL FSUB Floating point subtraction FTRC Floating point conversion with rounding to integer LDS Load into floating point system register FPU related CPU instructions 2 STS Store from floating point system register 8 10 BAND Bit AND 14 Bit manipulation BCLR Bit clear BLD Bit load BOR Bit OR BSET Bit set BST Bit store BXOR Bit exclusive OR BANDNOT Bit NOT AND BORNOT Bit...

Page 78: ... operand M Q T Flag bits in SR Logical AND of each bit Logical OR of each bit Exclusive logical OR of each bit Logical NOT of each bit n n bit left shift n n bit right shift Value when no wait states are inserted 1 Value of T bit after instruction is executed Explanation of Symbols No change Notes 1 Instruction execution cycles The execution cycles shown in the table are minimums In practice the n...

Page 79: ... Rn 1 Yes Yes Yes MOV L Rm Rn 0110nnnnmmmm0010 Rm Rn 1 Yes Yes Yes MOV B Rm Rn 0010nnnnmmmm0100 Rn 1 Rn Rm Rn 1 Yes Yes Yes MOV W Rm Rn 0010nnnnmmmm0101 Rn 2 Rn Rm Rn 1 Yes Yes Yes MOV L Rm Rn 0010nnnnmmmm0110 Rn 4 Rn Rm Rn 1 Yes Yes Yes MOV B Rm Rn 0110nnnnmmmm0100 Rm sign extension Rn Rm 1 Rm 1 Yes Yes Yes MOV W Rm Rn 0110nnnnmmmm0101 Rm sign extension Rn Rm 2 Rm 1 Yes Yes Yes MOV L Rm Rn 0110nn...

Page 80: ...1 Yes Yes Yes MOV W disp GBR R0 11000101dddddddd disp 2 GBR sign extension R0 1 Yes Yes Yes MOV L disp GBR R0 11000110dddddddd disp 4 GBR R0 1 Yes Yes Yes MOV B R0 Rn 0100nnnn10001011 R0 Rn Rn 1 Rn 1 Yes MOV W R0 Rn 0100nnnn10011011 R0 Rn Rn 2 Rn 1 Yes MOV L R0 Rn 0100nnnn10101011 R0 Rn Rn 4 Rn 1 Yes MOV B Rm R0 0100mmmm11001011 Rm 1 Rm Rm sign extension R0 1 Yes MOV W Rm R0 0100mmmm11011011 Rm 2 ...

Page 81: ...iii imm 8 sign extension Rn 1 Yes MOVML L Rm R15 0100mmmm11110001 R15 4 R15 Rm R15 R15 4 R15 Rm 1 R15 R15 4 R15 R0 R15 Note When Rm R15 read Rm as PR 1 to 16 Yes MOVML L R15 Rn 0100nnnn11110101 R15 R0 R15 4 R15 R15 R1 R15 4 R15 R15 Rn Note When Rn R15 read Rn as PR 1 to 16 Yes MOVMU L Rm R15 0100mmmm11110000 R15 4 R15 PR R15 R15 4 R15 R14 R15 R15 4 R15 Rm R15 Note When Rm R15 read Rm as PR 1 to 16...

Page 82: ...ero extension Rn 1 Yes MOVU W disp12 Rm Rn 0011nnnnmmmm0001 1001dddddddddddd disp 2 Rm zero extension Rn 1 Yes NOTT 0000000001101000 T T 1 Ope ration result Yes PREF Rn 0000nnnn10000011 Rn operand cache 1 Yes Yes SWAP B Rm Rn 0110nnnnmmmm1000 Rm swap lower 2 bytes Rn 1 Yes Yes Yes SWAP W Rm Rn 0110nnnnmmmm1001 Rm swap upper and lower words Rn 1 Yes Yes Yes XTRCT Rm Rn 0010nnnnmmmm1101 Middle 32 bi...

Page 83: ... Yes CMP EQ Rm Rn 0011nnnnmmmm0000 When Rn Rm 1 T Otherwise 0 T 1 Com parison result Yes Yes Yes CMP HS Rm Rn 0011nnnnmmmm0010 When Rn Rm unsigned 1 T Otherwise 0 T 1 Com parison result Yes Yes Yes CMP GE Rm Rn 0011nnnnmmmm0011 When Rn Rm signed 1 T Otherwise 0 T 1 Com parison result Yes Yes Yes CMP HI Rm Rn 0011nnnnmmmm0110 When Rn Rm unsigned 1 T Otherwise 0 T 1 Com parison result Yes Yes Yes CM...

Page 84: ...m 1 Calcu lation result Yes Yes Yes DIV0S Rm Rn 0010nnnnmmmm0111 MSB of Rn Q MSB of Rm M M Q T 1 Calcu lation result Yes Yes Yes DIV0U 0000000000011001 0 M Q T 1 0 Yes Yes Yes DIVS R0 Rn 0100nnnn10010100 Signed operation of Rn R0 Rn 32 32 32 bits 36 Yes DIVU R0 Rn 0100nnnn10000100 Unsigned operation of Rn R0 Rn 32 32 32 bits 34 Yes DMULS L Rm Rn 0011nnnnmmmm1101 Signed operation of Rn Rm MACH MACL...

Page 85: ...Rn Rm MAC MAC 16 16 64 64 bits 3 Yes Yes Yes MUL L Rm Rn 0000nnnnmmmm0111 Rn Rm MACL 32 32 32 bits 2 Yes Yes Yes MULR R0 Rn 0100nnnn10000000 R0 Rn Rn 32 32 32 bits 2 Yes MULS W Rm Rn 0010nnnnmmmm1111 Signed operation of Rn Rm MACL 16 16 32 bits 1 Yes Yes Yes MULU W Rm Rn 0010nnnnmmmm1110 Unsigned operation of Rn Rm MACL 16 16 32 bits 1 Yes Yes Yes NEG Rm Rn 0110nnnnmmmm1011 0 Rm Rn 1 Yes Yes Yes N...

Page 86: ... Yes Yes OR imm R0 11001011iiiiiiii R0 imm R0 1 Yes Yes Yes OR B imm R0 GBR 11001111iiiiiiii R0 GBR imm R0 GBR 3 Yes Yes Yes TAS B Rn 0100nnnn00011011 When Rn is 0 1 T Otherwise 0 T 1 MSB of Rn 3 Test result Yes Yes Yes TST Rm Rn 0010nnnnmmmm1000 Rn Rm When the result is 0 1 T Otherwise 0 T 1 Test result Yes Yes Yes TST imm R0 11001000iiiiiiii R0 imm When the result is 0 1 T Otherwise 0 T 1 Test r...

Page 87: ...00nnnnmmmm1100 When Rm 0 Rn Rm Rn When Rm 0 Rn Rm MSB Rn 1 Yes Yes SHAL Rn 0100nnnn00100000 T Rn 0 1 MSB Yes Yes Yes SHAR Rn 0100nnnn00100001 MSB Rn T 1 LSB Yes Yes Yes SHLD Rm Rn 0100nnnnmmmm1101 When Rm 0 Rn Rm Rn When Rm 0 Rn Rm 0 Rn 1 Yes Yes SHLL Rn 0100nnnn00000000 T Rn 0 1 MSB Yes Yes Yes SHLR Rn 0100nnnn00000001 0 Rn T 1 LSB Yes Yes Yes SHLL2 Rn 0100nnnn00001000 Rn 2 Rn 1 Yes Yes Yes SHLR2...

Page 88: ...2 PC PC When T 0 nop 2 1 Yes Yes Yes BRA label 1010dddddddddddd Delayed branch disp 2 PC PC 2 Yes Yes Yes BRAF Rm 0000mmmm00100011 Delayed branch Rm PC PC 2 Yes Yes Yes BSR label 1011dddddddddddd Delayed branch PC PR disp 2 PC PC 2 Yes Yes Yes BSRF Rm 0000mmmm00000011 Delayed branch PC PR Rm PC PC 2 Yes Yes Yes JMP Rm 0100mmmm00101011 Delayed branch Rm PC 2 Yes Yes Yes JSR Rm 0100mmmm00001011 Dela...

Page 89: ... GBR 0100mmmm00010111 Rm GBR Rm 4 Rm 1 Yes Yes Yes LDC L Rm VBR 0100mmmm00100111 Rm VBR Rm 4 Rm 1 Yes Yes Yes LDS Rm MACH 0100mmmm00001010 Rm MACH 1 Yes Yes Yes LDS Rm MACL 0100mmmm00011010 Rm MACL 1 Yes Yes Yes LDS Rm PR 0100mmmm00101010 Rm PR 1 Yes Yes Yes LDS L Rm MACH 0100mmmm00000110 Rm MACH Rm 4 Rm 1 Yes Yes Yes LDS L Rm MACL 0100mmmm00010110 Rm MACL Rm 4 Rm 1 Yes Yes Yes LDS L Rm PR 0100mmm...

Page 90: ... Yes STS PR Rn 0000nnnn00101010 PR Rn 1 Yes Yes Yes STS L MACH Rn 0100nnnn00000010 Rn 4 Rn MACH Rn 1 Yes Yes Yes STS L MACL Rn 0100nnnn00010010 Rn 4 Rn MACL Rn 1 Yes Yes Yes STS L PR Rn 0100nnnn00100010 Rn 4 Rn PR Rn 1 Yes Yes Yes TRAPA imm 11000011iiiiiiii PC SR stack area imm 4 VBR PC 5 Yes Yes Yes Notes 1 Instruction execution cycles The execution cycles shown in the table are minimums In pract...

Page 91: ...T FRm FRn 1111nnnnmmmm0101 FRn FRm 1 0 T 1 Compa rison result Yes Yes Yes FCMP GT DRm DRn 1111nnn0mmm00101 DRn DRm 1 0 T 2 Compa rison result Yes Yes FCNVDS DRm FPUL 1111mmm010111101 float DRm FPUL 2 Yes Yes FCNVSD FPUL DRn 1111nnn010101101 double FPUL DRn 2 Yes Yes FDIV FRm FRn 1111nnnnmmmm0011 FRn FRm FRn 10 Yes Yes Yes FDIV DRm DRn 1111nnn0mmm00011 DRn DRm DRn 23 Yes Yes FLDI0 FRn 1111nnnn10001...

Page 92: ...Rn 1 Yes Yes Yes FMOV D DRm R0 Rn 1111nnnnmmm00111 DRm R0 Rn 2 Yes Yes FMOV S FRm Rn 1111nnnnmmmm1011 Rn 4 FRm Rn 1 Yes Yes Yes FMOV D DRm Rn 1111nnnnmmm01011 Rn 8 DRm Rn 2 Yes Yes FMOV S FRm Rn 1111nnnnmmmm1010 FRm Rn 1 Yes Yes Yes FMOV D DRm Rn 1111nnnnmmm01010 DRm Rn 2 Yes Yes FMOV S FRm disp12 Rn 0011nnnnmmmm0001 0011dddddddddddd FRm disp 4 Rn 1 Yes FMOV D DRm disp12 Rn 0011nnnnmmm00001 0011dd...

Page 93: ... 18 FPU Related CPU Instructions Compatibility Instruction Instruction Code Operation Execu tion Cycles T Bit SH2E SH4 SH 2A SH2A FPU LDS Rm FPSCR 0100mmmm01101010 Rm FPSCR 1 Yes Yes Yes LDS Rm FPUL 0100mmmm01011010 Rm FPUL 1 Yes Yes Yes LDS L Rm FPSCR 0100mmmm01100110 Rm FPSCR Rm 4 1 Yes Yes Yes LDS L Rm FPUL 0100mmmm01010110 Rm FPUL Rm 4 1 Yes Yes Yes STS FPSCR Rn 0000nnnn01101010 FPSCR Rn 1 Yes...

Page 94: ...110nnnn0iii 0 imm of Rn 1 Yes BLD B imm3 disp12 Rn 0011nnnn0iii1001 0011dddddddddddd imm of disp Rn 3 Ope ration result Yes BLD imm3 Rn 10000111nnnn1iii imm of Rn T 1 Ope ration result Yes BLDNOT B imm3 disp12 Rn 0011nnnn0iii1001 1011dddddddddddd imm of disp Rn T 3 Ope ration result Yes BOR B imm3 disp12 Rn 0011nnnn0iii1001 0101dddddddddddd imm of disp Rn T T 3 Ope ration result Yes BORNOT B imm3 ...

Page 95: ...2006 Page 65 of 1588 REJ09B0313 0050 Compatibility Instruction Instruction Code Operation Execu tion Cycles T Bit SH2 SH2E SH4 SH 2A BXOR B imm3 disp12 Rn 0011nnnn0iii1001 0110dddddddddddd imm of disp Rn T T 3 Ope ration result Yes ...

Page 96: ...ion handling source occurs Exception handling ends NMI interrupt or IRQ interrupt occurs Power down state Reset canceled STBY bit cleared for SLEEP instruction Reset state Interrupt source or DMA address error occurs NMI interrupt IRQ interrupt manual reset and power on reset STBY bit set and DEEP bit cleared for SLEEP instruction STBY and DEEP bits set for SLEEP instruction Deep standby mode Note...

Page 97: ...rt address and execution of the program begins For an interrupt the stack pointer SP is accessed and the program counter PC and status register SR are saved to the stack area The exception service routine start address is fetched from the exception handling vector table the CPU then branches to that address and the program starts executing thereby entering the program execution state 3 Program Exe...

Page 98: ...Section 2 CPU Rev 0 50 May 18 2006 Page 68 of 1588 REJ09B0313 0050 ...

Page 99: ...to IEEE754 standard 16 single precision floating point registers can also be referenced as eight double precision registers Two rounding modes Round to nearest and round to zero Denormalization modes Flush to zero Five exception sources Invalid operation divide by zero overflow underflow and inexact Comprehensive instructions Single precision double precision and system control ...

Page 100: ...es 3 1 and 3 2 31 30 23 22 0 s e f Figure 3 1 Format of Single Precision Floating Point Number 63 62 52 51 0 s e f Figure 3 2 Format of Double Precision Floating Point Number The exponent is expressed in biased form as follows e E bias The range of unbiased exponent E is Emin 1 to Emax 1 The two values Emin 1 and Emax 1 are distinguished as follows Emin 1 indicates zero both positive and negative ...

Page 101: ...8 bits 11 bits Fraction field 23 bits 52 bits Precision 24 bits 53 bits Bias 127 1023 Emax 127 1023 Emin 126 1022 Floating point number value v is determined as follows If E Emax 1 and f 0 v is a non number NaN irrespective of sign s If E Emax 1 and f 0 v 1 s infinity positive or negative infinity If Emin E Emax v 1 s 2 E 1 f normalized number If E Emin 1 and f 0 v 1 s 2 Emin 0 f denormalized numb...

Page 102: ...FFF to H 0080 0000 H 7FEF FFFF FFFF FFFF to H 0010 0000 0000 0000 Positive denormalized number H 007F FFFF to H 0000 0001 H 000F FFFF FFFF FFFF to H 0000 0000 0000 0001 Positive zero H 0000 0000 H 0000 0000 0000 0000 Negative zero H 8000 0000 H 8000 0000 0000 0000 Negative denormalized number H 8000 0001 to H 807F FFFF H 8000 0000 0000 0001 to H 800F FFFF FFFF FFFF Negative normalized number H 808...

Page 103: ...at generates a floating point value When the EN V bit in FPSCR is 0 the operation result output is a qNaN When the EN V bit in FPSCR is 1 an invalid operation exception will be generated In this case the contents of the operation destination register are unchanged If a qNaN is input in an operation that generates a floating point value and an sNaN has not been input in that operation the output wi...

Page 104: ...bit in the status register FPSCR is always set to 1 therefore a denormalized number source operand or operation result is always flushed to 0 in a floating point operation that generates a value an operation other than copy FNEG or FABS When the DN bit in FPSCR is 0 a denormalized number source operand or operation result is processed as it is See the individual instruction descriptions for detail...

Page 105: ...le precision floating point registers FRi 16 registers FR0 to FR15 indicate FPR0 to FPR15 3 Double precision floating point registers or single precision floating point vector registers in pairs DRi 8 registers A DR register comprises two FR registers DR0 FR0 FR1 DR2 FR2 FR3 DR4 FR4 FR5 DR6 FR6 FR7 DR8 FR8 FR9 DR10 FR10 FR11 DR12 FR12 FR13 DR14 FR14 FR15 FPR0 FPR1 FPR2 FPR3 FPR4 FPR5 FPR6 FPR7 FPR...

Page 106: ...t Name Initial Value R W Description 31 to 23 All 0 R Reserved These bits are always read as 0 The write value should always be 0 22 QIS 0 R W Nonnunerical Processing Mode 0 Processes qNaN or as such 1 Treats qNaN or as the same as sNaN valid only when FPSCR Enable V 1 21 0 R Reserved This bit is always read as 0 The write value should always be 0 20 SZ 0 R W Transfer Size Mode 0 Data size of FMOV...

Page 107: ...e rounding mode 00 Round to Nearest 01 Round to Zero 10 Reserved 11 Reserved Table 3 3 Bit Allocation for FPU Exception Handling Field Name FPU Error E Invalid Operation V Division by Zero Z Overflow O Underflow U Inexact I Cause FPU exception cause field Bit 17 Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Enable FPU exception enable field None Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Flag FPU exception flag field N...

Page 108: ... by the RM bits in FPSCR FPSCR RM 1 0 00 Round to Nearest FPSCR RM 1 0 01 Round to Zero 1 Round to Nearest The operation result is rounded to the nearest expressible value If there are two nearest expressible values the one with an LSB of 0 is selected If the unrounded value is 2 Emax 2 2 P or more the result will be infinity with the same sign as the unrounded value The values of Emax and P respe...

Page 109: ... E Thus FPU errors cannot be disabled When an FPU exception occurs the corresponding bit in the FPU exception cause field is set to 1 and 1 is added to the corresponding bit in the FPU exception flag field When an FPU exception does not occur the corresponding bit in the FPU exception cause field is cleared to 0 but the corresponding bit in the FPU exception flag field remains unchanged 3 5 2 FPU ...

Page 110: ...e is not generated Also the destination register is not changed by any FPU exception handling operation Except for the above the FPU disables exception handling In every processing the bit corresponding to source V Z O U or I is set to 1 and a default value is generated as the operation result Invalid operation V qNaN is generated as the result Division by zero Z Infinity with the same sign as the...

Page 111: ...clock or the clock for USB Three clocks generated independently An internal clock Iφ for the CPU and cache a peripheral clock Pφ for the on chip peripheral modules a bus clock Bφ CKIO for the external bus interface Frequency change function Internal and peripheral clock frequencies can be changed independently using the PLL phase locked loop circuits and divider circuits within the CPG Frequencies...

Page 112: ...illator Peripheral bus Bus interface FRQCR Legend Frequency control register EXTAL XTAL MD_CLK1 MD_CLK0 FRQCR CPG control unit Clock frequency control circuit Standby control circuit USB_X2 1 1 2 1 3 1 4 1 6 1 8 1 12 MTU clock Iφ Max 200 MHz Bus clock Bφ CKIO Max 66 67 MHz Peripheral clock Pφ Max 33 33 MHz Divider 2 1 1 2 1 4 Divider 1 CKIO Crystal oscillator Figure 4 1 Block Diagram of Clock Puls...

Page 113: ...equency control register When this is done the phase of the rising edge of the internal clock is controlled so that it will agree with the phase of the rising edge of the CKIO pin The input clock to be used depends on the clock operating mode The clock operating mode is specified using the MD_CLK0 and MD_CLK1 pins For details on the clock operating mode see table 4 2 4 Divider 2 Divider 2 generate...

Page 114: ...the standby control register is provided to control the power down mode of other modules For details on the standby control register see section 28 Power Down Modes 7 Frequency Control Register FRQCR The frequency control register FRQCR has control bits assigned for the following functions clock output non output from the CKIO pin during software standby mode the frequency multiplication ratio of ...

Page 115: ...l clock Pull up this pin Pull up this pin Clock input output pin CKIO I O Clock output pin Clock input pin Clock output pin USB_X1 Input Connected to the crystal resonator to input the clock for USB only or used to input external clock When USB is not used this pin should be pulled up Connected to the crystal resonator to input the clock for USB only or used to input external clock When USB is not...

Page 116: ...ock is input from the EXTAL pin or the crystal oscillator The PLL circuit shapes waveforms and the frequency is multiplied according to the frequency control register setting before the clock is supplied to the LSI The oscillating frequency for the crystal resonator and EXTAL pin input clock ranges from 10 to 16 67 MHz The frequency range of CKIO is from 40 to 66 67 MHz To reduce current supply pu...

Page 117: ...AL pin when the LSI is used in mode 2 When USB is not used pull up the USB_X1 pin and open the USB_X2 pin Mode 3 In mode 3 clock is input from the USB_X1 pin or the crystal oscillator The external clock is input through this pin and waveform is shaped in the PLL circuit Then the frequency is multiplied according to the frequency control register setting before the clock is supplied to the LSI The ...

Page 118: ...10 to 12 5 40 to 50 80 to 100 40 to 50 13 33 to 16 67 H x003 ON 8 4 2 1 20 to 33 33 40 to 66 67 80 to 133 36 40 to 66 67 20 to 33 33 H x004 ON 8 4 2 4 3 20 to 33 33 40 to 66 67 80 to 133 36 40 to 66 67 13 33 to 22 22 H x005 ON 8 4 2 1 2 20 to 33 33 40 to 66 67 80 to 133 36 40 to 66 67 10 to 16 67 H x006 ON 8 4 1 1 3 20 to 33 33 40 to 66 67 80 to 133 36 40 to 66 67 6 67 to 11 11 H x104 ON 12 6 2 1 ...

Page 119: ...H x216 ON 16 2 1 1 3 48 48 96 48 16 Notes 1 x in the FRQCR register setting depends on the set value in bits 12 and 13 2 The ratio of clock frequencies where the input clock frequency is assumed to be 1 3 In mode 0 or 1 the frequency of the EXTAL pin input clock or the crystal resonator In mode 2 the frequency of the CKIO pin input clock In mode 3 the frequency of the USB_X1 pin input clock or the...

Page 120: ...divisor of the divider 1 The frequency of the peripheral clock should be set to 33 33 MHz or less and should not be set higher than the frequency on the CKIO pin 3 The frequency multiplier of PLL circuit can be selected as 8 12 or 16 The divisor of the divider can be selected as 1 1 2 1 3 1 4 1 6 1 8 or 1 12 The settings are made in the frequency control register FRQCR 4 The output frequency of th...

Page 121: ...tandby mode cancellation The register also specifies the frequency multiplier of the PLL circuit and the frequency division ratio for the internal clock and peripheral clock Pφ FRQCR is accessed by word FRQCR is initialized to H 0003 only by a power on reset or in deep standby FRQCR retains its previous value in manual reset or software standby mode The previous value is also retained when an inte...

Page 122: ...fore the malfunction of an external circuit caused by an unstable CKIO clock during cancellation of standby mode can be prevented In clock operating mode 2 the CKIO pin functions as an input regardless of the value of these bits In normal operation In release of bus mastership In standby mode 00 Output Output off Hi Z Output off Hi Z 01 Output Output Low level output 10 Output Output Output unstab...

Page 123: ... ratio of the internal clock with respect to the output frequency of PLL circuit 0 1 time 1 1 2 time 3 0 R Reserved This bit is always read as 0 The write value should always be 0 2 to 0 PFC 2 0 011 R W Peripheral Clock Frequency Division Ratio These bits specify the frequency division ratio of the peripheral clock with respect to the output frequency of PLL circuit 000 Reserved setting prohibited...

Page 124: ...pecified oscillation settling time in the WDT and stop the WDT The following must be set WTCSR TME 0 WDT stops WTCSR CKS 2 0 Division ratio of WDT count clock WTCNT counter Initial counter value The WDT count is incremented using the clock after the setting 3 Set the desired value in the STC1 and STC0 bits The division ratio can also be set in the IFC and PFC2 to PFC0 bits 4 This LSI pauses tempor...

Page 125: ...in the IFC and PFC2 to IFC0 bits The values that can be set are limited by the clock operating mode and the multiplication rate of PLL circuit Note that if the wrong value is set this LSI will malfunction 3 After the register bits IFC and PFC2 to PFC0 have been set the clock is supplied of the new division ratio Note When executing the SLEEP instruction after the frequency has been changed be sure...

Page 126: ... state Example of connection with XTAL pin open Figure 4 2 Example of Connecting External Clock 4 6 2 Note on Using an External Crystal Resonator Place the crystal resonator and capacitors CL1 and CL2 as close to the XTAL and EXTAL pins as possible In addition to minimize induction and thus obtain oscillation at the correct frequency the capacitors to be attached to the resonator must be grounded ...

Page 127: ...is not applied to the resonator pin 4 6 4 Note on Using a PLL Oscillation Circuit In the PLLVcc and PLLVss connection pattern for the PLL signal lines from the board power supply pins must be as short as possible and pattern width must be as wide as possible to reduce inductive interference In clock operating mode 2 or 3 the EXTAL pin is pulled up and the XTAL pin is left open Since the analog pow...

Page 128: ...Section 4 Clock Pulse Generator CPG Rev 0 50 May 18 2006 Page 98 of 1588 REJ09B0313 0050 ...

Page 129: ...iority shown Table 5 1 Types of Exception Handling and Priority Order Type Exception Handling Priority Power on reset Reset Manual reset CPU address error Address error DMAC address error Integer division exception division by zero Instruction Integer division exception overflow Bank underflow Register bank error Bank overflow NMI User break H UDI IRQ PINT Direct memory access controller DMAC USB2...

Page 130: ...e High Instruction Slot illegal instructions undefined code placed directly after a delayed branch instruction 1 including FPU instructions and FPU related CPU instructions in FPU module standby state instructions that rewrite the PC 2 32 bit instructions 3 RESBANK instruction DIVS instruction and DIVU instruction Low Notes 1 Delayed branch instructions JMP JSR BRA BSR RTS RTE BF S BT S BSRF BRAF ...

Page 131: ...erformed to register banks Register bank error Bank overflow In the state where saving has been performed to all register bank areas starts when acceptance of register bank overflow exception has been set by the interrupt controller the BOVE bit in IBNR of the INTC is 1 and an interrupt that uses a register bank has occurred and been accepted by the CPU Trap instruction Starts from the execution o...

Page 132: ... the PC address fetched from the exception handling vector table 2 Exception Handling Triggered by Address Errors Register Bank Errors Interrupts and Instructions SR and PC are saved to the stack indicated by R15 In the case of interrupt exception handling other than NMI or user breaks with usage of the register banks enabled general registers R0 to R14 control register GBR system registers MACH M...

Page 133: ...ws the vector numbers and vector table address offsets Table 5 4 shows how vector table addresses are calculated Table 5 3 Exception Handling Vector Table Exception Sources Vector Numbers Vector Table Address Offset PC 0 H 00000000 to H 00000003 Power on reset SP 1 H 00000004 to H 00000007 PC 2 H 00000008 to H 0000000B Manual reset SP 3 H 0000000C to H 0000000F General illegal instruction 4 H 0000...

Page 134: ...hip peripheral module interrupts 64 511 H 00000100 to H 00000103 H 000007FC to H 000007FF Note The vector numbers and vector table address offsets for each external interrupt and on chip peripheral module interrupt are given in table 6 4 in section 6 Interrupt Controller INTC Table 5 4 Calculating Exception Handling Vector Table Addresses Exception Source Vector Table Address Calculation Resets Ve...

Page 135: ...nitialized in both a power on reset and a manual reset The FPU state is initialized by a power on reset but not by a manual reset On chip peripheral module registers except a few registers are also initialized by a power on reset but not by a manual reset Table 5 6 Reset States Conditions for Transition to Reset State Internal States Type RES H UDI Command MRES WDT Overflow CPU Other Modules Low I...

Page 136: ...eption handling vector table 3 The vector base register VBR is cleared to H 00000000 the interrupt mask level bits I3 to I0 of the status register SR are initialized to H F B 1111 and the BO and CS bits are initialized The BN bit in IBNR of the INTC is also initialized to 0 FPSCR is initialized to H 00040001 4 The values fetched from the exception handling vector table are set in the PC and SP and...

Page 137: ...se WRCSR of the WDT and FRQCR of the CPG are not initialized by the reset signal generated by the WDT If a reset caused by the RES pin or the H UDI reset assert command occurs simultaneously with a reset caused by WDT overflow the reset caused by the RES pin or the H UDI reset assert command has priority and the WOVF bit in WRCSR is cleared to 0 When power on reset exception processing is started ...

Page 138: ...and the BO and CS bits are initialized The BN bit in IBNR of the INTC is also initialized to 0 4 The values fetched from the exception handling vector table are set in the PC and SP and the program begins executing 2 Manual Reset Initiated by WDT When a setting is made for a manual reset to be generated in the WDT s watchdog timer mode and WTCNT of the WDT overflows this LSI enters the manual rese...

Page 139: ... Instruction fetch CPU Instruction fetched from on chip peripheral module space or H F0000000 to H F5FFFFFF in on chip RAM space Address error occurs Word data accessed from even address None normal Word data accessed from odd address Address error occurs Longword data accessed from a longword boundary None normal Longword data accessed from other than a long word boundary Address error occurs Byt...

Page 140: ...ception service routine start address which corresponds to the address error that occurred is fetched from the exception handling vector table 2 The status register SR is saved to the stack 3 The program counter PC is saved to the stack The PC value saved is the start address of the instruction to be executed after the last executed instruction 4 After jumping to the exception service routine star...

Page 141: ...ister bank error exception handling starts The CPU operates as follows 1 The exception service routine start address which corresponds to the register bank error that occurred is fetched from the exception handling vector table 2 The status register SR is saved to the stack 3 The program counter PC is saved to the stack The PC value saved is the start address of the instruction to be executed afte...

Page 142: ...put 8 Direct memory access controller DMAC 16 USB2 0 host function module USB 1 LCD controller LCDC 1 Compare match timer CMT 2 Bus state controller BSC 1 Watchdog timer WDT 1 Multi function timer pulse unit 2 MTU2 25 A D converter ADC 1 I 2 C bus interface 3 IIC3 20 Serial communications interface with FIFO SCIF 16 Synchronous serial communications unit SSU 6 Serial sound interface SSI 4 AND NAND...

Page 143: ...interrupt priority level is 15 Priority levels of IRQ interrupts PINT interrupts and on chip peripheral module interrupts can be set freely using the interrupt priority registers 01 02 and 05 to 17 IPR01 IPR02 and IPR05 to IPR17 of the INTC as shown in table 5 9 The priority levels that can be set are 0 to 15 Level 16 cannot be set See section 6 3 1 Interrupt Priority Registers 01 02 05 to 17 IPR0...

Page 144: ...ddress offset of the interrupt exception handling to be executed are saved in the register banks In the case of exception handling due to an address error NMI interrupt user break interrupt or instruction saving is not performed to the register banks If saving has been performed to all register banks 0 to 14 automatic saving to the stack is performed instead of register bank saving In this case an...

Page 145: ...instructions RESBANK instruction DIVS instruction and DIVU instruction Delayed branch instructions JMP JSR BRA BSR RTS RTE BF S BT S BSRF BRAF Instructions that rewrite the PC JMP JSR BRA BSR RTS RTE BT BF TRAPA BF S BT S BSRF BRAF JSR N RTV N 32 bit instructions BAND B BANDNOT B BCLR B BLD B BLDNOT B BOR B BORNOT B BSET B BST B BXOR B MOV B disp12 MOV W disp12 MOV L disp12 MOVI20 MOVI20S MOVU B M...

Page 146: ...tructions and FPU related CPU instructions in FPU module standby state an instruction that rewrites the PC a 32 bit instruction an RESBANK instruction a DIVS instruction or a DIVU instruction slot illegal exception handling starts when such kind of instruction is decoded When the FPU has entered a module standby state the floating point operation instruction and FPU related CPU instructions are ha...

Page 147: ...ons however the program counter value stored is the start address of the undefined code 5 6 5 Integer Division Instructions When an integer division instruction performs division by zero or the result of integer division overflows integer division instruction exception handling starts The instructions that may become the source of division by zero exception are DIVU and DIVS The only source instru...

Page 148: ...ion is reported to the CPU When exception handling is started the CPU operations are as follows 1 The start address of the exception service routine which corresponds to the FPU exception that occurred is fetched from the exception handling vector table 2 The status register SR is saved to the stack 3 The program counter PC is saved to the stack The PC value saved is the start address of the instr...

Page 149: ...y but stored instead as shown in table 5 11 When this happens it will be accepted when an instruction that can accept the exception is decoded Table 5 11 Exception Source Generation Immediately after Delayed Branch Instruction Exception Source Point of Occurrence Address Error FPU Exception Register Bank Error Overflow Interrupt Immediately after a delayed branch instruction Not accepted Not accep...

Page 150: ...SR Address of instruction after executed instruction SP Interrupt 32 bits 32 bits SR Address of instruction after executed instruction SP Register bank error overflow 32 bits 32 bits SR Address of instruction after executed instruction SP Register bank error underflow 32 bits 32 bits SR Start address of relevant RESBANK instruction SP Trap instruction 32 bits 32 bits SR Address of instruction afte...

Page 151: ...Stack Status General illegal instruction 32 bits 32 bits SR Start address of general illegal instruction SP Integer division instruction 32 bits 32 bits SR Start address of relevant integer division instruction SP FPU exception 32 bits 32 bits SR Address of instruction after executed instruction SP ...

Page 152: ...rrupts etc and address error exception handling will start up as soon as the first exception handling is ended Address errors will then also occur in the stacking for this address error exception handling To ensure that address error exception handling does not go into an endless loop no address errors are accepted at that point This allows program control to be shifted to the address error except...

Page 153: ... interrupts and on chip peripheral module interrupts can be selected from 16 levels for request sources NMI noise canceler function An NMI input level bit indicates the NMI pin state By reading this bit in the interrupt exception service routine the pin state can be checked enabling it to be used as the noise canceler function Occurrence of interrupt can be reported externally IRQOUT pin For examp...

Page 154: ...request Interrupt request Interrupt request Interrupt request Interrupt request Interrupt request Interrupt request Priority identifier Com parator Interrupt request Bus interface Peripheral bus User break controller User debugging interface Direct memory access controller USB2 0 host function module LCDC controller Compare match timer Bus state controller Watchdog timer Multi function timer pulse...

Page 155: ...TC Table 6 1 Pin Configuration Pin Name Symbol I O Function Nonmaskable interrupt input pin NMI Input Input of nonmaskable interrupt request signal IRQ7 to IRQ0 Input Interrupt request input pins PINT7 to PINT0 Input Input of maskable interrupt request signals Interrupt request output pin IRQOUT Output Output of signal to report occurrence of interrupt source ...

Page 156: ...ter 01 IPR01 R W H 0000 H FFFE0818 16 32 Interrupt priority register 02 IPR02 R W H 0000 H FFFE081A 16 32 Interrupt priority register 05 IPR05 R W H 0000 H FFFE0820 16 32 Interrupt priority register 06 IPR06 R W H 0000 H FFFE0C00 16 32 Interrupt priority register 07 IPR07 R W H 0000 H FFFE0C02 16 32 Interrupt priority register 08 IPR08 R W H 0000 H FFFE0C04 16 32 Interrupt priority register 09 IPR...

Page 157: ...Initial value R W Table 6 3 Interrupt Request Sources and IPR01 IPR02 and IPR05 to IPR17 Register Name Bits 15 to 12 Bits 11 to 8 Bits 7 to 4 Bits 3 to 0 Interrupt priority register 01 IRQ0 IRQ1 IRQ2 IRQ3 Interrupt priority register 02 IRQ4 IRQ5 IRQ6 IRQ7 Interrupt priority register 05 PINT7 to PINT0 Reserved Reserved Reserved Interrupt priority register 06 DMAC0 DMAC1 DMAC2 DMAC3 Interrupt priori...

Page 158: ...I3 Reserved Interrupt priority register 16 FLCTL Reserved RTC RCAN0 Interrupt priority register 17 RCAN1 Reserved Reserved Reserved As shown in table 6 3 by setting the 4 bit groups bits 15 to 12 bits 11 to 8 bits 7 to 4 and bits 3 to 0 with values from H 0 0000 to H F 1111 the priority of each corresponding interrupt is set Setting of H 0 means priority level 0 the lowest level and H F means prio...

Page 159: ...ame Initial Value R W Description 15 NMIL R NMI Input Level Sets the level of the signal input at the NMI pin The NMI pin level can be obtained by reading this bit This bit cannot be modified 0 Low level is input to NMI pin 1 High level is input to NMI pin 14 to 9 All 0 R Reserved These bits are always read as 0 The write value should always be 0 8 NMIE 0 R W NMI Edge Select Selects whether the fa...

Page 160: ...IRQ11S IRQ10S IRQ01S IRQ00S Bit Bit Name Initial Value R W Description 15 IRQ71S 0 R W 14 IRQ70S 0 R W 13 IRQ61S 0 R W 12 IRQ60S 0 R W 11 IRQ51S 0 R W 10 IRQ50S 0 R W 9 IRQ41S 0 R W 8 IRQ40S 0 R W 7 IRQ31S 0 R W 6 IRQ30S 0 R W 5 IRQ21S 0 R W 4 IRQ20S 0 R W 3 IRQ11S 0 R W 2 IRQ10S 0 R W 1 IRQ01S 0 R W 0 IRQ00S 0 R W IRQ Sense Select These bits select whether interrupt signals corresponding to pins ...

Page 161: ...tial value R W PINT7S PINT6S PINT5S PINT4S PINT3S PINT2S PINT1S PINT0S Bit Bit Name Initial Value R W Description 15 to 8 All 0 R Reserved These bits are always read as 0 The write value should always be 0 7 PINT7S 0 R W 6 PINT6S 0 R W 5 PINT5S 0 R W 4 PINT4S 0 R W 3 PINT3S 0 R W 2 PINT2S 0 R W 1 PINT1S 0 R W 0 PINT0S 0 R W PINT Sense Select These bits select whether interrupt signals correspondin...

Page 162: ...pts writing 0 to the IRQ7F to IRQ0F bits after reading IRQ7F to IRQ0F 1 cancels the retained interrupts 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Note Only 0 can be written to clear the flag after 1 is read Bit Initial value R W 0 0 0 0 0 0 0 0 R R R R R R R R IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Bit Bit Name Initial Value R W Description 15 t...

Page 163: ... interrupt requests Level detection 0 IRQn interrupt request has not occurred Clearing condition IRQn input is high 1 IRQn interrupt has occurred Setting condition IRQn input is low Edge detection 0 IRQn interrupt request is not detected Clearing conditions Cleared by reading IRQnF while IRQnF 1 then writing 0 to IRQnF Cleared by executing IRQn interrupt exception handling 1 IRQn interrupt request...

Page 164: ...W R W Bit Initial value R W PINT7E PINT6E PINT5E PINT4E PINT3E PINT2E PINT1E PINT0E Bit Bit Name Initial Value R W Description 15 to 8 All 0 R Reserved These bits are always read as 0 The write value should always be 0 7 PINT7E 0 R W 6 PINT6E 0 R W 5 PINT5E 0 R W 4 PINT4E 0 R W 3 PINT3E 0 R W 2 PINT2E 0 R W 1 PINT1E 0 R W 0 PINT0E 0 R W PINT Enable These bits select whether to enable interrupt req...

Page 165: ...R R R R R R R R R R Bit Initial value R W PINT7R PINT6R PINT5R PINT4R PINT3R PINT2R PINT1R PINT0R Bit Bit Name Initial Value R W Description 15 to 8 All 0 R Reserved These bits are always read as 0 The write value should always be 0 7 PINT7R 0 R 6 PINT6R 0 R 5 PINT5R 0 R 4 PINT4R 0 R 3 PINT3R 0 R 2 PINT2R 0 R 1 PINT1R 0 R 0 PINT0R 0 R PINT Interrupt Request These bits indicate the status of the PI...

Page 166: ...14 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 Bit Bit Name Initial Value R W Description 15 E15 0 R W 14 E14 0 R W 13 E13 0 R W 12 E12 0 R W 11 E11 0 R W 10 E10 0 R W 9 E9 0 R W 8 E8 0 R W 7 E7 0 R W 6 E6 0 R W 5 E5 0 R W 4 E4 0 R W 3 E3 0 R W 2 E2 0 R W 1 E1 0 R W Enable These bits enable or disable use of register banks for interrupt priority levels 15 to 1 However use of register banks is alway...

Page 167: ... W Description 15 14 BE 1 0 00 R W Register Bank Enable These bits enable or disable use of register banks 00 Use of register banks is disabled for all interrupts The setting of IBCR is ignored 01 Use of register banks is enabled for all interrupts except NMI and user break The setting of IBCR is ignored 10 Reserved setting prohibited 11 Use of register banks is controlled by the setting of IBCR 1...

Page 168: ...mber These bits indicate the bank number to which saving is performed next When an interrupt using register banks is accepted saving is performed to the register bank indicated by these bits and BN is incremented by 1 After BN is decremented by 1 due to execution of a RESBANK restore from register bank instruction restoration from the register bank is performed ...

Page 169: ...the I3 to I0 bits in SR to level 15 For user break interrupts see section 7 User Break Controller UBC 6 4 3 H UDI Interrupt The user debugging interface H UDI interrupt has a priority level of 15 and occurs at serial input of an H UDI interrupt instruction H UDI interrupt requests are edge detected and retained until they are accepted The H UDI interrupt exception handling sets the I3 to I0 bits i...

Page 170: ...e interrupt requests is enabled by the PINT enable bits PINT7E to PINT0E in the PINT interrupt enable register PINTER For the PINT7 to PINT0 interrupts low level or high level detection can be selected individually for each pin by the PINT sense select bits PINT7S to PINT0S in interrupt control register 2 ICR2 A single priority level in a range from 0 to 15 can be set for all PINT7 to PINT0 interr...

Page 171: ...C bus interface 3 IIC3 Serial communications interface with FIFO SCIF Synchronous serial communications unit SSU Serial sound interface SSI AND NAND flash memory controller FLCTL Realtime clock RTC Controller area network RCAN TL1 As every source is assigned a different interrupt vector the source does not need to be identified in the exception service routine A priority level in a range from 0 to...

Page 172: ...f the vector table address see table 5 4 in section 5 Exception Handling The priorities of IRQ interrupts PINT interrupts and on chip peripheral module interrupts can be set freely between 0 and 15 for each pin or module by setting interrupt priority registers 01 02 and 05 to 17 IPR01 IPR02 and IPR05 to IPR17 However if two or more interrupts specified by the same IPR among IPR05 to IPR17 occur th...

Page 173: ...00 to H 00000103 0 to 15 0 IPR01 15 to 12 IRQ1 65 H 00000104 to H 00000107 0 to 15 0 IPR01 11 to 8 IRQ2 66 H 00000108 to H 0000010B 0 to 15 0 IPR01 7 to 4 IRQ3 67 H 0000010C to H 0000010F 0 to 15 0 IPR01 3 to 0 IRQ4 68 H 00000110 to H 00000113 0 to 15 0 IPR02 15 to 12 IRQ5 69 H 00000114 to H 00000117 0 to 15 0 IPR02 11 to 8 IRQ6 70 H 00000118 to H 0000011B 0 to 15 0 IPR02 7 to 4 IRQ IRQ7 71 H 0000...

Page 174: ... DMAC0 HEI0 109 H 000001B4 to H 000001B7 2 DEI1 112 H 000001C0 to H 000001C3 1 DMAC1 HEI1 113 H 000001C4 to H 000001C7 0 to 15 0 IPR06 11 to 8 2 DEI2 116 H 000001D0 to H 000001D3 1 DMAC2 HEI2 117 H 000001D4 to H 000001D7 0 to 15 0 IPR06 7 to 4 2 DEI3 120 H 000001E0 to H 000001E3 1 DMAC3 HEI3 121 H 000001E4 to H 000001E7 0 to 15 0 IPR06 3 to 0 2 DEI4 124 H 000001F0 to H 000001F3 1 DMAC4 HEI4 125 H ...

Page 175: ... 12 LCDC LCDCI 141 H 00000234 to H 00000237 0 to 15 0 IPR08 11 to 8 CMI0 142 H 00000238 to H 0000023B 0 to 15 0 IPR08 7 to 4 CMT CMI1 143 H 0000023C to H 0000023F 0 to 15 0 IPR08 3 to 0 BSC CMI 144 H 00000240 to H 00000243 0 to 15 0 IPR09 15 to 12 WDT ITI 145 H 00000244 to H 00000247 0 to 15 0 IPR09 11 to 8 TGI0A 146 H 00000248 to H 0000024B 1 TGI0B 147 H 0000024C to H 0000024F 2 TGI0C 148 H 00000...

Page 176: ...o 12 2 TCI1V 155 H 0000026C to H 0000026F 1 MTU1 TCI1U 156 H 00000270 to H 00000273 0 to 15 0 IPR10 11 to 8 2 TGI2A 157 H 00000274 to H 00000277 1 TGI2B 158 H 00000278 to H 0000027B 0 to 15 0 IPR10 7 to 4 2 TCI2V 159 H 0000027C to H 0000027F 1 MTU2 TCI2U 160 H 00000280 to H 00000283 0 to 15 0 IPR10 3 to 0 2 TGI3A 161 H 00000284 to H 00000287 1 TGI3B 162 H 00000288 to H 0000028B 2 TGI3C 163 H 00000...

Page 177: ...000002A7 0 to 15 0 IPR11 7 to 4 4 MTU2 MTU4 TCI4V 170 H 000002A8 to H 000002AB 0 to 15 0 IPR11 15 to 12 ADC ADI 171 H 000002AC to H 000002AF 0 to 15 0 IPR12 15 to 12 STPI0 172 H 000002B0 to H 000002B3 1 NAKI0 173 H 000002B4 to H 000002B7 2 RXI0 174 H 000002B8 to H 000002BB 3 TXI0 175 H 000002BC to H 000002BF 4 IIC3 0 TEI0 176 H 000002C0 to H 000002C3 0 to 15 0 IPR12 11 to 8 5 STPI1 177 H 000002C4 ...

Page 178: ...XI2 184 H 000002E0 to H 000002E3 3 TXI2 185 H 000002E4 to H 000002E7 4 IIC3 2 TEI2 186 H 000002E8 to H 000002EB 0 to 15 0 IPR12 3 to 0 5 STPI3 187 H 000002EC to H 000002EF 1 NAKI3 188 H 000002F0 to H 000002F3 2 RXI3 189 H 000002F4 to H 000002F7 3 TXI3 190 H 000002F8 to H 000002FB 4 IIC3 IIC3 3 TEI3 191 H 000002FC to H 000002FF 0 to 15 0 IPR13 15 to 12 5 BRI0 192 H 00000300 to H 00000303 1 ERI0 193...

Page 179: ... SCIF1 TXI1 199 H 0000031C to H 0000031F 0 to 15 0 IPR13 7 to 4 4 BRI2 200 H 00000320 to H 00000323 1 ERI2 201 H 00000324 to H 00000327 2 RXI2 202 H 00000328 to H 0000032B 3 SCIF2 TXI2 203 H 0000032C to H 0000032F 0 to 15 0 IPR13 3 to 0 4 BRI3 204 H 00000330 to H 00000333 1 ERI3 205 H 00000334 to H 00000337 2 RXI3 206 H 00000338 to H 0000033B 3 SCIF SCIF3 TXI3 207 H 0000033C to H 0000033F 0 to 15 ...

Page 180: ...R14 7 to 4 3 SSI0 SSII0 214 H 00000358 to H 0000035B 0 to 15 0 IPR14 3 to 0 SSI1 SSII1 215 H 0000035C to H 0000035F 0 to 15 0 IPR15 15 to 12 SSI2 SSII2 216 H 00000360 to H 00000363 0 to 15 0 IPR15 11 to 8 SSI SSI3 SSII3 217 H 00000364 to H 00000367 0 to 15 0 IPR15 7 to 4 FLSTEI 224 H 00000380 to H 00000383 1 FLTENDI 225 H 00000384 to H 00000387 2 FLTREQ0I 226 H 00000388 to H 0000038B 3 FLCTL FLTRE...

Page 181: ...fault Priority ERS0 234 H 000003A8 to H 000003AB 1 OVR0 235 H 000003AC to H 000003AF 2 RM00 236 H 000003B0 to H 000003B3 3 RM10 237 H 000003B4 to H 000003B7 4 RCAN0 SLE0 238 H 000003B8 to H 000003BB 0 to 15 0 IPR16 3 to 0 5 ERS1 239 H 000003BC to H 000003BF 1 OVR1 240 H 000003C0 to H 000003C3 2 RM01 241 H 000003C4 to H 000003C7 3 RM11 242 H 000003C8 to H 000003CB 4 High RCAN TL1 RCAN1 SLE1 243 H 0...

Page 182: ...ss than the level set in bits I3 to I0 the interrupt request is ignored If the interrupt request priority level is higher than the level in bits I3 to I0 the interrupt controller accepts the interrupt and sends an interrupt request signal to the CPU 4 When the interrupt controller accepts an interrupt a low level is output from the IRQOUT pin 5 The CPU detects the interrupt request sent from the i...

Page 183: ...quired before the interrupt source sent to the CPU is actually cancelled To ensure that an interrupt request that should have been cleared is not inadvertently accepted again read the interrupt source flag after it has been cleared and then execute an RTE instruction Interrupt requests that are designated as edge sensing are held pending until the interrupt requests are accepted IRQ interrupts how...

Page 184: ...n state Interrupt NMI User break I3 to I0 level 14 Level 14 interrupt Level 1 interrupt I3 to I0 level 13 I3 to I0 level 0 H UDI interrupt Level 15 interrupt IRQOUT low Save SR to stack Save PC to stack Copy accept interrupt level to I3 to I0 IRQOUT high Read exception handling vector table Branch to interrupt exception service routine Figure 6 2 Interrupt Operation Flow ...

Page 185: ...Handling Figure 6 3 shows the stack after interrupt exception handling Address SP 2 4n 8 PC 1 SR 4n 4 4n 32 bits 32 bits Notes 1 PC Start address of the next instruction return destination instruction after the executed instruction 2 Always make sure that SP is a multiple of 4 Figure 6 3 Stack after Interrupt Exception Handling ...

Page 186: ...Q PINT Peripheral Module Remarks Time from occurrence of interrupt request until interrupt controller identifies priority compares it with mask bits in SR and sends interrupt request signal to CPU 2 Icyc 2 Bcyc 1 Pcyc 3 Icyc 2 Icyc 1 Pcyc 2 Icyc 3 Bcyc 1 Pcyc 2 Icyc 2 Bcyc Min 3 Icyc m1 m2 No register banking Max 4 Icyc 2 m1 m2 m3 Min is when the interrupt wait time is zero Max is when a higher pr...

Page 187: ... 0 110 µs Register banking without register bank overflow Max 14 Icyc 1 Pcyc m1 m2 14 Icyc 3 Bcyc 1 Pcyc m1 m2 14 Icyc 2 Bcyc m1 m2 200 MHz operation 1 2 0 120 to 0 155 µs Min 5 Icyc 1 Pcyc m1 m2 5 Icyc 3 Bcyc 1 Pcyc m1 m2 5 Icyc 2 Bcyc m1 m2 200 MHz operation 1 2 0 065 to 0 110 µs Interrupt response time Register banking with register bank overflow Max 5 Icyc 1 Pcyc m1 m2 19 m4 5 Icyc 3 Bcyc 1 Pc...

Page 188: ...terrupt acceptance D E E M M M F D E Legend Vector address read Saving of SR stack Saving of PC stack Instruction fetch Instruction is fetched from memory in which program is stored Instruction decoding Fetched instruction is decoded Instruction execution Data operation or address calculation is performed in accordance with the result of decoding Memory access Memory data access is performed Figur...

Page 189: ...outine First instruction in multiple interrupt exception service routine Figure 6 5 Example of Pipeline Operation for Multiple Interrupts No Register Banking F 2 Icyc 3 Bcyc 1 Pcyc 3 Icyc m1 m2 m3 3 Icyc m1 m2 IRQ D E E M M M E F D E Legend m1 m2 m3 Vector address read Saving of SR stack Saving of PC stack Interrupt acceptance First instruction in interrupt exception service routine Instruction in...

Page 190: ...g interrupt exception handling Figure 6 7 Example of Pipeline Operation when Interrupt is Accepted during RESBANK Instruction Execution Register Banking without Register Bank Overflow F 2 Icyc 3 Bcyc 1 Pcyc 3 Icyc m1 m2 m3 3 Icyc m1 m2 IRQ D E E M M M M F D Legend m1 m2 m3 Vector address read Saving of SR stack Saving of PC stack Interrupt acceptance First instruction in interrupt exception servic...

Page 191: ...F D m4 m4 Legend m1 m2 m3 m4 Vector address read Saving of SR stack Saving of PC stack Restoration of banked registers Interrupt acceptance First instruction in interrupt exception service routine Instruction instruction replacing interrupt exception handling Figure 6 9 Example of Pipeline Operation when Interrupt is Accepted during RESBANK Instruction Execution Register Banking with Register Bank...

Page 192: ... the register bank configuration General registers Bank control register Bank number register Bank control registers interrupt controller Banked register Vector table address offset Note Interrupt generated save RESBANK instruction restore Registers Register banks Bank 0 Bank 1 Bank 14 R0 R1 R14 R15 SR GBR VBR TBR MACH MACL PR PC Control registers System registers R0 R1 R14 GBR VTO VTO IBCR IBNR M...

Page 193: ... place in the reverse order beginning from the last bank saved to 6 8 2 Bank Save and Restore Operations 1 Saving to Bank Figure 6 11 shows register bank save operations The following operations are performed when an interrupt for which usage of register banks is allowed is accepted by the CPU a Assume that the bank number bit value in the bank number register IBNR BN is i before the interrupt is ...

Page 194: ...R11 4 R4 R5 R6 R7 5 R0 R1 R2 R3 Overrun fetch Saved to bank D E E M M M E F F D E Legend m1 m2 m3 Vector address read Saving of SR stack Saving of PC stack First instruction in interrupt exception service routine Instruction instruction replacing interrupt exception handling Figure 6 12 Bank Save Timing 2 Restoration from Bank The RESBANK restore from register bank instruction is used to restore d...

Page 195: ...rogram counter PC are saved to the stack during interrupt exception handling 2 The contents of the banked registers R0 to R14 GBR MACH MACL and PR are saved to the stack The registers are saved to the stack in the order of MACL MACH GBR PR R14 R13 R1 and R0 3 The register bank overflow bit BO in SR is set to 1 4 The bank number bit BN value in the bank number register IBNR remains set to the maxim...

Page 196: ...PR do not change In addition the bank number bit BN value in the bank number register IBNR remains set to 0 6 8 5 Register Bank Error Exception Handling When a register bank error occurs register bank error exception handling starts When this happens the CPU operates as follows 1 The exception service routine start address which corresponds to the register bank error that occurred is fetched from ...

Page 197: ...errupt source select 1 DE2 interrupt source select 2 DE3 interrupt source select 3 DE4 interrupt source select 4 DE5 interrupt source select 5 DE6 interrupt source select 6 DE7 interrupt source select 7 Figure 6 13 shows a block diagram of interrupt control Here DME is bit 0 in DMAOR of the DMAC and DEn n 0 to 7 is bit 0 in CHCR0 to CHCR7 of the DMAC For details see section 10 Direct Memory Access...

Page 198: ...interrupts occur interrupt requests are sent to the CPU 3 The CPU clears the interrupt source and performs the necessary processing in the interrupt exception service routine 6 9 2 Handling Interrupt Request Signals as Sources for Activating DMAC but Not CPU Interrupt 1 Select DMAC activating sources and set both the DE and DME bits to 1 This masks CPU interrupt sources regardless of the interrupt...

Page 199: ...source flag time from occurrence of interrupt request until interrupt controller identifies priority compares it with mask bits in SR and sends interrupt request signal to CPU shown in table 6 5 is required before the interrupt source sent to the CPU is actually cancelled To ensure that an interrupt request that should have been cleared is not inadvertently accepted again read the interrupt source...

Page 200: ...Section 6 Interrupt Controller INTC Rev 0 50 May 18 2006 Page 170 of 1588 REJ09B0313 0050 ...

Page 201: ... and the internal DMA bus on which the DMA issues bus cycles The UBC monitors the C bus and I bus 7 1 Features 1 The following break comparison conditions can be set Number of break channels two channels channels 0 and 1 User break can be requested as the independent condition on channels 0 and 1 Address Comparison of the 32 bit address is maskable in 1 bit units One of the four address buses F ad...

Page 202: ...l 0 Access comparator Address comparator Data comparator Control Channel 1 User break interrupt request Legend BBR BAR BAMR BDR BDMR BRCR Break bus cycle register Break address register Break address mask register Access control Data comparator UBCTRG pin output Internal bus I bus CPU bus C bus Break data register Break data mask register Break control register IDDB IDAB Internal DMA bus Internal ...

Page 203: ...173 of 1588 REJ09B0313 0050 7 2 Input Output Pin Table 7 1 shows the pin configuration of the UBC Table 7 1 Pin Configuration Pin Name Symbol I O Function UBC trigger UBCTRG Output Indicates that a setting condition is satisfied on either channel 0 or 1 of the UBC ...

Page 204: ...dress register_0 BAR_0 R W H 00000000 H FFFC0400 32 Break address mask register_0 BAMR_0 R W H 00000000 H FFFC0404 32 Break bus cycle register_0 BBR_0 R W H 0000 H FFFC04A0 16 Break data register_0 BDR_0 R W H 00000000 H FFFC0408 32 0 Break data mask register_0 BDMR_0 R W H 00000000 H FFFC040C 32 Break address register_1 BAR_1 R W H 00000000 H FFFC0410 32 Break address mask register_1 BAMR_1 R W H...

Page 205: ... W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W Bit Initial value R W BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16 BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8 BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0 Bit Bit Name Initial Value R W Description 31 to 0 BA31 to BA0 All 0 R W Break Address Store an address on the CPU address bus FAB or MAB or internal addre...

Page 206: ... 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W Bit Initial value R W BAM31 BAM30 BAM29 BAM28 BAM27 BAM26 BAM25 BAM24 BAM23 BAM22 BAM21 BAM20 BAM19 BAM18 BAM17 BAM16 BAM15 BAM14 BAM13 BAM12 BAM11 BAM10 BAM9 BAM8 BAM7 BAM6 BAM5 BAM4 BAM3 BAM2 BAM1 BAM0 Bit Bit Nam...

Page 207: ...e R W Bit Initial value R W BD31 BD30 BD29 BD28 BD27 BD26 BD25 BD24 BD23 BD22 BD21 BD20 BD19 BD18 BD17 BD16 BD15 BD14 BD13 BD12 BD11 BD10 BD9 BD8 BD7 BD6 BD5 BD4 BD3 BD2 BD1 BD0 Bit Bit Name Initial Value R W Description 31 to 0 BD31 to BD0 All 0 R W Break Data Bits Store data which specifies a break condition When the C bus is selected by BBR specify the break data on MDB in bits BD31 to BD0 When...

Page 208: ...l value R W Bit Initial value R W BDM31 BDM30 BDM29 BDM28 BDM27 BDM26 BDM25 BDM24 BDM23 BDM22 BDM21 BDM20 BDM19 BDM18 BDM17 BDM16 BDM15 BDM14 BDM13 BDM12 BDM11 BDM10 BDM9 BDM8 BDM7 BDM6 BDM5 BDM4 BDM3 BDM2 BDM1 BDM0 Bit Bit Name Initial Value R W Description 31 to 0 BDM31 to BDM0 All 0 R W Break Data Mask Specify bits masked in the break data bits specified by BDR BD31 to BD0 0 Break data bit BDn ...

Page 209: ...6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R W R W R R R W R W R W R W R W R W R W R W R W R W Bit Initial value R W UBID DBE CP 1 0 CD 1 0 ID 1 0 RW 1 0 SZ 1 0 Bit Bit Name Initial Value R W Description 15 14 All 0 R Reserved These bits are always read as 0 The write value should always be 0 13 UBID 0 R W User Break Interrupt Disable Disables or enables user break interrupt requests when a...

Page 210: ...performed 01 Break condition is the C bus F bus or M bus cycle 10 Break condition is the I bus cycle 11 Break condition is the C bus F bus or M bus cycle 5 4 ID 1 0 00 R W Instruction Fetch Data Access Select Select the instruction fetch cycle or data access cycle as the bus cycle of the break condition If the instruction fetch cycle is selected select the C bus cycle 00 Condition comparison is no...

Page 211: ...her a trigger signal is output to the UBCTRG pin when a break condition is satisfied BRCR is a 32 bit readable writable register that has break condition match flags and bits for setting other break conditions For the condition match flags of bits 15 to 12 writing 1 is invalid previous values are retained and writing 0 is only possible To clear the flag write 0 to the flag bit to be cleared and 1 ...

Page 212: ...when a break condition for channel 0 is satisfied 0 Outputs a trigger signal to the UBCTRG pin when a break condition for channel 0 is satisfied 1 Does not output a trigger signal to the UBCTRG pin when a break condition for channel 0 is satisfied 17 16 CKS 1 0 00 R W Clock Select Specifies the pulse width output to the UBCTRG pin when a break condition is satisfied 00 Pulse width of UBCTRG is one...

Page 213: ...tches 12 SCMFD1 0 R W I Bus Cycle Condition Match Flag 1 When the I bus cycle condition in the break conditions set for channel 1 is satisfied this flag is set to 1 In order to clear this flag write 0 to this bit 0 The I bus cycle condition for channel 1 does not match 1 The I bus cycle condition for channel 1 matches 11 to 7 All 0 R Reserved These bits are always read as 0 The write value should ...

Page 214: ...ser Break Controller UBC Rev 0 50 May 18 2006 Page 184 of 1588 REJ09B0313 0050 Bit Bit Name Initial Value R W Description 4 to 0 All 0 R Reserved These bits are always read as 0 The write value should always be 0 ...

Page 215: ... for the appropriate channel and outputs a pulse to the UBCTRG pin with the width set by the CKS 1 0 bits Setting the UBID bit in BBR to 1 enables external monitoring of the trigger output without requesting user break interrupts 3 On receiving a user break interrupt request signal the INTC determines its priority Since the user break interrupt has a priority level of 15 it is accepted when the pr...

Page 216: ... break for instruction fetch which is set as a break before instruction execution occurs when it is confirmed that the instruction has been fetched and will be executed This means a break does not occur for instructions fetched by overrun instructions fetched at a branch or during an interrupt transition but not to be executed When this kind of break is set for the delay slot of a delayed branch i...

Page 217: ...pares break address register bits 31 to 0 to address bus bits 31 to 0 This means that when address H 00001003 is set in the break address register BAR for example the bus cycle in which the break condition is satisfied is as follows where other conditions are met Longword access at H 00001000 Word access at H 00001002 Byte access at H 00001003 3 When the data value is included in the break conditi...

Page 218: ... break condition is saved to the stack The instruction that matched the condition is not executed and the break occurs before it However when a delay slot instruction matches the condition the instruction is executed and the branch destination address is saved to the stack 2 When C bus FAB instruction fetch after instruction execution is specified as a break condition The address of the instructio...

Page 219: ...nd size is not included in the condition A user break occurs after an instruction of address H 00000404 is executed or before instructions of addresses H 00008010 to H 00008016 are executed Example 1 2 Register specifications BAR_0 H 00027128 BAMR_0 H 00000000 BBR_0 H 005A BAR_1 H 00031415 BAMR_1 H 00000000 BBR_1 H 0054 BDR_1 H 00000000 BDMR_1 H 00000000 BRCR H 00000000 Channel 0 Address H 0002712...

Page 220: ...tion with addresses H 00008000 to H 00008FFE is executed or before an instruction with addresses H 00008010 to H 00008016 are executed 2 Break Condition Specified for C Bus Data Access Cycle Example 2 1 Register specifications BAR_0 H 00123456 BAMR_0 H 00000000 BBR_0 H 0064 BAR_1 H 000ABCDE BAMR_1 H 000000FF BBR_1 H 106A BDR_1 H A512A512 BDMR_1 H 00000000 BRCR H 00000000 Channel 0 Address H 001234...

Page 221: ... 0 Address H 00314156 Address mask H 00000000 Bus cycle Internal CPU bus instruction fetch read operand size is not included in the condition Channel 1 Address H 00055555 Address mask H 00000000 Data H 00000078 Data mask H 0000000F Bus cycle Internal DMA bus data access write byte On channel 0 the setting of the internal CPU bus instruction fetch is ignored On channel 1 a user break occurs when th...

Page 222: ... request is not received immediately before execution of the branch destination 5 User breaks are disabled during UBC module standby mode Do not read from or write to the UBC registers during UBC module standby mode the values are not guaranteed 6 Do not set an address within an interrupt exception handling routine whose interrupt priority level is at least 15 including user break interrupts as a ...

Page 223: ...algorithm 8 1 1 Cache Structure The cache separates data and instructions and uses a 4 way set associative system It is composed of four ways banks each of which is divided into an address section and a data section Each of the address and data sections is divided into 128 entries The data section of the entry is called a line Each line consists of 16 bytes 4 bytes 4 The data capacity per way is 2...

Page 224: ...s not The tag address holds the physical address used in the external memory access It consists of 21 bits address bits 31 to 11 used for comparison during cache searches In this LSI the addresses of the cache enabled space are H 00000000 to H 1FFFFFFF see section 9 Bus State Controller BSC and therefore the upper three bits of the tag address are cleared to 0 The V and U bits are initialized to 0...

Page 225: ...the cache lock function only for operand cache is not used concerning the case where the cache lock function is used see section 8 2 2 Cache Control Register 2 CCR2 If a bit pattern other than those listed in table 8 1 is set in the LRU bits by software the cache will not function correctly When modifying the LRU bits by software set one of the patterns listed in table 8 1 The LRU bits are initial...

Page 226: ...or disabled using the OCE bit The OCF bit controls disabling of all operand cache entries The WT bit selects either write through mode or write back mode for operand cache Programs that change the contents of CCR1 should be placed in a cache disabled space and a cache enabled space should be accessed after reading the contents of CCR1 CCR1 is initialized to H 00000000 by a power on reset but not i...

Page 227: ...Indicates whether the instruction cache function is enabled disabled 0 Instruction cache disable 1 Instruction cache enable 7 to 4 All 0 R Reserved These bits are always read as 0 The write value should always be 0 3 OCF 0 R W Operand Cache Flush Writing 1 flushes all operand cache entries clears the V U and LRU bits of all operand cache entries to 0 Always reads 0 Write back to external memory is...

Page 228: ... when the prefetch instruction is executed with W3LOAD 1 and W3LOCK 1 specified in cache locking mode while one line data already exists in way 0 which is specified by Rn a cache hit occurs and data is not fetched to way 3 In the cache access other than the prefetch instruction in cache locking mode ways to be replaced by bits W3LOCK and W2LOCK are restricted The relationship between the setting o...

Page 229: ...cache miss occurs by the prefetch instruction while W3LOAD 1 and W3LOCK 1 in cache locking mode the data is always loaded into way 3 Under any other condition the cache miss data is loaded into the way to which LRU points 7 to 2 All 0 R Reserved These bits are always read as 0 The write value should always be 0 1 0 W2LOAD W2LOCK 0 0 R W R W Way 2 Load Way 2 Lock When a cache miss occurs by the pre...

Page 230: ...e same time Table 8 4 Way to be Replaced when a Cache Miss Occurs in Other than PREF Instruction LE W3LOAD W3LOCK W2LOAD W2LOCK Way to be Replaced 0 x x x x Decided by LRU table 8 1 1 x 0 x 0 Decided by LRU table 8 1 1 x 0 x 1 Decided by LRU table 8 5 1 x 1 x 0 Decided by LRU table 8 6 1 x 1 x 1 Decided by LRU table 8 7 Legend x Don t care Note The W3LOAD and W2LOAD bits should not be set to 1 at ...

Page 231: ...0001 101001 101011 2 000100 000110 000111 001111 010100 010110 011110 011111 1 110000 110100 111000 111001 111011 111100 111110 111111 0 Table 8 7 LRU and Way Replacement when W2LOCK 1 and W3LOCK 1 LRU Bits 5 to 0 Way to be Replaced 000000 000001 000011 000100 000110 000111 001011 001111 010100 010110 011110 011111 1 100000 100001 101001 101011 110000 110100 111000 111001 111011 111100 111110 1111...

Page 232: ...che will be searched to see if the desired data is in the cache Figure 8 2 illustrates the method by which the cache is searched Entries are selected using bits 10 to 4 of the address used to access memory and the tag address of that entry is read At this time the upper three bits of the tag address are always cleared to 0 Bits 31 to 11 of the address used to access memory are compared with the re...

Page 233: ...Entry 127 V U LW0 LW1 LW2 LW3 31 10 11 4 3 2 1 0 CMP0 CMP1 CMP2 CMP3 Access address Tag address Address array ways 0 to 3 Data array ways 0 to 3 Legend CMP0 to CMP3 Comparison circuits 0 to 3 Hit signal way 1 Entry selection Longword LW selection Entry 127 Entry 1 Figure 8 2 Cache Search Scheme ...

Page 234: ...1 and LRU is updated so that the replaced way becomes the latest In operand cache the U bit is additionally cleared to 0 When the U bit of the entry to be replaced by updating the entry in write back mode is 1 the cache update cycle starts after the entry is transferred to the write back buffer After the cache completes its update cycle the write back buffer writes the entry back to the memory The...

Page 235: ...the latest After the cache completes its update cycle the write back buffer writes the entry back to the memory The write back unit is 16 bytes In write through mode no write to cache occurs in a write miss the write is only to the external memory 8 3 5 Write Back Buffer Only for Operand Cache When the U bit of the entry to be replaced in the write back mode is 1 it must be written back to the ext...

Page 236: ...l cycle is generated Then write back cycle in write back buffer is generated Renewed to new values by cache renewal cycle Write Hit Write through mode Write cycle CPU issues is generated Renewed to new values by write cycle the CPU issues Write back mode x Not generated Renewed to new values by write cycle the CPU issues Miss Write through mode Write cycle CPU issues is generated Not renewed Write...

Page 237: ...6 Coherency of Cache and External Memory Use software to ensure coherency between the cache and the external memory When memory shared by this LSI and another device is mapped in the cache enabled space operate the memory mapped cache to invalidate and write back as required ...

Page 238: ...longword specify B 00 for bits 1 and 0 of the address The tag address LRU bits U bit only for operand cache and V bit are specified as data Always specify 0 for the upper three bits bits 31 to 29 of the tag address For the address and data formats see figure 8 4 The following three operations are possible for the address array 1 Address Array Read The tag address LRU bits U bit only for operand ca...

Page 239: ...for write accesses must be specified The address field specifies information for selecting the entry to be accessed the data field specifies the longword data to be written to the data array Specify the entry address for selecting the entry the L bit indicating the longword position within the 16 byte line and the W bit for selecting the way In the L bit B 00 is longword 0 B 01 is longword 1 B 10 ...

Page 240: ...Read access Write access b Data specification both read and write accesses 1 2 Data array access both read and write accesses a Address specification Tag address 28 to 11 Entry address b Data specification Longword data Don t care E Bit 10 of entry address for read don t care for write X 0 for read don t care for write Legend Entry address Tag address 28 to 11 Entry address Entry address Entry add...

Page 241: ... 28 11 B 0 0001 0001 0000 0000 0 U 0 V 0 R1 H F080 0088 operand cache address array access entry B 000 1000 A 1 MOV L R0 R1 2 Reading the Data of a Specific Entry The data section of a specific cache entry can be read by the memory mapping cache access The longword indicated in the data field of the data array in figure 8 4 is read into the register An example when an address is specified in R0 an...

Page 242: ...Section 8 Cache Rev 0 50 May 18 2006 Page 212 of 1588 REJ09B0313 0050 ...

Page 243: ...ch address space Controls insertion of wait cycles for each address space Controls insertion of wait cycles for each read access and write access Can set independent idle cycles during the continuous access for five cases read write in same space different spaces read read in same space different spaces the first cycle is a write access 2 Normal space interface Supports the interface that can dire...

Page 244: ... needs an address data multiplexing Supports burst transfer 9 Burst ROM interface clocked synchronous Can connect directly to a ROM of the clocked synchronous type 10 Bus arbitration Shares all of the resources with other CPU and outputs the bus enable after receiving the bus request from external devices 11 Refresh function Supports the auto refresh and self refresh functions Specifies the refres...

Page 245: ...controller Refresh controller Legend Module bus BSC CS0 to CS7 REFOUT WAIT MD A25 to A0 D31 to D0 BACK BREQ BS RD WR RD WE3 to WE0 RASU RASL CASU CASL CKE DQMxx AH FRAME IOIS16 CE2A CE2B CMNCR CSnWCR CSnBCR SDCR RTCSR RTCNT RTCOR Common control register CSn space wait control register n 0 to 7 CSn space bus control register n 0 to 7 SDRAM control register Refresh timer control status register Refr...

Page 246: ... Read pulse signal read data output enable signal Functions as a strobe signal for indicating memory read cycles when PCMCIA is used WE3 DQMUU ICIOWR AH Output Indicates that D31 to D24 are being written to Connected to the byte select signal when a SRAM with byte selection is connected Functions as the select signals for D31 to D24 when SDRAM is connected Functions as a strobe signal for indicati...

Page 247: ...SRAM with byte selection is connected Functions as the select signals for D7 to D0 when SDRAM is connected RASU RASL Output Connects to RAS pin when SDRAM is connected CASU CASL Output Connects to CAS pin when SDRAM is connected CKE Output Connects to CKE pin when SDRAM is connected FRAME Output Functions as FRAME signal when connected to burst MPX I O interface WAIT Input External wait input BREQ...

Page 248: ...e SRAM with byte selection SDRAM H 0C000000 to H 0FFFFFFF CS3 Normal space SRAM with byte selection SDRAM H 10000000 to H 13FFFFFF CS4 Normal space SRAM with byte selection burst ROM asynchronous H 14000000 to H 17FFFFFF CS5 Normal space SRAM with byte selection MPX I O PCMCIA H 18000000 to H 1BFFFFFF CS6 Normal space SRAM with byte selection burst MPX I O PCMCIA H 1C000000 to H 1FFFFFFF CS7 Norma...

Page 249: ...ble data bus widths may be limited depending on the connected memory type After a power on reset the LSI starts execution of the program stored in the external memory allocated in area 0 Since ROM is assumed as the external memory in area 0 minimum pin functions such as the address bus data bus CS0 and RD are available The sample access waveforms shown in this section include other pins such as BS...

Page 250: ...egister CS5BCR R W H 36DB0600 3 H FFFC0018 32 CS6 space bus control register CS6BCR R W H 36DB0600 3 H FFFC001C 32 CS7 space bus control register CS7BCR R W H 36DB0600 3 H FFFC0020 32 CS0 space wait control register CS0WCR R W H 00000500 H FFFC0028 32 CS1 space wait control register CS1WCR R W H 00000500 H FFFC002C 32 CS2 space wait control register CS2WCR R W H 00000500 H FFFC0030 32 CS3 space wa...

Page 251: ...B0400 when the bus width is set to 16 bits 9 4 1 Common Control Register CMNCR CMNCR is a 32 bit register that controls the common items for each area 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 R R R R R W R W R W R W R W R W R W R R R R W R W Bit Initial value...

Page 252: ...10 Accepts neither a refresh request nor a bus mastership request during DMA burst transfer 11 Reserved setting prohibited 8 to 6 DMAIW 2 0 000 R W Wait states between access cycles when DMA single address transfer is performed Specify the number of idle cycles to be inserted after an access to an external device with DACK when DMA single address transfer is performed The method of inserting idle ...

Page 253: ...I insert the idle cycles after an access to an external device with DACK even when the continuous access cycles to an external device with DACK are performed 0 Idle cycles inserted when another device drives the data bus after an external device with DACK drove it 1 Idle cycles always inserted after an access to an external device with DACK 4 1 R Reserved This bit is always read as 1 The write val...

Page 254: ...eadable writable register that specifies the function of each area the number of idle cycles between bus cycles and the bus width Do not access external memory other than area 0 until CSnBCR initial setting is completed Idle cycles may be inserted even when they are not specified For details see section 9 5 12 Wait between Access Cycles 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1...

Page 255: ...cle inserted 001 1 idle cycle inserted 010 2 idle cycles inserted 011 4 idle cycles inserted 100 6 idle cycles inserted 101 8 idle cycles inserted 110 10 idle cycles inserted 111 12 idle cycles inserted 27 to 25 IWRWD 2 0 011 R W Idle Cycles for Another Space Read Write Specify the number of idle cycles to be inserted after the access to a memory that is connected to the space The target access cy...

Page 256: ... 010 2 idle cycles inserted 011 4 idle cycles inserted 100 6 idle cycles inserted 101 8 idle cycles inserted 110 10 idle cycles inserted 111 12 idle cycles inserted 21 to 19 IWRRD 2 0 011 R W Idle Cycles for Read Read in Another Space Specify the number of idle cycles to be inserted after the access to a memory that is connected to the space The target cycle is a read read cycle of which continuou...

Page 257: ...1 8 idle cycles inserted 110 10 idle cycles inserted 111 12 idle cycles inserted 15 0 R Reserved This bit is always read as 0 The write value should always be 0 14 to 12 TYPE 2 0 000 R W Specify the type of memory connected to a space 000 Normal space 001 Burst ROM asynchronous 010 MPX I O 011 SRAM with byte selection 100 SDRAM 101 PCMCIA 110 Burst MPX I O 111 Burst ROM clock synchronous For detai...

Page 258: ...settings in CS0BCR are ignored but the bus width settings in CS1BCR to CS7BCR can be modified 3 If area 6 is specified as burst MPX I O space the bus width can be specified as 32 bits only 4 If area 5 or area 6 is specified as PCMCIA space the bus width can be specified as either 8 bits or 16 bits 5 If area 2 or area 3 is specified as SDRAM space the bus width can be specified as either 16 bits or...

Page 259: ...R R R R R R R R R R R W R W R R R W R W 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 R R R R W R W R W R W R W R W R W R R R R R W R W Bit Initial value R W Bit Initial value R W BAS SW 1 0 WR 3 0 WM HW 1 0 Bit Bit Name Initial Value R W Description 31 to 22 All 0 R Reserved These bits are always read as 0 The write value should always be 0 21 0 R W Reserved Set this bit to 0 when the interface for normal spac...

Page 260: ...0 R W Reserved Set this bit to 0 when the interface for normal space or SRAM with byte selection is used 15 to 13 All 0 R Reserved These bits are always read as 0 The write value should always be 0 12 11 SW 1 0 00 R W Number of Delay Cycles from Address CS0 Assertion to RD WEn Assertion Specify the number of delay cycles from address and CS0 assertion to RD and WEn assertion 00 0 5 cycles 01 1 5 c...

Page 261: ...10 6 cycles 0111 8 cycles 1000 10 cycles 1001 12 cycles 1010 14 cycles 1011 18 cycles 1100 24 cycles 1101 Reserved setting prohibited 1110 Reserved setting prohibited 1111 Reserved setting prohibited 6 WM 0 R W External Wait Mask Specification Specifies whether or not the external wait input is valid The specification by this bit is valid even when the number of access wait cycle is 0 0 External w...

Page 262: ...bits CS1WCR CS7WCR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R W R R W R W R W 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 R R R R W R W R W R W R W R W R W R R R R R W R W Bit Initial value R W Bit Initial value R W BAS WW 2 0 SW 1 0 WR 3 0 WM HW 1 0 Bit Bit Name Initial Value R W Description 31 to 21 All 0 R Re...

Page 263: ...essary for write access 000 The same cycles as WR 3 0 setting number of read access wait cycles 001 No cycle 010 1 cycle 011 2 cycles 100 3 cycles 101 4 cycles 110 5 cycles 111 6 cycles 15 to 13 All 0 R Reserved These bits are always read as 0 The write value should always be 0 12 11 SW 1 0 00 R W Number of Delay Cycles from Address CSn Assertion to RD WEn Assertion Specify the number of delay cyc...

Page 264: ...ved setting prohibited 1110 Reserved setting prohibited 1111 Reserved setting prohibited 6 WM 0 R W External Wait Mask Specification Specifies whether or not the external wait input is valid The specification by this bit is valid even when the number of access wait cycle is 0 0 External wait input is valid 1 External wait input is ignored 5 to 2 All 0 R Reserved These bits are always read as 0 The...

Page 265: ...M Bit Bit Name Initial Value R W Description 31 to 21 All 0 R Reserved These bits are always read as 0 The write value should always be 0 20 BAS 0 R W SRAM with Byte Selection Byte Access Select Specifies the WEn and RD WR signal timing when the SRAM interface with byte selection is used 0 Asserts the WEn signal at the read timing and asserts the RD WR signal during the write access cycle 1 Assert...

Page 266: ...10 6 cycles 0111 8 cycles 1000 10 cycles 1001 12 cycles 1010 14 cycles 1011 18 cycles 1100 24 cycles 1101 Reserved setting prohibited 1110 Reserved setting prohibited 1111 Reserved setting prohibited 6 WM 0 R W External Wait Mask Specification Specifies whether or not the external wait input is valid The specification by this bit is valid even when the number of access wait cycle is 0 0 External w...

Page 267: ...ld always be 0 20 BAS 0 R W SRAM with Byte Selection Byte Access Select Specifies the WEn and RD WR signal timing when the SRAM interface with byte selection is used 0 Asserts the WEn signal at the read timing and asserts the RD WR signal during the write access cycle 1 Asserts the WEn signal during the read access cycle and asserts the RD WR signal at the write timing 19 0 R Reserved This bit is ...

Page 268: ... of delay cycles from address and CS4 assertion to RD and WE assertion 00 0 5 cycles 01 1 5 cycles 10 2 5 cycles 11 3 5 cycles 10 to 7 WR 3 0 1010 R W Number of Read Access Wait Cycles Specify the number of cycles that are necessary for read access 0000 No cycle 0001 1 cycle 0010 2 cycles 0011 3 cycles 0100 4 cycles 0101 5 cycles 0110 6 cycles 0111 8 cycles 1000 10 cycles 1001 12 cycles 1010 14 cy...

Page 269: ...ts are always read as 0 The write value should always be 0 1 0 HW 1 0 00 R W Delay Cycles from RD WEn Negation to Address CS4 Negation Specify the number of delay cycles from RD and WEn negation to address and CS4 negation 00 0 5 cycles 01 1 5 cycles 10 2 5 cycles 11 3 5 cycles CS5WCR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ...

Page 270: ... bits 0 1 Not affected 16 bits 1 Not affected 0 8 bits 1 Not affected 1 16 bits 21 SZSEL 0 R W 20 MPXW 0 R W MPX I O Interface Address Wait This bit setting is valid only when area 5 is specified as MPX I O Specifies the address cycle insertion wait for MPX I O interface 0 Inserts no wait cycle 1 Inserts 1 wait cycle BAS 0 R W SRAM with Byte Selection Byte Access Select This bit setting is valid o...

Page 271: ...cles as WR 3 0 setting number of read access wait cycles 001 No cycle 010 1 cycle 011 2 cycles 100 3 cycles 101 4 cycles 110 5 cycles 111 6 cycles 15 to 13 All 0 R Reserved These bits are always read as 0 The write value should always be 0 12 11 SW 1 0 00 R W Number of Delay Cycles from Address CS5 Assertion to RD WE Assertion Specify the number of delay cycles from address and CS5 assertion to RD...

Page 272: ...ved setting prohibited 1110 Reserved setting prohibited 1111 Reserved setting prohibited 6 WM 0 R W External Wait Mask Specification Specifies whether or not the external wait input is valid The specification by this bit is valid even when the number of access wait cycle is 0 0 External wait input is valid 1 External wait input is ignored 5 to 2 All 0 R Reserved These bits are always read as 0 The...

Page 273: ... value should always be 0 20 BAS 0 R W SRAM with Byte Selection Byte Access Select Specifies the WEn and RD WR signal timing when the SRAM interface with byte selection is used 0 Asserts the WEn signal at the read timing and asserts the RD WR signal during the write access cycle 1 Asserts the WEn signal during the read write access cycle and asserts the RD WR signal at the write timing 19 to 13 Al...

Page 274: ...ting prohibited 1110 Reserved setting prohibited 1111 Reserved setting prohibited 6 WN 0 R W External Wait Mask Specification Specifies whether or not the external wait input is valid The specification of this bit is valid even when the number of access wait cycles is 0 0 The external wait input is valid 1 The external wait input is ignored 5 to 2 All 0 R Reserved These bits are always read as 0 T...

Page 275: ...R W Bit Initial value R W BST 1 0 BW 1 0 W 3 0 WM Bit Bit Name Initial Value R W Description 31 to 22 All 0 R Reserved These bits are always read as 0 The write value should always be 0 Burst Count Specification Specify the burst count for 16 byte access These bits must not be set to B 11 Bus Width BST 1 0 Burst count 00 16 burst one time 8 bits 01 4 burst four times 00 8 burst one time 01 2 burst...

Page 276: ...ycles 11 3 cycles 15 to 11 All 0 R Reserved These bits are always read as 0 The write value should always be 0 10 to 7 W 3 0 1010 R W Number of Access Wait Cycles Specify the number of wait cycles to be inserted in the first access cycle 0000 No cycle 0001 1 cycle 0010 2 cycles 0011 3 cycles 0100 4 cycles 0101 5 cycles 0110 6 cycles 0111 8 cycles 1000 10 cycles 1001 12 cycles 1010 14 cycles 1011 1...

Page 277: ...18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R W R W R R R W R W 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 R R R R W R W R W R W R W R W R W R R R R R W R W Bit Initial value R W Bit Initial value R W BST 1 0 BW 1 0 SW 1 0 W 3 0 WM HW 1 0 Bit Bit Name Initial Value R W Description 31 to 22 All 0 R Reserved These bits are always read as 0 The write value ...

Page 278: ... the number of wait cycles to be inserted between the second or subsequent access cycles in burst access 00 No cycle 01 1 cycle 10 2 cycles 11 3 cycles 15 to 13 All 0 R Reserved These bits are always read as 0 The write value should always be 0 12 11 SW 1 0 00 R W Number of Delay Cycles from Address CS4 Assertion to RD WE Assertion Specify the number of delay cycles from address and CS4 assertion ...

Page 279: ...served setting prohibited 1110 Reserved setting prohibited 1111 Reserved setting prohibited 6 WM 0 R W External Wait Mask Specification Specifies whether or not the external wait input is valid The specification by this bit is valid even when the number of access wait cycle is 0 0 External wait input is valid 1 External wait input is ignored 5 to 2 All 0 R Reserved These bits are always read as 0 ...

Page 280: ...cription 31 to 11 All 0 R Reserved These bits are always read as 0 The write value should always be 0 10 1 R Reserved This bit is always read as 1 The write value should always be 1 9 0 R Reserved This bit is always read as 0 The write value should always be 0 8 7 A2CL 1 0 10 R W CAS Latency for Area 2 Specify the CAS latency for area 2 00 1 cycle 01 2 cycles 10 3 cycles 11 4 cycles 6 to 0 All 0 R...

Page 281: ... 1 0 Bit Bit Name Initial Value R W Description 31 to 15 All 0 R Reserved These bits are always read as 0 The write value should always be 0 14 13 WTRP 1 0 00 R W Number of Auto Precharge Completion Wait Cycles Specify the number of minimum precharge completion wait cycles as shown below From the start of auto precharge and issuing of ACTV command for the same bank From issuing of the PRE PALL com...

Page 282: ... Command Specify the minimum number of wait cycles from issuing the ACTV command to issuing the READ A WRIT A command The setting for areas 2 and 3 is common 00 No cycle 01 1 cycle 10 2 cycles 11 3 cycles 9 0 R Reserved This bit is always read as 0 The write value should always be 0 8 7 A3CL 1 0 10 R W CAS Latency for Area 3 Specify the CAS latency for area 3 00 1 cycle 01 2 cycles 10 3 cycles 11 ...

Page 283: ...f the WRITA command until the issuance of the ACTV command Confirm that how many cycles are required between the WRITE command receive in the SDRAM and the auto precharge activation referring to each SDRAM data sheet And set the cycle number so as not to exceed the cycle number specified by this bit Cycle number from the issuance of the WRITA command until the issuance of the PRE command This is t...

Page 284: ...m the issuance of the REF command until the issuance of the ACTV REF MRS command From releasing self refresh until the issuance of the ACTV REF MRS command The setting for areas 2 and 3 is common 00 2 cycles 01 3 cycles 10 5 cycles 11 8 cycles Note If both areas 2 and 3 are specified as SDRAM WTRP 1 0 WTRCD 1 0 TRWL 1 0 and WTRC 1 0 bit settings are used in both areas in common If only one area is...

Page 285: ... 0 PCW 3 0 TEH 3 0 WM Bit Bit Name Initial Value R W Description 31 to 22 All 0 R Reserved These bits are always read as 0 The write value should always be 0 21 20 SA 1 0 00 R W Space Attribute Specification Select memory card interface or I O card interface when PCMCIA interface is selected SA1 0 Selects memory card interface for the space for A25 1 1 Selects I O card interface for the space for ...

Page 286: ...Specify the number of delay cycles from address output to RD WE assertion for the memory card or to ICIORD ICIOWR assertion for the I O card in PCMCIA interface 0000 0 5 cycle 0001 1 5 cycles 0010 2 5 cycles 0011 3 5 cycles 0100 4 5 cycles 0101 5 5 cycles 0110 6 5 cycles 0111 7 5 cycles 1000 8 5 cycles 1001 9 5 cycles 1010 10 5 cycles 1011 11 5 cycles 1100 12 5 cycles 1101 13 5 cycles 1110 14 5 cy...

Page 287: ...s 0101 18 cycles 0110 22 cycles 0111 26 cycles 1000 30 cycles 1001 33 cycles 1010 36 cycles 1011 38 cycles 1100 52 cycles 1101 60 cycles 1110 64 cycles 1111 80 cycles 6 WM 0 R W External Wait Mask Specification Specifies whether or not the external wait input is valid The specification by this bit is valid even when the number of access wait cycles is 0 0 External wait input is valid 1 External wa...

Page 288: ... the number of address hold cycles from RD WE negation for the memory card or those from ICIORD ICIOWR negation for the I O card in PCMCIA interface 0000 0 5 cycle 0001 1 5 cycles 0010 2 5 cycles 0011 3 5 cycles 0100 4 5 cycles 0101 5 5 cycles 0110 6 5 cycles 0111 7 5 cycles 1000 8 5 cycles 1001 9 5 cycles 1010 10 5 cycles 1011 11 5 cycles 1100 12 5 cycles 1101 13 5 cycles 1110 14 5 cycles 1111 15...

Page 289: ...W R R W R W 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 R R R R R R W R W R W R W R W R R R R R R Bit Initial value R W Bit Initial value R W MPXAW 1 0 MPXMD BW 1 0 W 3 0 WM Bit Bit Name Initial Value R W Description 31 to 22 All 0 R Reserved These bits are always read as 0 The write value should always be 0 21 20 MPXAW 1 0 00 R W Number of Address Cycle Waits Specify the number of waits to be inserted in the...

Page 290: ... 1 Word 2 bytes 0 1 0 Longword 4 bytes 0 1 1 Reserved quadword 8 bytes 1 0 0 16 bytes 1 0 1 Reserved 32 bytes 1 1 0 Reserved 64 bytes Transfer size when MPXMD 1 D31 D30 D29 Transfer Size 0 0 0 Byte 1 byte 0 0 1 Word 2 bytes 0 1 0 Longword 4 bytes 0 1 1 Quadword 8 bytes 1 0 0 Reserved 32 bytes 19 MPXMD 0 R W 18 0 R Reserved This bit is always read as 0 The write value should always be 0 17 16 BW 1 ...

Page 291: ...les 0011 3 cycles 0100 4 cycles 0101 5 cycles 0110 6 cycles 0111 8 cycles 1000 10 cycles 1001 12 cycles 1010 14 cycles 1011 18 cycles 1100 24 cycles 1101 Reserved setting prohibited 1110 Reserved setting prohibited 1111 Reserved setting prohibited 6 WM 0 R W External Wait Mask Specification Specifies whether or not the external wait input is valid The specification by this bit is valid even when t...

Page 292: ... W R W R W R W R W R R R R R R Bit Initial value R W Bit Initial value R W BW 1 0 W 3 0 WM Bit Bit Name Initial Value R W Description 31 to 18 All 0 R Reserved These bits are always read as 0 The write value should always be 0 17 16 BW 1 0 00 R W Number of Burst Wait Cycles Specify the number of wait cycles to be inserted between the second or subsequent access cycles in burst access 00 No cycle 0...

Page 293: ...0110 6 cycles 0111 8 cycles 1000 10 cycles 1001 12 cycles 1010 14 cycles 1011 18 cycles 1100 24 cycles 1101 Reserved setting prohibited 1110 Reserved setting prohibited 1111 Reserved setting prohibited 6 WM 0 R W External Wait Mask Specification Specifies whether or not the external wait input is valid The specification by this bit is valid even when the number of access wait cycle is 0 0 External...

Page 294: ...R W Bit Initial value R W A2ROW 1 0 A3ROW 1 0 A2COL 1 0 A3COL 1 0 DEEP SLOW RFSH RMODEPDOWN BACTV Bit Bit Name Initial Value R W Description 31 to 21 All 0 R Reserved These bits are always read as 0 The write value should always be 0 20 19 A2ROW 1 0 00 R W Number of Bits of Row Address for Area 2 Specify the number of bits of row address for area 2 00 11 bits 01 12 bits 10 13 bits 11 Reserved sett...

Page 295: ...y Mode Specifies the output timing of command address and write data for SDRAM and the latch timing of read data from SDRAM Setting this bit makes the hold time for command address write and read data extended for half cycle output or read at the falling edge of CKIO This mode is suitable for SDRAM with low frequency clock 0 Command address and write data for SDRAM is output at the rising edge of ...

Page 296: ...ess to the SDRAM With this bit being set to 1 after the SDRAM is accessed the CKE signal is driven low and the SDRAM enters the power down mode 0 The SDRAM does not enter the power down mode after being accessed 1 The SDRAM enters the power down mode after being accessed 8 BACTV 0 R W Bank Active Mode Specifies to access whether in auto precharge mode using READA and WRITA commands or in bank acti...

Page 297: ...ea 3 Specify the number of bits of the row address for area 3 00 11 bits 01 12 bits 10 13 bits 11 Reserved setting prohibited 2 0 R Reserved This bit is always read as 0 The write value should always be 0 1 0 A3COL 1 0 00 R W Number of Bits of Column Address for Area 3 Specify the number of bits of the column address for area 3 00 8 bits 01 9 bits 10 10 bits 11 Reserved setting prohibited ...

Page 298: ... value other than B 000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R W R W R W R W R W R W R W R W Bit Initial value R W Bit Initial value R W CMF CMIE CKS 2 0 RRC 2 0 Bit Bit Name Initial Value R W Description 31 to 8 All 0 R Reserved These bit...

Page 299: ...ount up the refresh timer counter RTCNT 000 Stop the counting up 001 Bφ 4 010 Bφ 16 011 Bφ 64 100 Bφ 256 101 Bφ 1024 110 Bφ 2048 111 Bφ 4096 2 to 0 RRC 2 0 000 R W Refresh Count Specify the number of continuous refresh cycles when the refresh request occurs after the coincidence of the values of the refresh timer counter RTCNT and the refresh time constant register RTCOR These bits can make the pe...

Page 300: ...o 255 When the RTCNT is written the upper 16 bits of the write data must be H A55A to cancel write protection 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R W R W R W R W R W R W R W R W Bit Initial value R W Bit Initial value R W Bit Bit Name Ini...

Page 301: ...tration When the CMIE bit in RTCSR is set to 1 an interrupt request is issued by this matching signal The request continues to be output until the CMF bit in RTCSR is cleared Clearing the CMF bit only affects the interrupt request and does not clear the refresh request Therefore a combination of refresh request and interval timer interrupt can be specified so that the number of refresh requests ar...

Page 302: ... Sequence to Write to ACSWR Read is done by the normal longword 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R W R W R W R W ACOSW 3 0 Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W Description 31 to 4 All 0 R R...

Page 303: ... only 8 bit register to access the AC characteristics switching register ACSWR The write value is ignored and the read value is undefined 7 6 5 4 3 2 1 0 W W W W W W W W Bit Initial value R W ACKEY 7 0 Bit Bit Name Initial Value R W Description 7 to 0 ACKEY 7 0 W AC Key Writing to this bit is required to write to the ACSWR register The write value is arbitrary ...

Page 304: ...tine Subroutine executed in on chip RAM 1 2 3 4 Incorrectly written Correcrly written Make sure to read and confirm as in step 4 after the write in step 3 If incorrectly written execute from step 1 again Transfer write subroutine to on chip RAM Write subroutine Return Byte write to ACKEYR Byte write to ACKEYR Longword write to ACSWR Read ACSWR to confirm Execute write subroutine Figure 9 2 Recomme...

Page 305: ...r made selectable as 8 bits or 16 bits by one of the address lines The data bus width for burst MPX I O is fixed at 32 bits Data alignment is in accord with the data bus width selected for the device This also means that four read operations are required to read longword data from a byte width device In this LSI data alignment and conversion of data length is performed automatically between the re...

Page 306: ...6 D15 to D8 D7 to D0 WE3 DQMUU WE2 DQMUL WE1 DQMLU WE0 DQMLL Byte access at 0 Data 7 to 0 Assert Byte access at 1 Data 7 to 0 Assert Byte access at 2 Data 7 to 0 Assert Byte access at 3 Data 7 to 0 Assert Word access at 0 Data 15 to 8 Data 7 to 0 Assert Assert Word access at 2 Data 15 to 8 Data 7 to 0 Assert Assert Longword access at 0 Data 31 to 24 Data 23 to 16 Data 15 to 8 Data 7 to 0 Assert As...

Page 307: ... to D0 WE3 DQMUU WE2 DQMUL WE1 DQMLU WE0 DQMLL Byte access at 0 Data 7 to 0 Assert Byte access at 1 Data 7 to 0 Assert Byte access at 2 Data 7 to 0 Assert Byte access at 3 Data 7 to 0 Assert Word access at 0 Data 15 to 8 Data 7 to 0 Assert Assert Word access at 2 Data 15 to 8 Data 7 to 0 Assert Assert 1st time at 0 Data 31 to 24 Data 23 to 16 Assert Assert Longword access at 0 2nd time at 2 Data 1...

Page 308: ...MLL Byte access at 0 Data 7 to 0 Assert Byte access at 1 Data 7 to 0 Assert Byte access at 2 Data 7 to 0 Assert Byte access at 3 Data 7 to 0 Assert 1st time at 0 Data 15 to 8 Assert Word access at 0 2nd time at 1 Data 7 to 0 Assert 1st time at 2 Data 15 to 8 Assert Word access at 2 2nd time at 3 Data 7 to 0 Assert 1st time at 0 Data 31 to 24 Assert 2nd time at 1 Data 23 to 16 Assert 3rd time at 2 ...

Page 309: ...16 D15 to D8 D7 to D0 WE3 DQMUU WE2 DQMUL WE1 DQMLU WE0 DQMLL Byte access at 0 Data 7 to 0 Assert Byte access at 1 Data 7 to 0 Assert Byte access at 2 Data 7 to 0 Assert Byte access at 3 Data 7 to 0 Assert Word access at 0 Data 15 to 8 Data 7 to 0 Assert Assert Word access at 2 Data 15 to 8 Data 7 to 0 Assert Assert Longword access at 0 Data 31 to 24 Data 23 to 16 Data 15 to 8 Data 7 to 0 Assert A...

Page 310: ...7 to D0 WE3 DQMUU WE2 DQMUL WE1 DQMLU WE0 DQMLL Byte access at 0 Data 7 to 0 Assert Byte access at 1 Data 7 to 0 Assert Byte access at 2 Data 7 to 0 Assert Byte access at 3 Data 7 to 0 Assert Word access at 0 Data 15 to 8 Data 7 to 0 Assert Assert Word access at 2 Data 15 to 8 Data 7 to 0 Assert Assert 1st time at 0 Data 15 to 8 Data 7 to 0 Assert Assert Longword access at 0 2nd time at 2 Data 31 ...

Page 311: ...DQMLL Byte access at 0 Data 7 to 0 Assert Byte access at 1 Data 7 to 0 Assert Byte access at 2 Data 7 to 0 Assert Byte access at 3 Data 7 to 0 Assert 1st time at 0 Data 7 to 0 Assert Word access at 0 2nd time at 1 Data 15 to 8 Assert 1st time at 2 Data 7 to 0 Assert Word access at 2 2nd time at 3 Data 15 to 8 Assert 1st time at 0 Data 7 to 0 Assert 2nd time at 1 Data 15 to 8 Assert 3rd time at 2 D...

Page 312: ... shows the basic timings of normal space access A no wait normal access is completed in two cycles The BS signal is asserted for one cycle to indicate the start of a bus cycle CKIO Note The waveform for DACKn is when active low is specified A25 to A0 RD WR RD WR D31 to D0 DACKn CSn T1 T2 RD WEn BS D31 to D0 Read Write Figure 9 3 Normal Space Basic Access Timing Access Wait 0 There is no access siz...

Page 313: ...taken when controlling the external data buffer to avoid collision Figures 9 4 and 9 5 show the basic timings of normal space access If the WM bit in CSnWCR is cleared to 0 a Tnop cycle is inserted after the CSn space access to evaluate the external wait figure 9 4 If the WM bit in CSnWCR is set to 1 external waits are ignored and no Tnop cycle is inserted figure 9 5 CKIO A25 to A0 RD RD WR D15 to...

Page 314: ...313 0050 CKIO A25 to A0 RD WR D15 to D0 DACKn CSn T1 T2 T1 T2 RD WEn BS WAIT D15 to D0 Read Write Note The waveform for DACKn is when active low is specified Figure 9 5 Continuous Access for Normal Space 2 Bus Width 16 Bits Longword Access CSnWCR WM Bit 1 Access Wait 0 Cycle Wait 0 ...

Page 315: ...of 1588 REJ09B0313 0050 A16 A0 CS OE I O7 I O0 WE A18 A2 CSn RD D31 D24 WE3 D23 D16 WE2 D15 D8 WE1 D7 D0 WE0 This LSI 128K 8 bit SRAM A16 A0 CS OE I O7 I O0 WE A16 A0 CS OE I O7 I O0 WE A16 A0 CS OE I O7 I O0 WE Figure 9 6 Example of 32 Bit Data Width SRAM Connection ...

Page 316: ... A0 CS OE I O7 I O0 WE A17 A1 CSn RD D15 D8 WE1 D7 D0 WE0 This LSI 128K 8 bit SRAM A16 A0 CS OE I O7 I O0 WE Figure 9 7 Example of 16 Bit Data Width SRAM Connection This LSI 128K 8 bit SRAM A16 A0 CS OE I O7 I O0 WE A16 A0 CSn RD D7 D0 WE0 Figure 9 8 Example of 8 Bit Data Width SRAM Connection ...

Page 317: ...d 8 to insert wait cycles independently in read access and in write access Areas 0 2 3 and 6 have common access wait for read cycle and write cycle The specified number of Tw cycles are inserted as wait cycles in a normal space access shown in figure 9 9 T1 CKIO A25 to A0 CSn RD WR RD D31 to D0 WEn D31 to D0 BS Tw Read Write T2 DACKn Note The waveform for DACKn is when active low is specified Figu...

Page 318: ...le wait is specified as a software wait The WAIT signal is sampled on the falling edge of CKIO at the transition from the T1 or Tw cycle to the T2 cycle T1 CKIO A25 to A0 CSn RD WR RD D31 to D0 WEn D31 to D0 WAIT Tw Tw Twx T2 Read Write BS Wait states inserted by WAIT signal DACKn Note The waveform for DACKn is when active low is specified Figure 9 10 Wait Cycle Timing for Normal Space Access Wait...

Page 319: ... a flexible interface to an external device can be obtained Figure 9 11 shows an example A Th cycle and a Tf cycle are added before and after an ordinary cycle respectively In these cycles RD and WEn are not asserted while other signals are asserted The data output is prolonged to the Tf cycle and this prolongation is useful for devices with slow writing operations T1 CKIO A25 to A0 CSn RD WR RD D...

Page 320: ...16 bits Alternatively it can be 8 bits or 16 bits depending on the address to be accessed Output of the addresses D15 to D0 or D7 to D0 is performed from cycle Ta2 to cycle Ta3 Because cycle Ta1 has a high impedance state collisions of addresses and data can be avoided without inserting idle cycles even in continuous access cycles Address output is increased to 3 cycles by setting the MPXW bit in ...

Page 321: ...09B0313 0050 T1 CKIO A25 to A0 CS5 RD WR RD D15 D7 to D0 WEn D15 D7 to D0 BS Read Write T2 DACKn Ta1 Ta2 Ta3 AH Address Address Data Data Note The waveform for DACKn is when active low is specified Figure 9 12 Access Timing for MPX Space Address Cycle No Wait Data Cycle No Wait ...

Page 322: ...B0313 0050 T1 CKIO A25 to A0 CS5 RD WR RD D15 D7 to D0 WEn D15 D7 to D0 BS Read Write T2 DACKn Ta1 Ta2 Ta3 AH Address Address Data Data Tadw Note The waveform for DACKn is when active low is specified Figure 9 13 Access Timing for MPX Space Address Cycle Wait 1 Data Cycle No Wait ...

Page 323: ...O A25 to A0 CS5 RD WR RD D15 D7 to D0 WEn D15 D7 to D0 BS Read Write T2 DACKn Ta1 Ta2 Ta3 AH Address Address Data Data Tadw Tw Twx WAIT Note The waveform for DACKn is when active low is specified Figure 9 14 Access Timing for MPX Space Address Cycle Access Wait 1 Data Cycle Wait 1 External Wait 1 ...

Page 324: ...he area that is connected to SDRAM can be set to 32 or 16 bits Burst read single write burst length 1 and burst read burst write burst length 1 are supported as the SDRAM operating mode Commands for SDRAM can be specified by RASU RASL CASU CASL RD WR and specific address signals These commands supports NOP Auto refresh REF Self refresh SELF All banks pre charge PALL Specified bank pre charge PRE B...

Page 325: ...ied by RASL and CASL and 4 banks specified by RASU and CASU When accessing the address with A25 0 RASL and CASL are asserted When accessing the address with A25 1 RASU and CASU are asserted A15 A2 CKE CKIO CSn RASU CASU RASL CASL RD WR D31 D16 DQMUU DQMUL D15 D0 DQMLU DQMLL 64M SDRAM 1M 16 bit 4 bank A13 A0 CKE CLK CS RAS CAS WE I O15 I O0 DQMU DQML A13 A0 CKE CLK CS RAS CAS WE I O15 I O0 DQMU DQM...

Page 326: ...1588 REJ09B0313 0050 A14 A1 CKE CKIO CSn RASU CASU RASL CASL RD WR D15 D0 DQMLU DQMLL 64M SDRAM 1M 16 bit 4 bank A13 A0 CKE CLK CS RAS CAS WE I O15 I O0 DQMU DQML This LSI Unused Unused Figure 9 16 Example of 16 Bit Data Width SDRAM Connection RASU and CASU are Not Used ...

Page 327: ...0050 A14 A1 CKE CKIO CSn RASU CASU RASL CASL RD WR D15 D0 DQMLU DQMLL 64M SDRAM 1M 16 bit 4 bank A13 A0 CKE CLK CS RAS CAS WE I O15 I O0 DQMU DQML A13 A0 CKE CLK CS RAS CAS WE I O15 I O0 DQMU DQML This LSI Figure 9 17 Example of 16 Bit Data Width SDRAM Connection RASU and CASU are Used ...

Page 328: ...utput at the address pins Do not specify those bits in the manner other than this table otherwise the operation of this LSI is not guaranteed A25 to A18 are not multiplexed and the original values of address are always output at these pins When the data bus width is 16 bits BSZ1 and BSZ0 B 10 A0 of SDRAM specifies a word address Therefore connect this A0 pin of SDRAM to the A1 pin of the LSI the A...

Page 329: ... A15 Unused A14 A22 2 A22 2 A12 BA1 A13 A21 2 A21 2 A11 BA0 Specifies bank A12 A20 L H 1 A10 AP Specifies address precharge A11 A19 A11 A9 A10 A18 A10 A8 A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11 A3 A1 A2 A10 A2 A0 Address A1 A9 A1 A0 A8 A0 Unused Example of connected memory 64 Mbit product 512 Kwords 32 bits 4 banks column 8 bits product 1 16 Mbit produc...

Page 330: ... A23 2 A23 2 A13 BA1 A14 A22 2 A22 2 A12 BA0 Specifies bank A13 A21 A13 A11 Address A12 A20 L H 1 A10 AP Specifies address precharge A11 A19 A11 A9 A10 A18 A10 A8 A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11 A3 A1 A2 A10 A2 A0 Address A1 A9 A1 A0 A8 A0 Unused Example of connected memory 128 Mbit product 1 Mword 32 bits 4 banks column 8 bits product 1 64 Mbit...

Page 331: ...es bank A13 A22 A13 A11 Address A12 A21 L H 1 A10 AP Specifies address precharge A11 A20 A11 A9 A10 A19 A10 A8 A9 A18 A9 A7 A8 A17 A8 A6 A7 A16 A7 A5 A6 A15 A6 A4 A5 A14 A5 A3 A4 A13 A4 A2 A3 A12 A3 A1 A2 A11 A2 A0 Address A1 A10 A1 A0 A9 A0 Unused Example of connected memory 256 Mbit product 2 Mwords 32 bits 4 banks column 9 bits product 1 128 Mbit product 2 Mwords 16 bits 4 banks column 9 bits p...

Page 332: ...ies bank A13 A23 A13 A11 Address A12 A22 L H 1 A10 AP Specifies address precharge A11 A21 A11 A9 A10 A20 A10 A8 A9 A19 A9 A7 A8 A18 A8 A6 A7 A17 A7 A5 A6 A16 A6 A4 A5 A15 A5 A3 A4 A14 A4 A2 A3 A13 A3 A1 A2 A12 A2 A0 Address A1 A11 A1 A0 A10 A0 Unused Example of connected memory 512 Mbit product 4 Mwords 32 bits 4 banks column 10 bits product 1 256 Mbit product 4 Mwords 16 bits 4 banks column 10 bi...

Page 333: ...3 A14 A12 A13 A22 A13 A11 Address A12 A21 L H 1 A10 AP Specifies address precharge A11 A20 A11 A9 A10 A19 A10 A8 A9 A18 A9 A7 A8 A17 A8 A6 A7 A16 A7 A5 A6 A15 A6 A4 A5 A14 A5 A3 A4 A13 A4 A2 A3 A12 A3 A1 A2 A11 A2 A0 Address A1 A10 A1 A0 A9 A0 Unused Example of connected memory 512 Mbit product 4 Mwords 32 bits 4 banks column 9 bits product 1 256 Mbit product 4 Mwords 16 bits 4 banks column 9 bits...

Page 334: ...A17 A25 A17 A16 A24 A16 A15 A23 A15 A14 A22 A14 Unused A13 A21 2 A21 2 A12 BA1 A12 A20 2 A20 2 A11 BA0 Specifies bank A11 A19 L H 1 A10 AP Specifies address precharge A10 A18 A10 A9 A9 A17 A9 A8 A8 A16 A8 A7 A7 A15 A7 A6 A6 A14 A6 A5 A5 A13 A5 A4 A4 A12 A4 A3 A3 A11 A3 A2 A2 A10 A2 A1 A1 A9 A1 A0 Address A0 A8 A0 Unused Example of connected memory 16 Mbit product 512 Kwords 16 bits 2 banks column ...

Page 335: ...7 A25 A17 A16 A24 A16 A15 A23 A15 Unused A14 A22 2 A22 2 A13 BA1 A13 A21 2 A21 2 A12 BA0 Specifies bank A12 A20 A12 A11 Address A11 A19 L H 1 A10 AP Specifies address precharge A10 A18 A10 A9 A9 A17 A9 A8 A8 A16 A8 A7 A7 A15 A7 A6 A6 A14 A6 A5 A5 A13 A5 A4 A4 A12 A4 A3 A3 A11 A3 A2 A2 A10 A2 A1 A1 A9 A1 A0 Address A0 A8 A0 Unused Example of connected memory 64 Mbit product 1 Mword 16 bits 4 banks ...

Page 336: ...6 A17 A16 A25 A16 A15 A24 A15 Unused A14 A23 2 A23 2 A13 BA1 A13 A22 2 A22 2 A12 BA0 Specifies bank A12 A21 A12 A11 Address A11 A20 L H 1 A10 AP Specifies address precharge A10 A19 A10 A9 A9 A18 A9 A8 A8 A17 A8 A7 A7 A16 A7 A6 A6 A15 A6 A5 A5 A14 A5 A4 A4 A13 A4 A3 A3 A12 A3 A2 A2 A11 A2 A1 A1 A10 A1 A0 Address A0 A9 A0 Unused Example of connected memory 128 Mbit product 2 Mwords 16 bits 4 banks c...

Page 337: ...7 A17 A16 A26 A16 A15 A25 A15 Unused A14 A24 2 A24 2 A13 BA1 A13 A23 2 A23 2 A12 BA0 Specifies bank A12 A22 A12 A11 Address A11 A21 L H 1 A10 AP Specifies address precharge A10 A20 A10 A9 A9 A19 A9 A8 A8 A18 A8 A7 A7 A17 A7 A6 A6 A16 A6 A5 A5 A15 A5 A4 A4 A14 A4 A3 A3 A13 A3 A2 A2 A12 A2 A1 A1 A11 A1 A0 Address A0 A10 A0 Unused Example of connected memory 256 Mbit product 4 Mwords 16 bits 4 banks ...

Page 338: ... A23 2 A23 2 A13 BA0 Specifies bank A13 A22 A13 A12 A12 A21 A12 A11 Address A11 A20 L H 1 A10 AP Specifies address precharge A10 A19 A10 A9 A9 A18 A9 A8 A8 A17 A8 A7 A7 A16 A7 A6 A6 A15 A6 A5 A5 A14 A5 A4 A4 A13 A4 A3 A3 A12 A3 A2 A2 A11 A2 A1 A1 A10 A1 A0 Address A0 A9 A0 Unused Example of connected memory 256 Mbit product 4 Mwords 16 bits 4 banks column 9 bits product 1 Notes 1 L H is a bit used...

Page 339: ...14 A24 2 A24 2 A13 BA0 Specifies bank A13 A23 A13 A12 A12 A22 A12 A11 Address A11 A21 L H 1 A10 AP Specifies address precharge A10 A20 A10 A9 A9 A19 A9 A8 A8 A18 A8 A7 A7 A17 A7 A6 A6 A16 A6 A5 A5 A15 A5 A4 A4 A14 A4 A3 A3 A13 A3 A2 A2 A12 A2 A1 A1 A11 A1 A0 Address A0 A10 A0 Unused Example of connected memory 512 Mbit product 8 Mwords 16 bits 4 banks column 10 bits product 1 Notes 1 L H is a bit ...

Page 340: ... byte continuous data from the SDRAM that is connected to a 32 bit data bus This access is called the burst read with the burst number 4 Table 9 17 shows the relationship between the access size and the number of bursts Note For details see section 24 LCD Controller LCDC Table 9 17 Relationship between Access Size and Number of Bursts Bus Width Access Size Number of Bursts 16 bits 8 bits 1 16 bits...

Page 341: ... in which wait cycles are inserted The number of cycles from the Tr cycle where the ACTV command is output to the Tc1 cycle where the READ command is output can be specified using the WTRCD1 and WTRCD0 bits in CS3WCR If the WTRCD1 and WTRCD0 bits specify one cycles or more a Trw cycle where the NOT command is issued is inserted between the Tr cycle and Tc1 cycle The number of cycles from the Tc1 c...

Page 342: ...IO A25 to A0 CSn RD WR RASL RASU DQMxx D31 to D0 BS Tap DACKn 2 Tr Tc2 Tc3 Tc1 Td4 Tde Td2 Td3 Td1 A12 A11 1 CASL CASU Notes 1 Address pin to be connected to pin A10 of SDRAM 2 The waveform for DACKn is when active low is specified Figure 9 18 Burst Read Basic Timing CAS Latency 1 Auto Pre Charge ...

Page 343: ...4 Tde Td2 Td3 Td1 Trw Tw CKIO A25 to A0 CSn RD WR RASL RASU DQMxx D31 to D0 BS DACKn 2 A12 A11 1 CASL CASU Notes 1 Address pin to be connected to pin A10 of SDRAM 2 The waveform for DACKn is when active low is specified Figure 9 19 Burst Read Wait Specification Timing CAS Latency 2 WTRCD 1 0 1 Cycle Auto Pre Charge ...

Page 344: ...to the burst read with the burst length 1 only the required data is output A read access that ends in one cycle is called single read Figure 9 20 shows the single read basic timing Tap Tr Tc1 Tde Td1 CKIO A25 to A0 CSn RD WR RASL RASU DQMxx D31 to D0 BS DACKn 2 A12 A11 1 CASL CASU Notes 1 Address pin to be connected to pin A10 of SDRAM 2 The waveform for DACKn is when active low is specified Figur...

Page 345: ...t for burst writes In burst write an ACTV command is output in the Tr cycle the WRIT command is issued in the Tc1 Tc2 and Tc3 cycles and the WRITA command is issued to execute an auto precharge in the Tc4 cycle In the write cycle the write data is output simultaneously with the write command After the write command with the auto precharge is output the Trw1 cycle that waits for the auto precharge ...

Page 346: ... 0050 Tc4 Tap Tr Tc2 Tc3 Tc1 Trwl CKIO A25 to A0 CSn RD WR RASL RASU DQMxx D31 to D0 BS DACKn 2 A12 A11 1 CASL CASU Notes 1 Address pin to be connected to pin A10 of SDRAM 2 The waveform for DACKn is when active low is specified Figure 9 21 Basic Timing for Burst Write Auto Pre Charge ...

Page 347: ...ite or burst write with burst length 1 is set in SDRAM only the required data is output The write access that ends in one cycle is called single write Figure 9 22 shows the single write basic timing Tap Tr Tc1 Trwl CKIO A25 to A0 CSn RD WR RASL RASU DQMxx D31 to D0 BS DACKn 2 A12 A11 1 CASL CASU Notes 1 Address pin to be connected to pin A10 of SDRAM 2 The waveform for DACKn is when active low is ...

Page 348: ...erformed after the access request is issued The number of cycles between issuance of the PRE command and the ACTV command is determined by the WTRP1 and WTPR0 bits in CS3WCR In a write when an auto precharge is performed a command cannot be issued to the same bank for a period of Trwl Tap cycles after issuance of the WRITA command When bank active mode is used READ or WRIT commands can be issued s...

Page 349: ...of the cycle in figure 9 24 or 9 27 An access to a different area during this time has no effect If there is an access to a different row address in the bank active state after this is detected the bus cycle in figure 9 24 or 9 27 is executed instead of that in figure 9 25 or 9 28 In bank active mode too all banks become inactive after a refresh cycle or after the bus is released as the result of ...

Page 350: ...op Td4 Tde Td2 Td3 Td1 CKIO A25 to A0 CS3 RD WR RASL RASU DQMxx D31 to D0 BS DACKn 2 A12 A11 1 CASL CASU Notes 1 Address pin to be connected to pin A10 of SDRAM 2 The waveform for DACKn is when active low is specified Figure 9 24 Burst Read Timing Bank Active Same Row Addresses in the Same Bank CAS Latency 1 ...

Page 351: ...Td4 Td2 Td3 Td1 Tde Tr CKIO A25 to A0 CS3 RD WR RASL RASU DQMxx D31 to D0 BS DACKn 2 A12 A11 1 CASL CASU Notes 1 Address pin to be connected to pin A10 of SDRAM 2 The waveform for DACKn is when active low is specified Figure 9 25 Burst Read Timing Bank Active Different Row Addresses in the Same Bank CAS Latency 1 ...

Page 352: ...EJ09B0313 0050 Tr Tc1 CKIO A25 to A0 CS3 RD WR RASL RASU DQMxx D31 to D0 BS DACKn 2 A12 A11 1 CASL CASU Notes 1 Address pin to be connected to pin A10 of SDRAM 2 The waveform for DACKn is when active low is specified Figure 9 26 Single Write Timing Bank Active Different Bank ...

Page 353: ...050 Tnop Tc1 CKIO A25 to A0 CS3 RD WR RASL RASU DQMxx D31 to D0 BS DACKn 2 A12 A11 1 CASL CASU Notes 1 Address pin to be connected to pin A10 of SDRAM 2 The waveform for DACKn is when active low is specified Figure 9 27 Single Write Timing Bank Active Same Row Addresses in the Same Bank ...

Page 354: ...pw Tp Tc1 Tr CKIO A25 to A0 CS3 RD WR RASL RASU DQMxx D31 to D0 BS DACKn 2 A12 A11 1 CASL CASU Notes 1 Address pin to be connected to pin A10 of SDRAM 2 The waveform for DACKn is when active low is specified Figure 9 28 Single Write Timing Bank Active Different Row Addresses in the Same Bank ...

Page 355: ...When the clock is selected by bits CKS2 to CKS0 RTCNT starts counting up from the value at that time The RTCNT value is constantly compared with the RTCOR value and if the two values are the same a refresh request is generated and an auto refresh is performed for the number of times specified by the RRC2 to RRC0 At the same time RTCNT is cleared to zero and the count up is restarted Figure 9 29 sh...

Page 356: ...8 REJ09B0313 0050 Tpw Tp Trr Trc Trc Trc Hi z CKIO A25 to A0 CSn RD WR RASL RASU DQMxx D31 to D0 BS DACKn 2 A12 A11 1 CASL CASU Notes 1 Address pin to be connected to pin A10 of SDRAM 2 The waveform for DACKn is when active low is specified Figure 9 29 Auto Refresh Timing ...

Page 357: ...y and auto refreshing is performed at the correct intervals When self refreshing is activated from the state in which auto refreshing is set or when exiting standby mode other than through a power on reset auto refreshing is restarted if the RFSH bit is set to 1 and the RMODE bit is cleared to 0 when self refresh mode is cleared If the transition from clearing of self refresh mode to the start of ...

Page 358: ...REJ09B0313 0050 Tpw Tp Trr Trc Trc Hi z Trc CKIO CKE A25 to A0 CSn RD WR RASL RASU DQMxx D31 to D0 BS DACKn 2 A12 A11 1 CASL CASU Notes 1 Address pin to be connected to pin A10 of SDRAM 2 The waveform for DACKn is when active low is specified Figure 9 30 Self Refresh Timing ...

Page 359: ...ction 25 Pin Function Controller PFC This LSI continues to assert REFOUT low level until the bus is acquired On receiving the asserted REFOUT signal the external device must negate the BREQ signal and return the bus If the external bus does not return the bus for a period longer than the specified refresh interval refresh cannot be executed and the SDRAM contents may be lost If a new refresh reque...

Page 360: ...s fetched at the rising edge of CKIO which is half a cycle faster than the normal timing This timing allows the hold time of commands addresses write data and read data to be extended If SDRAM is operated at a high frequency with the SLOW bit set to 1 the setup time of commands addresses write data and read data are not guaranteed Take the operating frequency and timing design into consideration w...

Page 361: ... access cycle However please note that if an access occurs in power down mode a cycle of overhead occurs because a cycle is needed to assert the CKE in order to cancel the power down mode Figure 9 32 shows the access timing in power down mode Tnop Power down Tr Tc1 Td1 Tde Tap Power down CKIO CKE A25 to A0 CSn RD WR RASL RASU DQMxx D31 to D0 BS DACKn 2 A12 A11 1 CASL CASU Notes 1 Address pin to be...

Page 362: ...ming a write to address H FFFC4000 X for area 2 SDRAM and to address H FFFC5000 X for area 3 SDRAM In this operation the data is ignored but the mode write is performed as a byte size access To set burst read single write CAS latency 2 to 3 wrap type sequential and burst length 1 supported by the LSI arbitrary data is written in a byte size access to the addresses shown in table 9 18 In this time ...

Page 363: ...h command is then issued 8 times An MRS command mode register write command is finally issued Idle cycles of which number is specified by the WTRP1 and WTRP0 bits in CS3WCR are inserted between the PALL and the first REF Idle cycles of which number is specified by the WTRC1 and WTRC0 bits in CS3WCR are inserted between REF and REF and between the 8th REF and MRS Idle cycles of which number is one ...

Page 364: ...rr Trc Trc Tmw Hi Z Tnop Trc Trr Trc REF REF MRS PALL CKIO A25 to A0 CSn RD WR RASL RASU DQMxx D31 to D0 BS DACKn 2 A12 A11 1 CASL CASU Notes 1 Address pin to be connected to pin A10 of SDRAM 2 The waveform for DACKn is when active low is specified Figure 9 33 SDRAM Mode Write Timing Based on JEDEC ...

Page 365: ...s issued according to the conditions specified in table below For example if data H 0YYYYYYY is written to address H FFFC5XX0 in longword the commands are issued to the CS3 space in the following sequence PALL REF 8 MRS EMRS In this case the MRS and EMRS issue addresses are H 0000XX0 and H YYYYYYY respectively If data H 1YYYYYYY is written to address H FFFC5XX0 in longword the commands are issued ...

Page 366: ... Tp Trr A12 A11 3 BA1 1 BA0 2 CASL CASU Notes 1 Address pin to be connected to pin BA1 of SDRAM 2 Address pin to be connected to pin BA0 of SDRAM 3 Address pin to be connected to pin A10 of SDRAM 4 The waveform for DACKn is when active low is specified Trc Trc Tmw Hi Z Tnop Trc Trr Trc REF REF MRS Temw Tnop EMRS PALL Figure 9 34 EMRS Command Issue Timing ...

Page 367: ...reas If the RMODE bit in the SDCR is set to 1 while the DEEP and RFSH bits in the SDCR are set to 1 the low power SDRAM enters the deep power down mode If the RMODE bit is cleared to 0 the CKE signal is pulled high to cancel the deep power down mode Before executing an access after returning from the deep power down mode the power up sequence must be re executed Tpw Tp Tdpd Trc Hi Z Trc Trc Trc Tr...

Page 368: ...ted For the 2nd and subsequent access cycles the number of wait cycles specified by the W1 to W0 bits in CSnWCR is inserted In the access to the burst ROM clocked asynchronous the BS signal is asserted only to the first access cycle An external wait input is valid only to the first access cycle In the single access or write access that does not perform the burst operation in the burst ROM clocked ...

Page 369: ...WCR are 10 the number of bursts and access count depend on the access start address At address H xxx0 or H xxx8 4 4 burst access is performed At address H xxx4 or H xxxC 2 4 2 burst access is performed CKIO A25 to A0 RD D31 to D0 DACKn Note The waveform for DACKn is when active low is specified WAIT CSn T1 Tw Tw TB2 Twb TB2 Twb TB2 Twb T2 RD WR BS Figure 9 36 Burst ROM Access Timing Clocked Asynch...

Page 370: ...tion SRAM interface the byte selection signal is output from the WEn pin which is different from that for the normal space interface The basic access timing is shown in figure 9 37 In write access data is written to the memory according to the timing of the byte selection pin WEn For details please refer to the Data Sheet for the corresponding memory If the BAS bit in CSnWCR is set to 1 the WEn pi...

Page 371: ...06 Page 341 of 1588 REJ09B0313 0050 CKIO A25 to A0 CSn WEn RD WR RD RD D31 to D0 D31 to D0 RD WR BS DACKn Read Write Note The waveform for DACKn is when active low is specified T1 T2 High Figure 9 37 Basic Access Timing for SRAM with Byte Selection BAS 0 ...

Page 372: ...06 Page 342 of 1588 REJ09B0313 0050 T1 T2 High CKIO A25 to A0 CSn WEn RD WR RD RD D31 to D0 D31 to D0 RD WR BS DACKn Read Write Note The waveform for DACKn is when active low is specified Figure 9 38 Basic Access Timing for SRAM with Byte Selection BAS 1 ...

Page 373: ...588 REJ09B0313 0050 T2 Tf Th T1 Tw High CKIO A25 to A0 CSn WEn RD WR RD RD D31 to D0 D31 to D0 RD WR BS DACKn Read Write Note The waveform for DACKn is when active low is specified Figure 9 39 Wait Timing for SRAM with Byte Selection BAS 1 SW 1 0 01 WR 3 0 0001 HW 1 0 01 ...

Page 374: ...1 D16 WE3 WE2 D15 D0 WE1 WE0 This LSI A15 A0 CS OE WE I O15 I O0 UB LB 64K 16 bit SRAM Figure 9 40 Example of Connection with 32 Bit Data Width SRAM with Byte Selection This LSI A16 A1 CSn RD RD WR D15 D0 WE1 WE0 A15 A0 CS OE WE I O 15 I O 0 UB LB 64K 16 bit SRAM Figure 9 41 Example of Connection with 16 Bit Data Width SRAM with Byte Selection ...

Page 375: ... to 1 and cleared to 0 respectively the upper 32 Mbytes of area 5 are used for IC memory card interface and the lower 32 Mbytes are used for I O card interface When the PCMCIA interface is used the bus size must be specified as 8 bits or 16 bits using the bits BSZ 1 0 in CS5BCR or CS6BCR Figure 9 42 shows an example of connection between this LSI and a PCMCIA card To enable hot swapping insertion ...

Page 376: ...SI PC card memory or I O A25 to A0 D7 to D0 CE1 CE2 OE WE PGM IORD IOWR REG A25 to A0 D7 to D0 D15 to D8 RD WR CS5B CE1A CE2A RD WE1 WE WE2 ICIORD WE3 ICIOWR REG Output port WAIT IOIS16 G G DIR G G DIR D15 to D8 WAIT IOIS16 CD1 CD2 Card detector Figure 9 42 Example of PCMCIA Interface Connection ...

Page 377: ...nd hold times for the address pins A25 to A0 card enable signals CE1A CE2A CE1B CE2B and write data D15 to D0 to the RD and WE signals become insufficient To prevent this error this LSI enables the setup times and hold times for areas 5 and 6 to be specified independently using CS5WCR and CS6WCR In the PCMCIA interface as in the normal space interface a software wait or hardware wait using the WAI...

Page 378: ...CMCIA Memory Card Interface TED 3 0 B 0010 PCW 3 0 B 0000 TEH 3 0 B 0001 Hardware Wait 1 A port is used to generate the REG signal that switches between the common memory and attribute memory As shown in the example in figure 9 45 when the total memory space necessary for the common memory and attribute memory is 32 Mbytes or less pin A24 can be used as the REG signal to allocate a 16 Mbyte common...

Page 379: ...ommon memory I O space Area 6 H 16000000 Area 5 H 18000000 Area 6 H 1A000000 For 16 Mbyte capacity A24 is used for REG Area 5 H 14000000 Attribute memory I O space Area 5 H 15000000 Area 5 H 16000000 H 17000000 Area 6 H 18000000 Area 6 H 19000000 Area 6 H 1A000000 H 1B000000 Common memory Attribute memory I O space Common memory Figure 9 45 Example of PCMCIA Space Allocation CS5WCR SA 1 0 B 10 CS6...

Page 380: ...the I O card bus the bus width will be recognized as 8 bits and only 8 bits of data will be accessed during the current cycle of the I O card bus Operation will automatically continue with access to the remaining 8 bits of data The IOIS16 signal is sampled on falling edges of the CKIO in Tpci0 as well as all Tpci0w cycles for which the TED3 to TED0 bits are set to 1 5 cycles or more and the CE2A a...

Page 381: ... 9 46 Basic Access Timing for PCMCIA I O Card Interface Tpci1w CKIO A25 to A0 CE1x RD WR ICIORD D15 to D0 ICIOWR IOIS16 D15 to D0 BS Read Write Tpci2 CE2x Tpci0 Tpci1 Tpci1w Tpci0w Tpci2w Tpci1w Tpci1w WAIT Tpci1w Tpci2 Tpci0 Tpci1 Tpci1w Tpci0w Tpci2w Tpci1w Tpci1w Figure 9 47 Dynamic Bus Size Adjustment Timing for PCMCIA I O Card Interface TED 3 0 B 0010 PCW 3 0 B 0000 TEH 3 0 B 0001 Hardware Wa...

Page 382: ...s size for the MPX I O interface are output to D25 to D0 and D31 to D29 respectively in address cycles For the access sizes of D31 to D29 see the description of CS6WCR for the burst MPX I O in section 9 4 3 5 Burst MPX I O Address pins A25 to A0 are used to output normal addresses In the burst MPX I O interface the bus size is fixed at 32 bits The BSZ1 and BSZ0 bits in CS6BCR must be specified as ...

Page 383: ...2006 Page 353 of 1588 REJ09B0313 0050 Tm1 Tmd1w Tmd1 A D Note The waveform for DACKn is when active low is specified CKIO D31 to D0 A25 to A0 FRAME CS6 RD WR WAIT BS DACKn Figure 9 49 Burst MPX Space Access Timing Single Read No Wait or Software Wait 1 ...

Page 384: ...age 354 of 1588 REJ09B0313 0050 Tm1 Tmd1w Tmd1w Tmd1 A D Note The waveform for DACKn is when active low is specified CKIO D31 to D0 A25 to A0 FRAME CS6 RD WR WAIT BS DACKn Figure 9 50 Burst MPX Space Access Timing Single Write Software Wait 1 Hardware Wait 1 ...

Page 385: ...88 REJ09B0313 0050 Tm1 Tmd1w Tmd1 Tmd2 Tmd3 Tmd4 A D0 D1 D2 D3 Note The waveform for DACKn is when active low is specified CKIO D31 to D0 A25 to A0 FRAME CS6 RD WR WAIT BS DACKn Figure 9 51 Burst MPX Space Access Timing Burst Read No Wait or Software Wait 1 CS6WCR MPXMD 0 ...

Page 386: ...ge 356 of 1588 REJ09B0313 0050 Tm1 Tmd1 Tmd2 Tmd3 Tmd4 A D0 D1 D2 D3 Note The waveform for DACKn is when active low is specified CKIO D31 to D0 A25 to A0 FRAME CS6 RD WR WAIT BS DACKn Figure 9 52 Burst MPX Space Access Timing Burst Write No Wait CS6WCR MPXMD 0 ...

Page 387: ...ength must be specified as 8 If the bus width is 32 bits the burst length must be specified as 4 The burst ROM interface does not support the 8 bit bus width for the burst ROM The burst ROM interface performs burst operations for all read access For example in a longword access over a 16 bit bus valid 16 bit data is read two times and invalid 16 bit data is read six times These invalid data read c...

Page 388: ... read write for the same space 4 Continuous access cycles are read read for different spaces 5 Continuous access cycles are read read for the same space 6 Data output from an external device caused by DMA single address transfer is followed by data output from another device that includes this LSI DMAIWA 0 7 Data output from an external device caused by DMA single address transfer is followed by a...

Page 389: ...e in the case where reading CS1 space followed by reading other CS space the bits IWRRD 2 0 in CS1BCR should be set to B 100 to specify six or more idle cycles This condition is effective only for access cycles other than single address transfer and generates idle cycles after the access is completed 0 to 12 Do not set 0 for the number of idle cycles between memory types which are not allowed to b...

Page 390: ...nship between the clock ratio and the minimum number of internal bus idle cycles 7 Write data wait cycles During write access a write cycle is executed on the external bus only after the write data becomes ready This write data wait period generates idle cycles before the write cycle Note that when the previous cycle is a write cycle and the internal bus idle cycles are shorter than the previous w...

Page 391: ...dle cycle after access Either one of them is effective 1 DMAIW 2 0 setting in CMNCR 2 IWW 2 0 setting in CSnBCR IWRWD 2 0 setting in CSnBCR IWRWS 2 0 setting in CSnBCR IWRRD 2 0 setting in CSnBCR IWRRS 2 0 setting in CSnBCR 3 WTRP 1 0 setting in CSnWCR TRWL 1 0 setting in CSnWCR WTRC 1 0 setting in CSnWCR 4 WM setting in CSnWCR 6 Internal bus idle cycles etc 8 Idle cycles between different memory ...

Page 392: ...dress Write write 0 2 Write read 0 or 2 0 Read write 0 0 Read read 0 2 Notes 1 The write write and read read columns in dual address transfer indicate the cycles in the divided access cycles 2 For the write read cycles in dual address transfer 0 means different channels are activated successively and 2 means when the same channel is activated successively 3 The write read and read write columns in...

Page 393: ...RAM BAS 0 0 0 1 0 1 1 1 5 0 0 0 Byte SRAM BAS 1 1 1 2 1 0 0 1 5 1 1 1 SDRAM 1 1 2 1 0 0 1 1 1 SDRAM low frequency mode 1 5 1 5 2 5 1 5 0 5 1 1 5 1 5 1 5 PCMCIA 0 0 1 0 1 1 1 5 0 0 0 Burst MPX 0 0 1 0 1 1 1 5 0 0 0 Burst ROM synchronous 0 0 1 0 1 1 1 5 0 0 0 Figure 9 55 shows sample estimation of idle cycles between access cycles In the actual operation the idle cycles may become shorter than the e...

Page 394: ...n internal idle cycle is generated due to execution of a loop condition check instruction 4 2 1 The bits for setting the idle cycles between access cycles in CS1BCR and CS2BCR are all set to 0 In CS1WCR and CS2WCR the WM bit is set to 1 external WAIT pin disabled and the HW 1 0 bits are set to 00 CS negation is not extended Iφ Bφ is set to 4 1 and no other processing is done during transfer For bo...

Page 395: ...us width is smaller than the access size for example between bus cycles when longword access is made to a memory with a data bus width of 8 bits 5 16 byte transfer by the DMAC 6 Setting the BLOCK bit in CMNCR to 1 7 16 byte to 128 byte transfer by the LCDC Moreover by using DPRTY bit in CMNCR whether the bus mastership request is received or not can be selected during DMAC burst transfer The LSI h...

Page 396: ... REFOUT signal is kept asserting at low level until the bus mastership is acquired The BREQ signal is negated by asserting the REFOUT signal and the bus mastership is returned from the external device If the bus mastership is not returned for a refreshing period or longer the contents of SDRAM cannot be guaranteed because a refreshing cannot be executed While releasing the bus mastership the SLEEP...

Page 397: ...d cache memory are connected to the CPU bus Internal bus masters other than the CPU and bus state controller are connected to the internal bus Low speed peripheral modules are connected to the peripheral bus Internal memories other than the cache memory are connected bidirectionally to the CPU bus and internal bus Access from the CPU bus to the internal bus is enabled but access from the internal ...

Page 398: ...g to the address is then read and data in the corresponding access of the cache is finally modified Following these operations a write back cycle for the saved 16 byte data is executed In write through mode the cache is first searched If data is detected at the address corresponding to the cache the data is re written to the cache simultaneously with the actual write via the internal bus If data i...

Page 399: ...waiting for the completion of writing to registers For example a case is described here in which the system is transferring to the software standby mode for power savings To make this transition the SLEEP instruction must be performed after setting the STBY bit in the STBCR register to 1 However a dummy read of the STBCR register is required before executing the SLEEP instruction If a dummy read i...

Page 400: ...Section 9 Bus State Controller BSC Rev 0 50 May 18 2006 Page 370 of 1588 REJ09B0313 0050 ...

Page 401: ... 216 transfers 24 bits Address mode Dual address mode and single address mode are supported Transfer requests External request On chip peripheral module request Auto request The following modules can issue on chip peripheral module requests Eight SCIF sources eight IIC3 sources one A D converter source five MTU2 sources two CMT sources two USB sources two FLCTL sources two RCAN TL1 sources four SS...

Page 402: ...nd transfer end signals Active levels for DACK and TEND can be set independently Support of reload functions in DMA transfer information registers DMA transfer using the same information as the current transfer can be repeated automatically without specifying the information again Modifying the reload registers during DMA transfer enables next DMA transfer to be done using different transfer infor...

Page 403: ...quest priority control Start up control Register control Iteration control RDMATCR_n DMATCR_n RSAR_n SAR_n DAR_n RDAR_n CHCR_n DMAOR DMARS0 to DMARS3 RDMATCR DMATCR RSAR SAR RDAR DAR DMA reload transfer count register DMA transfer count register DMA reload source address register DMA source address register DMA reload destination address register DMA destination address register CHCR DMAOR DMARS0 ...

Page 404: ...an external device DMA transfer request DREQ1 I DMA transfer request input from an external device to channel 1 1 DMA transfer request acknowledge DACK1 O DMA transfer request acknowledge output from channel 1 to an external device DMA transfer request DREQ2 I DMA transfer request input from an external device to channel 2 2 DMA transfer request acknowledge DACK2 O DMA transfer request acknowledge...

Page 405: ...16 32 DMA transfer count register_0 DMATCR_0 R W H 00000000 H FFFE1008 16 32 DMA channel control register_0 CHCR_0 R W 1 H 00000000 H FFFE100C 8 16 32 DMA reload source address register_0 RSAR_0 R W H 00000000 H FFFE1100 16 32 DMA reload destination address register_0 RDAR_0 R W H 00000000 H FFFE1104 16 32 0 DMA reload transfer count register_0 RDMATCR_0 R W H 00000000 H FFFE1108 16 32 DMA source ...

Page 406: ... 00000000 H FFFE1120 16 32 DMA reload destination address register_2 RDAR_2 R W H 00000000 H FFFE1124 16 32 2 DMA reload transfer count register_2 RDMATCR_2 R W H 00000000 H FFFE1128 16 32 DMA source address register_3 SAR_3 R W H 00000000 H FFFE1030 16 32 DMA destination address register_3 DAR_3 R W H 00000000 H FFFE1034 16 32 DMA transfer count register_3 DMATCR_3 R W H 00000000 H FFFE1038 16 32...

Page 407: ... 00000000 H FFFE1140 16 32 DMA reload destination address register_4 RDAR_4 R W H 00000000 H FFFE1144 16 32 4 DMA reload transfer count register_4 RDMATCR_4 R W H 00000000 H FFFE1148 16 32 DMA source address register_5 SAR_5 R W H 00000000 H FFFE1050 16 32 DMA destination address register_5 DAR_5 R W H 00000000 H FFFE1054 16 32 DMA transfer count register_5 DMATCR_5 R W H 00000000 H FFFE1058 16 32...

Page 408: ... 00000000 H FFFE1160 16 32 DMA reload destination address register_6 RDAR_6 R W H 00000000 H FFFE1164 16 32 6 DMA reload transfer count register_6 RDMATCR_6 R W H 00000000 H FFFE1168 16 32 DMA source address register_7 SAR_7 R W H 00000000 H FFFE1070 16 32 DMA destination address register_7 DAR_7 R W H 00000000 H FFFE1074 16 32 DMA transfer count register_7 DMATCR_7 R W H 00000000 H FFFE1078 16 32...

Page 409: ... DMAOR only 0 can be written to clear the flags after 1 is read 10 3 1 DMA Source Address Registers SAR The DMA source address registers SAR are 32 bit readable writable registers that specify the source address of a DMA transfer During a DMA transfer these registers indicate the next source address When the data of an external device with DACK is transferred in single address mode SAR is ignored ...

Page 410: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W Bit Initial value R W 10 3 3 DMA Transfer Count Registers DMATCR The DMA transfer count registers DMATCR are 32 bit readable writable registers that specify the number of DMA transfers The transfer count is 1 when the setting is H 00000001 16 777 215 when H 00FFFFFF is set and 16 7...

Page 411: ...R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W Bit Initial value R W Note Only 0 can be written to clear the flag after 1 is read TC RLD SAR RLD DAR DO TL TE MASK HE HIE AM AL DM 1 0 SM 1 0 RS 3 0 DL DS TB TS 1 0 IE TE DE Bit Bit Name Initial Value R W Description 31 TC 0 R W Transfer Count Mode Specifies whether to...

Page 412: ...ATCR 27 to 24 All 0 R Reserved These bits are always read as 0 The write value should always be 0 23 DO 0 R W DMA Overrun Selects whether DREQ is detected by overrun 0 or by overrun 1 This bit is valid only in CHCR_0 to CHCR_3 This bit is reserved in CHCR_4 to CHCR_7 it is always read as 0 and the write value should always be 0 0 Detects DREQ by overrun 0 1 Detects DREQ by overrun 1 22 TL 0 R W Tr...

Page 413: ... 1 0 DMA transfer stops if the TE bit is set 1 DMA transfer does not stop even if the TE bit is set 19 HE 0 R W Half End Flag This bit is set to 1 when the transfer count reaches half of the DMATCR value that was specified before transfer starts If DMA transfer ends because of an NMI interrupt a DMA address error or clearing of the DE bit or the DME bit in DMAOR before the transfer count reaches h...

Page 414: ...fore transfer starts 2 17 AM 0 R W Acknowledge Mode Specifies whether DACK is output in data read cycle or in data write cycle in dual address mode In single address mode DACK is always output regardless of the specification by this bit This bit is valid only in CHCR_0 to CHCR_3 This bit is reserved in CHCR_4 to CHCR_7 it is always read as 0 and the write value should always be 0 0 DACK output in ...

Page 415: ...sfer 10 Destination address is decremented 1 in 8 bit transfer 2 in 16 bit transfer 4 in 32 bit transfer setting prohibited in 16 byte transfer 11 Setting prohibited 13 12 SM 1 0 00 R W Source Address Mode These bits select whether the DMA source address is incremented decremented or left fixed In single address mode SM1 and SM0 bits are ignored when data is transferred from an external device wit...

Page 416: ... 0010 External request single address mode External address space External device with DACK 0011 External request single address mode External device with DACK External address space 0100 Auto request 0101 Setting prohibited 0110 Setting prohibited 0111 Setting prohibited 1000 DMA extension resource selector 1001 RCAN TL10 1010 RCAN TL11 1011 Setting prohibited 1100 Setting prohibited 1101 Setting...

Page 417: ...module or if an auto request is specified the specification by these bits is ignored 00 DREQ detected in low level 01 DREQ detected at falling edge 10 DREQ detected in high level 11 DREQ detected at rising edge 5 TB 0 R W Transfer Bus Mode Specifies the bus mode when DMA transfers data Note that the burst mode must not be selected when TC 0 0 Cycle steal mode 1 Burst mode 4 3 TS 1 0 00 R W Transfe...

Page 418: ...t 1 TE 0 R W Transfer End Flag This bit is set to 1 when DMATCR becomes 0 and DMA transfer ends The TE bit is not set to 1 in the following cases DMA transfer ends due to an NMI interrupt or DMA address error before DMATCR becomes 0 DMA transfer is ended by clearing the DE bit and DME bit in DMA operation register DMAOR To clear the TE bit write 0 after reading TE 1 Even if the DE bit is set to 1 ...

Page 419: ...er request is generated by the devices or peripheral modules after setting the bits DE and DME to 1 If the DREQ signal is detected by low high level in external request mode or in peripheral module request mode the NMIF bit and the AE bit must be 0 if the TEMASK bit is 1 If the TEMASK bit is 0 the TE bit must also be 0 If the DREQ signal is detected by a rising falling edge in external request mod...

Page 420: ...for the next DMA transfer can be preset in RSAR during the current DMA transfer When the SAR reload function is disabled RSAR is ignored To transfer data in word 2 byte longword 4 byte or 16 byte unit specify the address with 2 byte 4 byte or16 byte address boundary respectively 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R ...

Page 421: ... value for the next DMA transfer can be preset in RDAR during the current DMA transfer When the DAR reload function is disabled RDAR is ignored To transfer data in word 2 byte longword 4 byte or 16 byte unit specify the address with 2 byte 4 byte or16 byte address boundary respectively 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 422: ...ransfer When the SAR DAR reload function is disabled RDMATCR is ignored The upper eight bits of RDMATCR are always read as 0 and the write value should always be 0 As in DMATCR the transfer count is 1 when the setting is H 00000001 16 777 215 when H 00FFFFFF is set and 16 777 216 the maximum when H 00000000 is set To transfer data in 16 bytes one 16 byte transfer 128 bits counts one 31 30 29 28 27...

Page 423: ... Initial value R W CMS 1 0 PR 1 0 AE NMIF DME Bit Bit Name Initial Value R W Description 15 14 All 0 R Reserved These bits are always read as 0 The write value should always be 0 13 12 CMS 1 0 00 R W Cycle Steal Mode Select These bits select either normal mode or intermittent mode in cycle steal mode It is necessary that the bus modes of all channels be set to cycle steal mode to make the intermit...

Page 424: ...ess error has occurred by the DMAC When this bit is set even if the DE bit in CHCR and the DME bit in DMAOR are set to 1 DMA transfer is not enabled This bit can only be cleared by writing 0 after reading 1 0 No DMAC address error 1 DMAC address error occurred Clearing condition Writing 0 after reading AE 1 1 NMIF 0 R W NMI Flag Indicates that an NMI interrupt occurred When this bit is set even if...

Page 425: ...specified as CH0 CH4 CH1 CH5 CH2 CH6 CH3 CH7 If fixed mode 1 is specified the channel priority is specified as CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 If the round robin mode is specified the transfer end channel is reset Table 10 3 show the priority change in each mode modes 0 to 2 specified by the priority mode bits In each priority mode the channel priority to accept the next transfer request may chang...

Page 426: ...fixed mode 1 Any channel 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 Mode 1 fixed mode 2 Any channel 0 1 CH0 CH4 CH1 CH5 CH2 CH6 CH3 CH7 CH0 1 1 CH1 CH2 CH3 CH0 CH4 CH5 CH6 CH7 CH1 1 1 CH2 CH3 CH0 CH1 CH4 CH5 CH6 CH7 CH2 1 1 CH3 CH0 CH1 CH2 CH4 CH5 CH6 CH7 CH3 1 1 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH4 1 1 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH5 1 1 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH6 1 1 CH0 CH1 CH2 CH3 CH4 CH5...

Page 427: ...be specified by these registers for these two sources can be specified using the RS3 to RS0 bits in the DMA channel control register CHCR DMARS0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W CH1 MID 5 0 CH1 RID 1 0 CH0 RID 1 0 CH0 MID 5 0 DMARS1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 ...

Page 428: ... 001010 B 11 SSL_3 H 2F B 001011 B 11 H 51 B 01 Receive SSU_0 H 52 B 010100 B 10 Transmit H 55 B 01 Receive SSU_1 H 56 B 010101 B 10 Transmit H 61 B 01 Transmit IIC3_0 H 62 B 011000 B 10 Receive H 65 B 01 Transmit IIC3_1 H 66 B 011001 B 10 Receive H 69 B 01 Transmit IIC3_2 H 6A B 011010 B 10 Receive H 6D B 01 Transmit IIC3_3 H 6E B 011011 B 10 Receive H 81 B 10 Receive SCIF_0 H 82 B 100000 B 01 Tr...

Page 429: ... E3 B 111000 B 11 MTU2_1 H E7 B 111001 B 11 MTU2_2 H EB B 111010 B 11 MTU2_3 H EF B 111011 B 11 MTU2_4 H F3 B 111100 B 11 CMT_0 H FB B 111110 B 11 CMT_1 H FF B 111111 B 11 When MID or RID other than the values listed in table 10 4 is set the operation of this LSI is not guaranteed The transfer request from DMARS is valid only when the resource select bits RS3 to RS0 in CHCR0 to CHCR7 have been set...

Page 430: ...ransfer request comes and transfer is enabled the DMAC transfers one transfer unit of data depending on the settings of the TS1 and TS0 bits For an auto request the transfer begins automatically when the DE bit and DME bit are set to 1 The DMATCR value will be decremented by 1 for each transfer The actual transfer flows vary by address mode and bus mode 3 When half of the specified transfer count ...

Page 431: ...CR DMATCR For a request from an on chip peripheral module the transfer acknowledge signal is sent to the module NMIF 1 or AE 1 or DE 0 or DME 0 Transfer end Bus mode transfer request mode DREQ detection system DMATCR 1 2 HE 1 HEI interrupt request when HE 1 When the TC bit in CHCR is 0 or for a request from an on chip peripheral module the transfer acknowledge signal is sent to the module NMIF 1 o...

Page 432: ...he DMAC to automatically generate a transfer request signal internally When the DE bits in CHCR_0 to CHCR_7 and the DME bit in DMAOR are set to 1 the transfer begins so long as the TE bits in CHCR_0 to CHCR_7 and the AE and NMIF bits in DMAOR are 0 2 External Request Mode In this mode a transfer is performed at the request signals DREQ0 to DREQ3 of an external device Choose one of the modes shown ...

Page 433: ...Bit Detection of External Request 0 Low level detection 0 1 Falling edge detection 0 High level detection 1 1 Rising edge detection When DREQ is accepted the DREQ pin enters the request accept disabled state non sensitive period After issuing acknowledge DACK signal for the accepted DREQ the DREQ pin again enters the request accept enabled state When DREQ is used by level detection there are follo...

Page 434: ...ting On Chip Peripheral Module Request Modes with RS3 to RS0 Bits CHCR DMARS RS 3 0 MID RID DMA Transfer Request Source DMA Transfer Request Signal Transfer Source Transfer Destination Bus Mode 1001 Any Any RCAN TL10 reception DM0 reception end RCAN0 MB0 Any 1010 Any Any RCAN TL11 reception DM0 reception end RCAN1 MB0 Any Cycle steal 1000 USB_DMA0 receive FIFO full D0FIFO Any 000000 11 USB USB_DMA...

Page 435: ...ansmission data empty Any ICDRT0 011000 10 IIC3_0 reception RXI0 reception data full ICDRR0 Any 01 IIC3_1 transmission TXI1 transmission data empty Any ICDRT1 011001 10 IIC3_1 reception RXI1 reception data full ICDRR1 Any 01 IIC3_2 transmission TXI2 transmission data empty Any ICDRT2 011010 10 IIC3_2 reception RXI2 reception data full ICDRR2 Any 01 IIC3_3 transmission TXI3 transmission data empty ...

Page 436: ...verter ADI A D conversion end ADDR Any FLCTL data part transmission Transmission FIFO data empty Any FLDTFIFO 101110 11 FLCTL data part reception Reception FIFO data full FLDTFIFO Any FLCTL control code part transmission Transmission FIFO data empty Any FLECFIFO 101111 11 FLCTL control code part reception Reception FIFO data full FLECFIFO Any 111000 11 MTU2_0 TGI0A input capture compare match Any ...

Page 437: ...3 CH7 These are selected by the PR1 and PR0 bits in the DMA operation register DMAOR 2 Round Robin Mode Each time one unit of word byte longword or 16 bytes is transferred on one channel the priority order is rotated The channel on which the transfer was just finished is rotated to the lowest of the priority order among the four round robin channels channels 0 to 4 The priority of the channels oth...

Page 438: ...mong the round robin channels CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH1 CH2 CH3 CH0 CH4 CH5 CH6 CH7 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH2 CH3 CH0 CH1 CH4 CH5 CH6 CH7 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH3 CH0 CH1 CH2 CH4 CH5 CH6 CH7 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH3 CH0 CH1 CH2 CH4 CH5 CH6 CH7 1 When channel 0 transfers Initial priority order Initial priority order Initial p...

Page 439: ...hannels 5 At this point channel 1 has a higher priority than channel 3 so the channel 1 transfer begins channel 3 waits for transfer 6 When the channel 1 transfer ends channel 1 is given the lowest priority among the round robin channels 7 The channel 3 transfer begins 8 When the channel 3 transfer ends channels 3 and 2 are lowered in priority so that channel 3 is given the lowest priority among t...

Page 440: ...ble 10 9 Supported DMA Transfers Transfer Destination Transfer Source External Device with DACK External Memory Memory Mapped External Device On Chip Peripheral Module On Chip Memory External device with DACK Not available Dual single Dual single Not available Not available External memory Dual single Dual Dual Dual Dual Memory mapped external device Dual single Dual Dual Dual Dual On chip periphe...

Page 441: ...t data is written to the other external memory in a data write cycle Data buffer Address bus Data bus Address bus Data bus Memory Transfer source module Transfer destination module Memory Transfer source module Transfer destination module SAR DAR Data buffer SAR DAR The SAR value is an address data is read from the transfer source module and the data is temporarily stored in the DMAC First bus cyc...

Page 442: ...0 D31 to D0 DACKn Active low CSn WEn RD Data read cycle Data write cycle 1st cycle 2nd cycle Transfer source address Transfer destination address Note In transfer between external memories with DACK output in the read cycle DACK output timing is the same as that of CSn Figure 10 6 Example of DMA Transfer Timing in Dual Mode Transfer Source Normal Memory Transfer Destination Normal Memory ...

Page 443: ...the transfer For example in the case of transfer between external memory and an external device with DACK shown in figure 10 7 when the external device outputs data to the data bus that data is written to the external memory in the same bus cycle External address bus External data bus DMAC External memory DACK DREQ Data flow from memory to device Data flow from device to memory External device wit...

Page 444: ...DACKn CSn WEn CK A25 to A0 D31 to D0 DACKn CSn RD Figure 10 8 Example of DMA Transfer Timing in Single Address Mode 2 Bus Modes There are two bus modes cycle steal and burst Select the mode by the TB bits in the channel control registers CHCR a Cycle Steal Mode Normal mode In normal mode of cycle steal the bus mastership is given to another bus master after a one transfer unit byte word longword o...

Page 445: ... other bus master These operations are repeated until the transfer end condition is satisfied It is thus possible to make lower the ratio of bus occupation by DMA transfer than the normal mode of cycle steal When DMAC obtains again the bus mastership DMA transfer may be postponed in case of entry updating due to cache miss The cycle steal intermittent mode can be used for any transfer section tran...

Page 446: ...ess DREQ Low Level Detection 3 Relationship between Request Modes and Bus Modes by DMA Transfer Category Table 10 10 shows the relationship between request modes and bus modes by DMA transfer category Table 10 10 Relationship of Request Modes and Bus Modes by DMA Transfer Category Address Mode Transfer Category Request Mode Bus Mode Transfer Size Bits Usable Channels Dual External device with DACK...

Page 447: ...ernal device External B C 8 16 32 128 0 to 3 Legend B Burst C Cycle steal Notes 1 External requests auto requests and on chip peripheral module requests are all available However in the case of internal module request along with the exception of MTU2 and CMT as the transfer request source the requesting module must be designated as the transfer source or the transfer destination 2 Access size perm...

Page 448: ...order channel 0 channel 1 channel 0 channel 1 etc That is the CPU cycle after the data transfer in cycle steal mode is replaced with a burst mode transfer cycle priority execution of burst mode cycle An example of this is shown in figure 10 12 When multiple channels are in burst mode data transfer on the channel that has the highest priority is given precedence When DMA transfer is being performed...

Page 449: ... show the DREQ input sampling timings in each bus mode CKIO DREQ DACK Bus cycle Rising Active high 1st acceptance 2nd acceptance CPU CPU CPU Acceptance start DMAC Non sensitive period Figure 10 13 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection CKIO DREQ Overrun 0 at high level DACK Active high Bus cycle 1st acceptance CPU CPU CPU DMAC CKIO DREQ Overrun 1 at high level DACK Acti...

Page 450: ...t Detection in Burst Mode Edge Detection CKIO DREQ Overrun 0 at high level DACK Active high Bus cycle 2nd acceptance CPU CPU DMAC CKIO DREQ Overrun 1 at high level DACK Active high Bus cycle 1st acceptance 2nd acceptance Non sensitive period Non sensitive period CPU CPU DMAC 3rd acceptance DMAC Acceptance start Acceptance start Acceptance start 1st acceptance Figure 10 16 Example of DREQ Input Det...

Page 451: ...e bus cycles when 16 byte transfer is performed for an 8 bit 16 bit or 32 bit external device when longword access is performed for an 8 bit or 16 bit external device or when word access is performed for an 8 bit external device When a setting is made so that the DMA transfer size is divided into multiple bus cycles and the CS signal is negated between bus cycles note that DACK and TEND are divide...

Page 452: ...n WAIT CS T1 T2 Taw T1 T2 DACKn Active low TEND Active low Note TEND is asserted for the last unit of DMA transfer If a transfer unit is divided into multiple bus cycles and the CS is negated between the bus cycles TEND is also divided Figure 10 18 BSC Normal Memory Access No Wait Idle Cycle 1 Longword Access to 16 Bit Device ...

Page 453: ...ble in combination with synchronous operation Buffer operation settable for channels 0 3 and 4 Phase counting mode settable independently for each of channels 1 and 2 Cascade connection operation Fast access via internal 16 bit bus 28 interrupt sources Automatic transfer of register data A D converter start trigger can be generated Module standby mode can be settable A total of six phase waveform ...

Page 454: ...B_0 TGRE_0 TGRA_1 TGRB_1 TGRA_2 TGRB_2 TGRA_3 TGRB_3 TGRA_4 TGRB_4 General registers buffer registers TGRC_0 TGRD_0 TGRF_0 TGRC_3 TGRD_3 TGRC_4 TGRD_4 I O pins TIOC0A TIOC0B TIOC0C TIOC0D TIOC1A TIOC1B TIOC2A TIOC2B TIOC3A TIOC3B TIOC3C TIOC3D TIOC4A TIOC4B TIOC4C TIOC4D Counter clear function TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture ...

Page 455: ...ture TGRA_4 compare match or input capture TCNT_4 underflow trough in complementary PWM mode Interrupt sources 7 sources Compare match or input capture 0A Compare match or input capture 0B Compare match or input capture 0C Compare match or input capture 0D Compare match 0E Compare match 0F Overflow 4 sources Compare match or input capture 1A Compare match or input capture 1B Overflow Underflow 4 s...

Page 456: ...hannel 2 Channel 3 Channel 4 A D converter start request delaying function A D converter start request at a match between TADCORA_4 and TCNT_4 A D converter start request at a match between TADCORB_4 and TCNT_4 Interrupt skipping function Skips TGRA_3 compare match interrupts Skips TCIV_4 interrupts Legend Available Not available ...

Page 457: ...Timer cycle data register TCBR Timer cycle buffer register TDDR Timer dead time data register TGRA Timer general register A TGRB Timer general register B TGRC Timer general register C TGRD Timer general register D TGRE Timer general register E TGRF Timer general register F Clock input Internal clock Pφ 1 Pφ 4 Pφ 16 Pφ 64 Pφ 256 Pφ 1024 External clock TCLKA TCLKB TCLKC TCLKD Input output pins Chann...

Page 458: ...pin 1 TIOC1A I O TGRA_1 input capture input output compare output PWM output pin TIOC1B I O TGRB_1 input capture input output compare output PWM output pin 2 TIOC2A I O TGRA_2 input capture input output compare output PWM output pin TIOC2B I O TGRB_2 input capture input output compare output PWM output pin 3 TIOC3A I O TGRA_3 input capture input output compare output PWM output pin TIOC3B I O TGRB...

Page 459: ...errupt enable register_0 TIER_0 R W H 00 H FFFE4304 8 Timer status register_0 TSR_0 R W H C0 H FFFE4305 8 Timer counter_0 TCNT_0 R W H 0000 H FFFE4306 16 Timer general register A_0 TGRA_0 R W H FFFF H FFFE4308 16 Timer general register B_0 TGRB_0 R W H FFFF H FFFE430A 16 Timer general register C_0 TGRC_0 R W H FFFF H FFFE430C 16 Timer general register D_0 TGRD_0 R W H FFFF H FFFE430E 16 Timer gene...

Page 460: ...6 2 Timer general register B_2 TGRB_2 R W H FFFF H FFFE400A 16 Timer control register_3 TCR_3 R W H 00 H FFFE4200 8 Timer mode register_3 TMDR_3 R W H 00 H FFFE4202 8 Timer I O control register H_3 TIORH_3 R W H 00 H FFFE4204 8 Timer I O control register L_3 TIORL_3 R W H 00 H FFFE4205 8 Timer interrupt enable register_3 TIER_3 R W H 00 H FFFE4208 8 Timer status register_3 TSR_3 R W H C0 H FFFE422...

Page 461: ...TGRD_4 R W H FFFF H FFFE422A 16 Timer buffer operation transfer mode register_4 TBTM_4 R W H 00 H FFFE4239 8 Timer A D converter start request control register TADCR R W H 0000 H FFFE4240 16 Timer A D converter start request cycle set register A_4 TADCORA_4 R W H FFFF H FFFE4244 16 Timer A D converter start request cycle set register B_4 TADCORB_4 R W H FFFF H FFFE4246 16 Timer A D converter start...

Page 462: ...r TCDR R W H FFFF H FFFE4214 16 Timer dead time data register TDDR R W H FFFF H FFFE4216 16 Timer subcounter TCNTS R H 0000 H FFFE4220 16 Timer cycle buffer register TCBR R W H FFFF H FFFE4222 16 Timer interrupt skipping set register TITCR R W H 00 H FFFE4230 8 Timer interrupt skipping counter TITCNT R H 00 H FFFE4231 8 Timer buffer transfer set register TBTER R W H 00 H FFFE4232 8 Timer dead time...

Page 463: ...d 11 5 for details 4 3 CKEG 1 0 00 R W Clock Edge 0 and 1 These bits select the input clock edge When the input clock is counted using both edges the input clock period is halved e g Pφ 4 both edges Pφ 2 rising edge If phase counting mode is used on channels 1 and 2 this setting is ignored and the phase counting mode setting has priority Internal clock edge selection is valid when the input clock ...

Page 464: ...or another channel performing synchronous clearing synchronous operation 1 Notes 1 Synchronous operation is set by setting the SYNC bit in TSYR to 1 2 When TGRC or TGRD is used as a buffer register TCNT is not cleared because the buffer register setting has priority and compare match input capture does not occur Table 11 5 CCLR0 to CCLR2 Channels 1 and 2 Channel Bit 7 Reserved 2 Bit 6 CCLR1 Bit 5 ...

Page 465: ...rnal clock counts on TCLKB pin input 1 0 External clock counts on TCLKC pin input 1 External clock counts on TCLKD pin input Table 11 7 TPSC0 to TPSC2 Channel 1 Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 1 0 0 0 Internal clock counts on Pφ 1 1 Internal clock counts on Pφ 4 1 0 Internal clock counts on Pφ 16 1 Internal clock counts on Pφ 64 1 0 0 External clock counts on TCLKA pin inpu...

Page 466: ...ernal clock counts on TCLKB pin input 1 0 External clock counts on TCLKC pin input 1 Internal clock counts on Pφ 1024 Note This setting is ignored when channel 2 is in phase counting mode Table 11 9 TPSC0 to TPSC2 Channels 3 and 4 Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 3 4 0 0 0 Internal clock counts on Pφ 1 1 Internal clock counts on Pφ 4 1 0 Internal clock counts on Pφ 16 1 Inte...

Page 467: ... 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R R W R W R W R W R W R W R W BFE BFB BFA MD 3 0 Bit Bit Name Initial Value R W Description 7 0 R Reserved This bit is always read as 0 The write value should always be 0 6 BFE 0 R W Buffer Operation E Specifies whether TGRE_0 and TGRF_0 are to operate in the normal way or to be used together for buffer operation TGRF compare match is generated when TGRF is used as t...

Page 468: ...0 and cannot be modified 0 TGRB and TGRD operate normally 1 TGRB and TGRD used together for buffer operation 4 BFA 0 R W Buffer Operation A Specifies whether TGRA is to operate in the normal way or TGRA and TGRC are to be used together for buffer operation When TGRC is used as a buffer register TGRC input capture output compare is not generated in a mode other than complementary PWM TGRC compare m...

Page 469: ...plementary PWM mode 1 transmit at crest 3 1 0 Complementary PWM mode 2 transmit at trough 3 1 Complementary PWM mode 2 transmit at crest and trough 3 Legend X Don t care Notes 1 PWM mode 2 cannot be set for channels 3 and 4 2 Phase counting mode cannot be set for channels 0 3 and 4 3 Reset synchronous PWM mode complementary PWM mode can only be set for channel 3 When channel 3 is set to reset sync...

Page 470: ... output at the point at which the counter is cleared to 0 is specified When TGRC or TGRD is designated for buffer operation this setting is invalid and the register operates as a buffer register TIORH_0 TIOR_1 TIOR_2 TIORH_3 TIORH_4 Bit Initial value R W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W IOB 3 0 IOA 3 0 Bit Bit Name Initial Value R W Description 7 to 4 IOB 3 0 0000 R ...

Page 471: ...R W R W R W R W R W IOD 3 0 IOC 3 0 Bit Bit Name Initial Value R W Description 7 to 4 IOD 3 0 0000 R W I O Control D0 to D3 Specify the function of TGRD See the following tables TIORL_0 Table 11 12 TIORL_3 Table 11 16 TIORL_4 Table 11 18 3 to 0 IOC 3 0 0000 R W I O Control C0 to C3 Specify the function of TGRC See the following tables TIORL_0 Table 11 20 TIORL_3 Table 11 24 TIORL_4 Table 11 26 ...

Page 472: ...1 Initial output is 0 Toggle output at compare match 0 0 Output retained 1 Initial output is 1 0 output at compare match 0 Initial output is 1 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 Toggle output at compare match 0 Input capture at rising edge 0 1 Input capture at falling edge 0 1 X Input capture at both edges 1 1 X X Input capture register Capture input sour...

Page 473: ... 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 0 0 0 Input capture at rising edge 1 Input capture at falling edge 1 X Input capture at both edges 1 X X Input capture register 2 Capture input source is channel 1 count clock Input capture at TCNT_1 count up count down Lege...

Page 474: ...output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 0 0 0 Input capture at rising edge 1 Input capture at falling edge 1 X Input capture at both edges 1 X X Input capture register Input ...

Page 475: ...output at compare match 1 0 Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 X 0 0 Input capture at rising edge 1 Input capture at falling edge 1 X Input capture register Inpu...

Page 476: ...output at compare match 1 0 Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 X 0 0 Input capture at rising edge 1 Input capture at falling edge 1 X Input capture register Inpu...

Page 477: ...itial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 X 0 0 Input capture at rising edge 1 Input capture at falling edge 1 X Input capture register 2 Input capture at both edges Legend X Don t care Notes 1 After power on reset 0 i...

Page 478: ...output at compare match 1 0 Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 X 0 0 Input capture at rising edge 1 Input capture at falling edge 1 X Input capture register Inpu...

Page 479: ...itial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 X 0 0 Input capture at rising edge 1 Input capture at falling edge 1 X Input capture register 2 Input capture at both edges Legend X Don t care Notes 1 After power on reset 0 i...

Page 480: ...1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 0 0 0 Input capture at rising edge 1 Input capture at falling edge 1 X Input capture at both edges 1 X X Input capture register Capture input sour...

Page 481: ... 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 0 0 0 Input capture at rising edge 1 Input capture at falling edge 1 X Input capture at both edges 1 X X Input capture register 2 Capture input source is channel 1 count clock Input capture at TCNT_1 count up count down Lege...

Page 482: ...t is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 0 0 0 Input capture at rising edge 1 Input capture at falling edge 1 X Input capture at both edges 1 X X Input capture register Input captu...

Page 483: ...output at compare match 1 0 Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 X 0 0 Input capture at rising edge 1 Input capture at falling edge 1 X Input capture register Inpu...

Page 484: ...output at compare match 1 0 Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 X 0 0 Input capture at rising edge 1 Input capture at falling edge 1 X Input capture register Inpu...

Page 485: ...itial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 X 0 0 Input capture at rising edge 1 Input capture at falling edge 1 X Input capture register 2 Input capture at both edges Legend X Don t care Notes 1 After power on reset 0 i...

Page 486: ...output at compare match 1 0 Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 X 0 0 Input capture at rising edge 1 Input capture at falling edge 1 X Input capture register Inpu...

Page 487: ...itial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 X 0 0 Input capture at rising edge 1 Input capture at falling edge 1 X Input capture register 2 Input capture at both edges Legend X Don t care Notes 1 After power on reset 0 i...

Page 488: ... input capture compare match 0 A D converter start request generation disabled 1 A D converter start request generation enabled 6 TTGE2 0 R W A D Converter Start Request Enable 2 Enables or disables generation of A D converter start requests by TCNT_4 underflow trough in complementary PWM mode In channels 0 to 3 bit 6 is reserved It is always read as 0 and the write value should always be 0 0 A D ...

Page 489: ... bit disabled 1 Interrupt requests TGID by TGFD bit enabled 2 TGIEC 0 R W TGR Interrupt Enable C Enables or disables interrupt requests TGIC by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0 3 and 4 In channels 1 and 2 bit 2 is reserved It is always read as 0 and the write value should always be 0 0 Interrupt requests TGIC by TGFC bit disabled 1 Interrupt requests TGIC by TGFC bit...

Page 490: ...mpare match between TCNT_0 and TGRE_0 disabled 1 A D converter start request generation by compare match between TCNT_0 and TGRE_0 enabled 6 to 2 All 0 R Reserved These bits are always read as 0 The write value should always be 0 1 TGIEF 0 R W TGR Interrupt Enable F Enables or disables interrupt requests by compare match between TCNT_0 and TGRF_0 0 Interrupt requests TGIF by TGFE bit disabled 1 In...

Page 491: ... Initial Value R W Description 7 TCFD 1 R Count Direction Flag Status flag that shows the direction in which TCNT counts in channels 1 to 4 In channel 0 bit 7 is reserved It is always read as 1 and the write value should always be 1 0 TCNT counts down 1 TCNT counts up 6 1 R Reserved This bit is always read as 1 The write value should always be 1 5 TCFU 0 R W 1 Underflow Flag Status flag that indic...

Page 492: ...alue underflows changes from H 0001 to H 0000 in complementary PWM mode this flag is also set 3 TGFD 0 R W 1 Input Capture Output Compare Flag D Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0 3 and 4 Only 0 can be written for flag clearing In channels 1 and 2 bit 3 is reserved It is always read as 0 and the write value should always be 0 Clearing con...

Page 493: ...ritten to TGFC after reading TGFC 1 2 Setting conditions When TCNT TGRC and TGRC is functioning as output compare register When TCNT value is transferred to TGRC by input capture signal and TGRC is functioning as input capture register 1 TGFB 0 R W 1 Input Capture Output Compare Flag B Status flag that indicates the occurrence of TGRB input capture or compare match Only 0 can be written for flag c...

Page 494: ...s activated by TGIA interrupt When 0 is written to TGFA after reading TGFA 1 2 Setting conditions When TCNT TGRA and TGRA is functioning as output compare register When TCNT value is transferred to TGRA by input capture signal and TGRA is functioning as input capture register Notes 1 Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way 2 When writing to the timer...

Page 495: ...t indicates the occurrence of compare match between TCNT_0 and TGRF_0 Clearing condition When 0 is written to TGFF after reading TGFF 1 2 Setting condition When TCNT_0 TGRF_0 and TGRF_0 is functioning as compare register 0 TGFE 0 R W 1 Compare Match Flag E Status flag that indicates the occurrence of compare match between TCNT_0 and TGRE_0 Clearing condition When 0 is written to TGFE after reading...

Page 496: ...ould always be 0 2 TTSE 0 R W Timing Select E Specifies the timing for transferring data from TGRF_0 to TGRE_0 when they are used together for buffer operation In channels 3 and 4 bit 2 is reserved It is always read as 0 and the write value should always be 0 0 When compare match E occurs in channel 0 1 When TCNT_0 is cleared 1 TTSB 0 R W Timing Select B Specifies the timing for transferring data ...

Page 497: ... W Input Capture Enable Specifies whether to include the TIOC2B pin in the TGRB_1 input capture conditions 0 Does not include the TIOC2B pin in the TGRB_1 input capture conditions 1 Includes the TIOC2B pin in the TGRB_1 input capture conditions 2 I2AE 0 R W Input Capture Enable Specifies whether to include the TIOC2A pin in the TGRA_1 input capture conditions 0 Does not include the TIOC2A pin in t...

Page 498: ...CNT_3 and TCNT_4 in the MTU2S in synchronization with the MTU2 The MTU2S has one TSYCR in channel 3 but the MTU2 has no TSYCR Bit Initial value R W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W CE0A CE0B CE0C CE0D CE1A CE1B CE2A CE2B Bit Bit Name Initial Value R W Description 7 CE0A 0 R W Clear Enable 0A Enables or disables counter clearing when the TGFA flag of TSR_0 in the MTU2...

Page 499: ...les counter clearing when the TGFA flag of TSR_1 in the MTU2 is set 0 Disables counter clearing by the TGFA flag in TSR_1 1 Enables counter clearing by the TGFA flag in TSR_1 2 CE1B 0 R W Clear Enable 1B Enables or disables counter clearing when the TGFB flag of TSR_1 in the MTU2 is set 0 Disables counter clearing by the TGFB flag in TSR_1 1 Enables counter clearing by the TGFB flag in TSR_1 1 CE2...

Page 500: ...l Value R W Description 15 14 BF 1 0 00 R W TADCOBRA_4 TADCOBRB_4 Transfer Timing Select Select the timing for transferring data from TADCOBRA_4 and TADCOBRB_4 to TADCORA_4 and TADCORB_4 For details see table 11 27 13 to 8 All 0 R Reserved These bits are always read as 0 The write value should always be 0 7 UT4AE 0 R W Up Count TRG4AN Enable Enables or disables A D converter start requests TRG4AN ...

Page 501: ..._4 down count operation 1 A D converter start requests TRG4BN enabled during TCNT_4 down count operation 3 ITA3AE 0 R W TGIA_3 Interrupt Skipping Link Enable Select whether to link A D converter start requests TRG4AN with TGIA_3 interrupt skipping operation 0 Does not link with TGIA_3 interrupt skipping 1 Links with TGIA_3 interrupt skipping 2 ITA4VE 0 R W TCIV_4 Interrupt Skipping Link Enable Sel...

Page 502: ...is enabled while interrupt skipping is disabled A D converter start requests will not be issued Do not set to 1 when complementary PWM mode is not selected Table 11 27 Setting of Transfer Timing by Bits BF1 and BF0 Bit 7 Bit 6 BF1 BF0 Description 0 0 Does not transfer data from the cycle set buffer register to the cycle set register 0 1 Transfers data from the cycle set buffer register to the cycl...

Page 503: ... W R W R W R W R W R W R W R W R W Note TADCORA_4 and TADCORB_4 must not be accessed in eight bits they should always be accessed in 16 bits 11 3 11 Timer A D Converter Start Request Cycle Set Buffer Registers TADCOBRA_4 and TADCOBRB_4 TADCOBRA_4 and TADCOBRB_4 are 16 bit readable writable registers When the crest or trough of the TCNT_4 count is reached these register values are transferred to TA...

Page 504: ...writable registers The MTU2 has eighteen TGR registers six for channel 0 two each for channels 1 and 2 four each for channels 3 and 4 TGRA TGRB TGRC and TGRD function as either output compare or input capture registers TGRC and TGRD for channels 0 3 and 4 can also be designated for operation as buffer registers TGR buffer register combinations are TGRA and TGRC and TGRB and TGRD TGRE_0 and TGRF_0 ...

Page 505: ...utput the counter stops but the TIOC pin output compare output level is retained If TIOR is written to when the CST bit is cleared to 0 the pin output level will be changed to the set initial output value 0 TCNT_4 and TCNT_3 count operation is stopped 1 TCNT_4 and TCNT_3 performs count operation 5 to 3 All 0 R Reserved These bits are always read as 0 The write value should always be 0 2 CST2 0 R W...

Page 506: ...hese bits are used to select whether operation is independent of or synchronized with other channels When synchronous operation is selected the TCNT synchronous presetting of multiple channels and synchronous clearing by counter clearing on another channel are possible To set synchronous operation the SYNC bits for at least two channels must be set to 1 To set synchronous clearing in addition to t...

Page 507: ...ed the TCNT synchronous presetting of multiple channels and synchronous clearing by counter clearing on another channel are possible To set synchronous operation the SYNC bits for at least two channels must be set to 1 To set synchronous clearing in addition to the SYNC bit the TCNT clearing source must also be set by means of bits CCLR0 to CCLR2 in TCR 0 TCNT_2 to TCNT_0 operates independently TC...

Page 508: ...scription 7 to 1 All 0 R Reserved These bits are always read as 0 The write value should always be 0 0 RWE 1 R W Read Write Enable Enables or disables access to the registers which have write protection capability against accidental modification 0 Disables read write access to the registers 1 Enables read write access to the registers Clearing condition When 0 is written to the RWE bit after readi...

Page 509: ...e always read as 1 The write value should always be 1 5 OE4D 0 R W Master Enable TIOC4D This bit enables disables the TIOC4D pin MTU2 output 0 MTU2 output is disabled inactive level 1 MTU2 output is enabled 4 OE4C 0 R W Master Enable TIOC4C This bit enables disables the TIOC4C pin MTU2 output 0 MTU2 output is disabled inactive level 1 MTU2 output is enabled 3 OE3D 0 R W Master Enable TIOC3D This b...

Page 510: ... low level is output 11 3 18 Timer Output Control Register 1 TOCR1 TOCR1 is an 8 bit readable writable register that enables disables PWM synchronized toggle output in complementary PWM mode reset synchronized PWM mode and controls output level inversion of PWM output Bit Initial value R W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R R W R R R W R W R W R W Note This bit can be set to 1 only once after a pow...

Page 511: ...ected 1 OLSN 0 R W Output Level Select N 3 This bit selects the reverse phase output level in reset synchronized PWM mode complementary PWM mode See table 11 28 0 OLSP 0 R W Output Level Select P 3 This bit selects the positive phase output level in reset synchronized PWM mode complementary PWM mode See table 11 29 Notes 1 Setting the TOCL bit to 1 prevents accidental modification when the CPU goe...

Page 512: ...evel High level High level Low level Figure 11 2 shows an example of complementary PWM mode output 1 phase when OLSN 1 OLSP 1 TCNT_3 and TCNT_4 values TGRA_3 TGRA_4 TDDR H 0000 Time TCNT_4 TCNT_3 Positive phase output Reverse phase output Active level Compare match output up count Initial output Initial output Active level Compare match output down count Compare match output down count Compare mat...

Page 513: ... to TOCR2 For details see table 11 30 5 OLS3N 0 R W Output Level Select 3N This bit selects the output level on TIOC4D in reset synchronized PWM mode complementary PWM mode See table 11 31 4 OLS3P 0 R W Output Level Select 3P This bit selects the output level on TIOC4B in reset synchronized PWM mode complementary PWM mode See table 11 32 3 OLS2N 0 R W Output Level Select 2N This bit selects the ou...

Page 514: ...fer register TOLBR to TOCR2 0 1 Transfers data from the buffer register TOLBR to TOCR2 at the crest of the TCNT_4 count Transfers data from the buffer register TOLBR to TOCR2 when TCNT_3 TCNT_4 is cleared 1 0 Transfers data from the buffer register TOLBR to TOCR2 at the trough of the TCNT_4 count Setting prohibited 1 1 Transfers data from the buffer register TOLBR to TOCR2 at the crest and trough ...

Page 515: ...el Low level High level Note The reverse phase waveform initial output value changes to the active level after elapse of the dead time after count start Table 11 34 TIOC4A Output Level Select Function Bit 2 Function Compare Match Output OLS2P Initial Output Active Level Up Count Down Count 0 High level Low level Low level High level 1 Low level High level High level Low level Table 11 35 TIOC3D Ou...

Page 516: ...it Initial value R W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R R R W R W R W R W R W R W OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P Bit Bit Name Initial value R W Description 7 6 All 0 R Reserved These bits are always read as 0 The write value should always be 0 5 OLS3N 0 R W Specifies the buffer value to be transferred to the OLS3N bit in TOCR2 4 OLS3P 0 R W Specifies the buffer value to be transferred to the O...

Page 517: ...l Setting Procedure in Buffer Operation 11 3 21 Timer Gate Control Register TGCR TGCR is an 8 bit readable writable register that controls the waveform output necessary for brushless DC motor control in reset synchronized PWM mode complementary PWM mode These register settings are ineffective for anything other than complementary PWM mode reset synchronized PWM mode Bit Initial value R W 7 6 5 4 3...

Page 518: ...output 1 Reset synchronized PWM complementary PWM output 3 FB 0 R W External Feedback Signal Enable This bit selects whether the switching of the output of the positive reverse phase is carried out automatically with the MTU2 channel 0 TGRA TGRB TGRC input capture signals or by writing 0 or 1 to bits 2 to 0 in TGCR 0 Output switching is external input Input sources are channel 0 TGRA TGRB TGRC inp...

Page 519: ...F OFF ON 1 0 OFF ON OFF ON OFF OFF 1 OFF ON OFF OFF OFF ON 1 0 0 OFF OFF ON OFF ON OFF 1 ON OFF OFF OFF ON OFF 1 0 OFF OFF ON ON OFF OFF 1 OFF OFF OFF OFF OFF OFF 11 3 22 Timer Subcounter TCNTS TCNTS is a 16 bit read only counter that is used only in complementary PWM mode The initial value of TCNTS is H 0000 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 520: ...1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Note Accessing the TDDR in 8 bit units is prohibited Always access in 16 bit units 11 3 24 Timer Cycle Data Register TCDR TCDR is a 16 bit register used only in complementary PWM mode Set half the PWM carrier sync value as the TCDR register value This register is constantly compared with the TCNTS counter in complementary ...

Page 521: ... in 16 bit units 11 3 26 Timer Interrupt Skipping Set Register TITCR TITCR is an 8 bit readable writable register that enables or disables interrupt skipping and specifies the interrupt skipping count The MTU2 has one TITCR Bit Initial value R W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W T3AEN 3ACOR 2 0 T4VEN 4VCOR 2 0 Bit Bit Name Initial value R W Description 7 T3AEN 0 R W T...

Page 522: ...ts the TGIA_3 interrupt skipping count to 1 0 1 0 Sets the TGIA_3 interrupt skipping count to 2 0 1 1 Sets the TGIA_3 interrupt skipping count to 3 1 0 0 Sets the TGIA_3 interrupt skipping count to 4 1 0 1 Sets the TGIA_3 interrupt skipping count to 5 1 1 0 Sets the TGIA_3 interrupt skipping count to 6 1 1 1 Sets the TGIA_3 interrupt skipping count to 7 Table 11 39 Setting of Interrupt Skipping Co...

Page 523: ... 1 the count in these bits is incremented every time a TGIA_3 interrupt occurs Clearing conditions When the 3ACNT2 to 3ACNT0 value in TITCNT matches the 3ACOR2 to 3ACOR0 value in TITCR When the T3AEN bit in TITCR is cleared to 0 When the 3ACOR2 to 3ACOR0 bits in TITCR are cleared to 0 3 0 R Reserved This bit is always read as 0 2 to 0 4VCNT 2 0 000 R TCIV_4 Interrupt Counter While the T4VEN bit in...

Page 524: ...t skipping operation The MTU2 has one TBTER Bit Initial value R W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R R R R R R R W R W BTE 1 0 Bit Bit Name Initial Value R W Description 7 to 2 All 0 R Reserved These bits are always read as 0 The write value should always be 0 1 0 BTE 1 0 00 R W These bits enable or disable transfer from the buffer registers used in complementary PWM mode to the temporary registers...

Page 525: ...gisters with interrupt skipping operation 2 1 1 Setting prohibited Note 1 Data is transferred according to the MD3 to MD0 bit setting in TMDR For details refer to section 11 4 8 Complementary PWM Mode 2 When interrupt skipping is disabled the T3AEN and T4VEN bits are cleared to 0 in the timer interrupt skipping set register TITCR or the skipping count set bits 3ACOR and 4VCOR in TITCR are cleared ...

Page 526: ...3 TDER must be modified only while TCNT stops Bit Initial value R W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 R R R R R R R R W TDER Bit Bit Name Initial Value R W Description 7 to 1 All 0 R Reserved These bits are always read as 0 The write value should always be 0 0 TDER 1 R W Dead Time Enable Specifies whether to generate dead time 0 Does not generate dead time 1 Generates dead time Clearing condition Wh...

Page 527: ...TWCR must be modified only while TCNT stops Bit Initial value R W 7 6 5 4 3 2 1 0 Note Do not set to 1 when complementary PWM mode is not selected 0 0 0 0 0 0 0 0 R W R R R R R R R W CCE WRE Bit Bit Name Initial Value R W Description 7 CCE 0 R W Compare Match Clear Enable Specifies whether to clear counters at TGRA_3 compare match in complementary PWM mode 0 Does not clear counters at TGRA_3 compa...

Page 528: ...re 11 40 0 Outputs the initial value specified in TOCR 1 Retains the waveform output immediately before synchronous clearing Setting condition When 1 is written to WRE after reading WRE 0 Note Do not set to 1 when complementary PWM mode is not selected 11 3 31 Bus Master Interface The timer counters TCNT general registers TGR timer subcounter TCNTS timer cycle buffer register TCBR timer dead time ...

Page 529: ...ple of Count Operation Setting Procedure Figure 11 4 shows an example of the count operation setting procedure Operation selection Select counter clock Periodic counter Select counter clearing source Select output compare register Set period Free running counter Start count operation Free running counter Periodic counter Start count operation 1 2 3 4 5 5 1 Select the counter clock with bits TPSC2 ...

Page 530: ...rates free running counter operation TCNT value H FFFF H 0000 CST bit TCFV Time Figure 11 5 Free Running Counter Operation When compare match is selected as the TCNT clearing source the TCNT counter for the relevant channel performs periodic count operation The TGR register for setting the period is designated as an output compare register and counter clearing by compare match is selected by means...

Page 531: ...f Setting Procedure for Waveform Output by Compare Match Figure 11 7 shows an example of the setting procedure for waveform output by compare match Output selection Select waveform output mode Set output timing Start count operation Waveform output 1 2 3 1 Select initial value 0 output or 1 output and compare match output value 0 output 1 output or toggle output by means of TIOR The set initial va...

Page 532: ...e the pin level does not change TCNT value H FFFF H 0000 TIOCA TIOCB Time TGRA TGRB No change No change No change No change 1 output 0 output Figure 11 8 Example of 0 Output 1 Output Operation Figure 11 9 shows an example of toggle output In this example TCNT has been designated as a periodic counter with counter clearing on compare match B and settings have been made such that the output is toggl...

Page 533: ...the input capture input for channels 0 and 1 Pφ 1 should not be selected as the counter input clock used for input capture input Input capture will not be generated if Pφ 1 is selected a Example of Input Capture Operation Setting Procedure Figure 11 10 shows an example of the input capture operation setting procedure Input selection Select input capture input Start count Input capture operation 1 ...

Page 534: ...ing and falling edges have been selected as the TIOCA pin input capture input edge the falling edge has been selected as the TIOCB pin input capture input edge and counter clearing by TGRB input capture has been designated for TCNT TCNT value H 0180 H 0000 TIOCA TGRA H 0010 H 0005 Counter cleared by TIOCB input falling edge H 0160 H 0005 H 0160 H 0010 TGRB H 0180 TIOCB Time Figure 11 11 Example of...

Page 535: ... synchronous operation Synchronous presetting Counter clearing Synchronous clearing Clearing source generation channel Select counter clearing source Start count Set synchronous counter clearing Start count 1 3 5 4 5 2 Synchronous operation selection 1 Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation 2 When the TCNT counter of any of the chann...

Page 536: ...ronous clearing has been set for the channel 1 and 2 counter clearing source Three phase PWM waveforms are output from pins TIOC0A TIOC1A and TIOC2A At this time synchronous presetting and synchronous clearing by TGRB_0 compare match are performed for channel 0 to 2 TCNT counters and the data set in TGRB_0 is used as the PWM cycle For details of PWM modes see section 11 4 5 PWM Modes TCNT0 to TCNT...

Page 537: ...egister and can only operate as a compare match register Table 11 41 shows the register combinations used in buffer operation Table 11 41 Register Combinations in Buffer Operation Channel Timer General Register Buffer Register 0 TGRA_0 TGRC_0 TGRB_0 TGRD_0 TGRE_0 TGRF_0 3 TGRA_3 TGRC_3 TGRB_3 TGRD_3 4 TGRA_4 TGRC_4 TGRB_4 TGRD_4 When TGR is an output compare register When a compare match occurs th...

Page 538: ...r general register TCNT Input capture signal Figure 11 15 Input Capture Buffer Operation 1 Example of Buffer Operation Setting Procedure Figure 11 16 shows an example of the buffer operation setting procedure Buffer operation Select TGR function Set buffer operation Start count Buffer operation 1 2 3 1 Designate TGR as an input capture register or output compare register by means of TIOR 2 Designa...

Page 539: ...ed to timer general register TGRA This operation is repeated each time that compare match A occurs For details of PWM modes see section 11 4 5 PWM Modes TCNT value TGRB_0 H 0000 TGRC_0 TGRA_0 H 0200 H 0520 TIOCA H 0200 H 0450 H 0520 H 0450 TGRA_0 H 0450 H 0200 Transfer Time Figure 11 17 Example of Buffer Operation 1 b When TGR is an input capture register Figure 11 18 shows an operation example in...

Page 540: ...fer mode registers TBTM_0 TBTM_3 and TBTM_4 Either compare match initial setting or TCNT clearing can be selected for the transfer timing TCNT clearing as transfer timing is one of the following cases When TCNT overflows H FFFF to H 0000 When H 0000 is written to TCNT during counting When TCNT is cleared to H 0000 under the condition specified in the CCLR2 to CCLR0 bits in TCR Note TBTM must be mo...

Page 541: ...low of TCNT_2 as set in bits TPSC0 to TPSC2 in TCR Underflow occurs only when the lower 16 bit TCNT is in phase counting mode Table 11 42 shows the register combinations used in cascaded operation Note When phase counting mode is set for channel 1 the counter clock setting is invalid and the counters operates independently in phase counting mode Table 11 42 Cascaded Combinations Combination Upper ...

Page 542: ...value TIOC2B Input capture from TCNT_2 to TGRB_2 I1BE bit 1 TIOC2B TIOC1B 1 Example of Cascaded Operation Setting Procedure Figure 11 20 shows an example of the setting procedure for cascaded operation Cascaded operation Set cascading Start count Cascaded operation 1 2 1 Set bits TPSC2 to TPSC0 in the channel 1 TCR to B 1111 to select TCNT_2 overflow underflow counting 2 Set the CST bit in TSTR fo...

Page 543: ...ions In this example the IOA0 to IOA3 bits in TIOR_1 have selected the TIOC1A rising edge for the input capture timing while the IOA0 to IOA3 bits in TIOR_2 have selected the TIOC2A rising edge for the input capture timing Under these conditions the rising edge of both TIOC1A and TIOC2A is used for the TGRA_1 input capture condition For the TGRA_2 input capture condition the TIOC2A rising edge is ...

Page 544: ...1 and TGRA_2 input capture conditions respectively In this example the IOA0 to IOA3 bits in both TIOR_1 and TIOR_2 have selected both the rising and falling edges for the input capture timing Under these conditions the ORed result of TIOC1A and TIOC2A input is used for the TGRA_1 and TGRA_2 input capture conditions TCNT_2 value H 0000 TGRA_1 TGRA_2 Time TIOC1A TIOC2A TCNT_1 H 0514 H 0514 H 0513 H ...

Page 545: ...r input capture occurrence for the input capture timing while the IOA0 to IOA3 bits in TIOR_2 have selected the TIOC2A rising edge for the input capture timing Under these conditions as TIOR_1 has selected TGRA_0 compare match or input capture occurrence for the input capture timing the TIOC2A edge is not used for TGRA_1 input capture condition although the I2AE bit in TICCR has been set to 1 TCNT...

Page 546: ...tput from the TIOCA and TIOCC pins at compare matches A and C and the output specified by bits IOB0 to IOB3 and IOD0 to IOD3 in TIOR is output at compare matches B and D The initial output value is the value set in TGRA or TGRC If the set values of paired TGRs are identical the output value does not change when a compare match occurs In PWM mode 1 a maximum 8 phase PWM output is possible PWM mode ...

Page 547: ...RB_0 TIOC0A TIOC0B TGRC_0 TIOC0C 0 TGRD_0 TIOC0C TIOC0D TGRA_1 TIOC1A 1 TGRB_1 TIOC1A TIOC1B TGRA_2 TIOC2A 2 TGRB_2 TIOC2A TIOC2B TGRA_3 Cannot be set TGRB_3 TIOC3A Cannot be set TGRC_3 Cannot be set 3 TGRD_3 TIOC3C Cannot be set TGRA_4 Cannot be set TGRB_4 TIOC4A Cannot be set TGRC_4 Cannot be set 4 TGRD_4 TIOC4C Cannot be set Note In PWM mode 2 PWM output is not possible for the TGR register in ...

Page 548: ...as the TCNT clearing source 3 Use TIOR to designate the TGR as an output compare register and select the initial value and output value 4 Set the cycle in the TGR selected in 2 and set the duty in the other TGR 5 Select the PWM mode with bits MD3 to MD0 in TMDR 6 Set the CST bit in TSTR to 1 to start the count operation Figure 11 25 Example of PWM Mode Setting Procedure 2 Examples of PWM Mode Oper...

Page 549: ...r channels 0 and 1 TGRB_1 compare match is set as the TCNT clearing source and 0 is set for the initial output value and 1 for the output value of the other TGR registers TGRA_0 to TGRD_0 TGRA_1 outputting a 5 phase PWM waveform In this case the value set in TGRB_1 is used as the cycle and the values set in the other TGRs are used as the duty levels TCNT value TGRB_1 H 0000 TIOC0A Counter cleared ...

Page 550: ... rewritten TGRB rewritten TCNT value TGRA H 0000 TIOCA Time TGRB 100 duty TGRB rewritten TGRB rewritten TGRB rewritten Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRA H 0000 TIOCA Time TGRB 100 duty TGRB rewritten TGRB rewritten TGRB rewritten Output does not change when cycle register and duty register compare matches occur simulta...

Page 551: ... If overflow occurs when TCNT is counting up the TCFV flag in TSR is set if underflow occurs when TCNT is counting down the TCFU flag is set The TCFD bit in TSR is the count direction flag Reading the TCFD flag reveals whether TCNT is counting up or down Table 11 45 shows the correspondence between external clock pins and channels Table 11 45 Phase Counting Mode Clock Input Pins External Clock Pin...

Page 552: ...1 30 shows an example of phase counting mode 1 operation and table 11 46 summarizes the TCNT up down count conditions TCNT value Time TCLKA channel 1 TCLKC channel 2 TCLKB channel 1 TCLKD channel 2 Up count Down count Figure 11 30 Example of Phase Counting Mode 1 Operation Table 11 46 Up Down Count Conditions in Phase Counting Mode 1 TCLKA Channel 1 TCLKC Channel 2 TCLKB Channel 1 TCLKD Channel 2 ...

Page 553: ...count TCNT value TCLKA channel 1 TCLKC channel 2 TCLKB channel 1 TCLKD channel 2 Figure 11 31 Example of Phase Counting Mode 2 Operation Table 11 47 Up Down Count Conditions in Phase Counting Mode 2 TCLKA Channel 1 TCLKC Channel 2 TCLKB Channel 1 TCLKD Channel 2 Operation High level Don t care Low level Don t care Low level Don t care High level Up count High level Don t care Low level Don t care ...

Page 554: ...count TCNT value TCLKA channel 1 TCLKC channel 2 TCLKB channel 1 TCLKD channel 2 Figure 11 32 Example of Phase Counting Mode 3 Operation Table 11 48 Up Down Count Conditions in Phase Counting Mode 3 TCLKA Channel 1 TCLKC Channel 2 TCLKB Channel 1 TCLKD Channel 2 Operation High level Don t care Low level Don t care Low level Don t care High level Up count High level Down count Low level Don t care ...

Page 555: ...ns Time Up count Down count TCNT value TCLKA channel 1 TCLKC channel 2 TCLKB channel 1 TCLKD channel 2 Figure 11 33 Example of Phase Counting Mode 4 Operation Table 11 49 Up Down Count Conditions in Phase Counting Mode 4 TCLKA Channel 1 TCLKC Channel 2 TCLKB Channel 1 TCLKD Channel 2 Operation High level Up count Low level Low level Don t care High level High level Down count Low level High level ...

Page 556: ...nter clearing by TGRC_0 compare match TGRA_0 and TGRC_0 are used for the compare match function and are set with the speed control period and position control period TGRB_0 is used for input capture with TGRB_0 and TGRD_0 operating in buffer mode The channel 1 counter input clock is designated as the TGRB_0 input capture source and the pulse widths of 2 phase encoder 4 multiplication pulses are de...

Page 557: ...13 0050 TCNT_1 TCNT_0 Channel 1 TGRA_1 speed period capture TGRA_0 speed control period TGRB_1 position period capture TGRC_0 position control period TGRB_0 pulse width capture TGRD_0 buffer operation Channel 0 TCLKA TCLKB Edge detection circuit Figure 11 34 Phase Counting Mode Application Example ...

Page 558: ...tput Pins for Reset Synchronized PWM Mode Channel Output Pin Description 3 TIOC3B PWM output pin 1 TIOC3D PWM output pin 1 negative phase waveform of PWM output 1 4 TIOC4A PWM output pin 2 TIOC4C PWM output pin 2 negative phase waveform of PWM output 2 TIOC4B PWM output pin 3 TIOC4D PWM output pin 3 negative phase waveform of PWM output 3 Table 11 51 Register Settings for Reset Synchronized PWM Mo...

Page 559: ... timer gate control register TGCR and set the feedback signal input source and output chopping or gate signal direct output 4 Reset TCNT_3 and TCNT_4 to H 0000 5 TGRA_3 is the period register Set the waveform period value in TGRA_3 Set the transition timing of the PWM output waveforms in TGRB_3 TGRA_4 and TGRB_4 Set times within the compare match range of TCNT_3 X TGRA_3 X set value 6 Select enabl...

Page 560: ...erate as upcounters The counter is cleared when a TCNT_3 and TGRA_3 compare match occurs and then begins incrementing from H 0000 The PWM output pin output toggles with each occurrence of a TGRB_3 TGRA_4 TGRB_4 compare match and upon counter clears TGRA_3 TGRB_3 TGRB_4 H 0000 TGRA_4 TIOC3B TIOC3D TIOC4A TIOC4C TIOC4B TIOC4D Time TCNT_3 and TCNT_4 values Figure 11 36 Reset Synchronized PWM Mode Ope...

Page 561: ...gisters used A function to directly cut off the PWM output by using an external signal is supported as a port function Table 11 52 Output Pins for Complementary PWM Mode Channel Output Pin Description 3 TIOC3A Toggle output synchronized with PWM period or I O port TIOC3B PWM output pin 1 TIOC3C I O port TIOC3D PWM output pin 1 non overlapping negative phase waveform of PWM output 1 PWM output with...

Page 562: ...M output 3 compare register Maskable by TRWER setting TGRC_4 PWM output 2 TGRA_4 buffer register Always readable writable TGRD_4 PWM output 3 TGRB_4 buffer register Always readable writable Timer dead time data register TDDR Set TCNT_4 and TCNT_3 offset value dead time value Maskable by TRWER setting Timer cycle data register TCDR Set TCNT_4 upper limit value 1 2 carrier cycle Maskable by TRWER se...

Page 563: ...an always be read or written from the CPU Registers that cannot be read or written from the CPU except for TCNTS which can only be read Registers that can be read or written from the CPU but for which access disabling can be set by TRWER TGRA_3 compare match interrupt TCNT_4 underflow interrupt PWM cycle output PWM output 1 PWM output 2 PWM output 3 PWM output 4 PWM output 5 PWM output 6 Output co...

Page 564: ... using the timer synchro register TSYR 6 Set the output PWM duty in the duty registers TGRB_3 TGRA_4 TGRB_4 and buffer registers TGRD_3 TGRC_4 TGRD_4 Set the same initial value in each corresponding TGR 7 This setting is necessary only when no dead time should be generated Make appropriate settings in the timer dead time enable register TDER so that no dead time is generated 8 Set the dead time in...

Page 565: ...tches TDDR the counter switches to up counting and the operation is repeated in this way TCNT_4 is initialized to H 0000 When the CST bit is set to 1 TCNT4 counts up in synchronization with TCNT_3 and switches to down counting when it matches TCDR On reaching H 0000 TCNT4 switches to up counting and the operation is repeated in this way TCNTS is a read only counter It need not be initialized When ...

Page 566: ...y the CPU Data in a compare register is changed by writing the new data to the corresponding buffer register The buffer registers can be read or written at any time The data written to a buffer register is constantly transferred to the temporary register in the Ta interval Data is not transferred to the temporary register in the Tb interval Data written to a buffer register in this interval is tra...

Page 567: ...refore there are two compare match registers for one phase output with the compare register containing the pre change data and the temporary register containing the new data In this interval the three counters TCNT_3 TCNT_4 and TCNTS and two registers compare register and temporary register are compared and PWM output controlled accordingly ...

Page 568: ...RC_4 Temporary register TEMP2 Compare register TGRA_4 Output waveform Output waveform Tb2 Ta Tb1 Ta Tb2 Ta TCNT_3 TCNT_4 TCNTS Output waveform is active low H 6400 H 0080 H 6400 H 6400 H 0080 H 0080 Transfer from temporary register to compare register Transfer from temporary register to compare register Figure 11 40 Example of Complementary PWM Mode Operation ...

Page 569: ...R bit in the timer dead time enable register TDER should be cleared to 0 TGRC_3 and TGRA_3 should be set to 1 2 the PWM carrier cycle 1 and TDDR should be set to 1 Set the respective initial PWM duty values in buffer registers TGRD_3 TGRC_4 and TGRD_4 The values set in the five buffer registers excluding TDDR are transferred simultaneously to the corresponding compare registers when complementary ...

Page 570: ... relationship between the positive and negative phases This non overlap time is called the dead time The non overlap time is set in the timer dead time data register TDDR The value set in TDDR is used as the TCNT_3 counter start value and creates non overlap between TCNT_3 and TCNT_4 Complementary PWM mode should be cleared before changing the contents of TDDR f Dead Time Suppressing Dead time gen...

Page 571: ... register TGRC_4 Temporary register TEMP2 Compare register TGRA_4 Output waveform Output waveform Ta Tb1 Ta Tb2 Ta TCNT_3 TCNT_4 TCNTS Output waveform is active low Data1 Data2 Data1 Data2 Data1 Data2 Transfer from temporary register to compare register Transfer from temporary register to compare register Figure 11 41 Example of Operation without Dead Time ...

Page 572: ...nd TCDR settings are made by setting the values in buffer registers TGRC_3 and TCBR The values set in TGRC_3 and TCBR are transferred simultaneously to TGRA_3 and TCDR in accordance with the transfer timing selected with bits MD3 to MD0 in the timer mode register TMDR The updated PWM cycle is reflected from the next cycle when the data update is performed at the crest and from the current cycle wh...

Page 573: ... this case the value written to a buffer register is transferred after TCNTS halts The temporary register value is transferred to the compare register at the data update timing set with bits MD3 to MD0 in the timer mode register TMDR Figure 11 43 shows an example of data updating in complementary PWM mode This example shows the mode in which data updating is performed at both the counter crest and...

Page 574: ...er from temporary register to compare register Transfer from temporary register to compare register Transfer from temporary register to compare register Transfer from temporary register to compare register Counter value TGRA_3 TGRC_4 TGRA_4 H 0000 BR data1 data2 data3 data4 data5 data6 data1 data1 data2 data3 data4 data6 data2 data3 data4 data5 data6 Temp_R GR Time Compare register Buffer register...

Page 575: ... mode register TMDR until TCNT_4 exceeds the value set in the dead time register TDDR Figure 11 44 shows an example of the initial output in complementary PWM mode An example of the waveform when the initial PWM duty value is smaller than the TDDR value is shown in figure 11 45 Timer output control register settings OLSN bit 0 initial output high active level low OLSP bit 0 initial output high act...

Page 576: ...N bit 0 initial output high active level low OLSP bit 0 initial output high active level low TCNT_3 4 value TGRA_4 TDDR TCNT_3 TCNT_4 Initial output Time Active level TCNT_3 4 count start TSTR setting Complementary PWM mode TMDR setting Positive phase output Negative phase output Figure 11 45 Example of Initial Output in Complementary PWM Mode 2 ...

Page 577: ...ring prior to a are ignored In the T2 period compare match c that turns off the positive phase has the highest priority and compare matches occurring prior to c are ignored In normal cases compare matches occur in the order a b c d or c d a b as shown in figure 11 46 If compare matches deviate from the a b c d order since the time for which the negative phase is off is less than twice the dead tim...

Page 578: ...d T1 period T1 period a b c a b d TGR3A_3 TCDR TDDR H 0000 Positive phase Negative phase Figure 11 46 Example of Complementary PWM Mode Waveform Output 1 T2 period T1 period T1 period TGRA_3 TCDR TDDR H 0000 Positive phase Negative phase c d a a b b Figure 11 47 Example of Complementary PWM Mode Waveform Output 2 ...

Page 579: ...1 period T2 period T1 period TGRA_3 TCDR TDDR H 0000 Positive phase Negative phase Figure 11 48 Example of Complementary PWM Mode Waveform Output 3 a b c d a b T2 period T1 period T1 period TGRA_3 TCDR TDDR H 0000 Positive phase Negative phase Figure 11 49 Example of Complementary PWM Mode 0 and 100 Waveform Output 1 ...

Page 580: ...iod T1 period TGRA_3 TCDR TDDR H 0000 Positive phase Negative phase a c d a b b Figure 11 50 Example of Complementary PWM Mode 0 and 100 Waveform Output 2 T2 period T1 period T1 period a b c d TGRA_3 TCDR TDDR H 0000 Positive phase Negative phase Figure 11 51 Example of Complementary PWM Mode 0 and 100 Waveform Output 3 ...

Page 581: ... H 0000 Positive phase Negative phase T2 period T1 period T1 period a b c b d a Figure 11 52 Example of Complementary PWM Mode 0 and 100 Waveform Output 4 c a d b T2 period T1 period T1 period TGRA_3 TCDR TDDR H 0000 Positive phase Negative phase Figure 11 53 Example of Complementary PWM Mode 0 and 100 Waveform Output 5 ...

Page 582: ...ches occur simultaneously but if a turn on compare match and turn off compare match for the same phase occur simultaneously both compare matches are ignored and the waveform does not change l Toggle Output Synchronized with PWM Cycle In complementary PWM mode toggle output can be performed in synchronization with the PWM carrier cycle by setting the PSYE bit to 1 in the timer output control regist...

Page 583: ...hronous clearing with bits CCLR2 to CCLR0 in the timer control register TCR it is possible to have TCNT_3 TCNT_4 and TCNTS cleared by another channel Figure 11 55 illustrates the operation Use of this function enables counter clearing and restarting to be performed by means of an external signal TGRA_3 TCDR TDDR H 0000 Channel 1 Input capture A TCNT_1 TCNT_3 TCNT_4 TCNTS Synchronous counter cleari...

Page 584: ... synchronous clearing occurs in the Tb interval at the trough as indicated by 10 or 11 in figure 11 56 When synchronous clearing occurs outside that interval the initial value specified by the OLS bits in TOCR is output Even in the Tb interval at the trough if synchronous clearing occurs in the initial value output period indicated by 1 in figure 11 56 immediately after the counters start operatio...

Page 585: ...ntrol at synchronous counter clearing Set TWCR and complementary PWM mode Start count operation Output waveform control at synchronous counter clearing 1 2 3 1 Clear bits CST3 and CST4 in the timer start register TSTR to 0 and halt timer counter TCNT operation Perform TWCR setting while TCNT_3 and TCNT_4 are stopped 2 Read bit WRE in TWCR and then write 1 to it to suppress initial value output at ...

Page 586: ...M mode and synchronous counter clearing is generated while the WRE bit in TWCR is set to 1 In the examples shown in figures 11 58 to 11 61 synchronous counter clearing occurs at timing 3 6 8 and 11 shown in figure 11 56 respectively TGRA_3 TGRB_3 TCDR TDDR H 0000 Positive phase Negative phase Output waveform is active low Synchronous clearing TCNT_3 MTU2 TCNT_4 MTU2 Bit WRE 1 Figure 11 58 Example ...

Page 587: ...88 REJ09B0313 0050 Positive phase Negative phase Output waveform is active low Synchronous clearing Bit WRE 1 TCNT_3 MTU2 TCNT_4 MTU2 TGRA_3 TGRB_3 TCDR TDDR H 0000 Figure 11 59 Example of Synchronous Clearing in Interval Tb at Crest Timing 6 in Figure 11 56 Bit WRE of TWCR in MTU2 is 1 ...

Page 588: ...8 REJ09B0313 0050 Positive phase Negative phase Output waveform is active low Synchronous clearing Bit WRE 1 TCNT_3 MTU2 TCNT_4 MTU2 TGRA_3 TGRB_3 TCDR TDDR H 0000 Figure 11 60 Example of Synchronous Clearing in Dead Time during Down Counting Timing 8 in Figure 11 56 Bit WRE of TWCR is 1 ...

Page 589: ...050 Positive phase Negative phase Output waveform is active low Synchronous clearing Bit WRE 1 TGRA_3 TGRB_3 TCDR TDDR H 0000 Initial value output is suppressed TCNT_3 MTU2 TCNT_4 MTU2 Figure 11 61 Example of Synchronous Clearing in Interval Tb at Trough Timing 11 in Figure 11 56 Bit WRE of TWCR is 1 ...

Page 590: ...lementary PWM mode 1 transfer at crest 2 Do not specify synchronous clearing by another channel do not set the SYNC0 to SYNC4 bits in the timer synchronous register TSYR to 1 or the CE0A CE0B CE0C CE0D CE1A CE1B CE1C and CE1D bits in the timer synchronous clear register TSYCR to 1 3 Do not set the PWM duty value to H 0000 4 Do not set the PSYE bit in timer output control register 1 TOCR1 to 1 TGRA...

Page 591: ...ed at pin TIOC0A TIOC0B or TIOC0C the output on off state is switched automatically When the FB bit is 1 the output on off state is switched when the UF VF or WF bit in TGCR is cleared to 0 or set to 1 The drive waveforms are output from the complementary PWM mode 6 phase output pins With this 6 phase output in the case of on output it is possible to use complementary PWM mode output and perform c...

Page 592: ...in TIOC4B pin TIOC4D pin 6 phase output When BDC 1 N 1 P 1 FB 0 output active level high Figure 11 64 Example of Output Phase Switching by External Input 2 TGCR UF bit VF bit WF bit TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin 6 phase output When BDC 1 N 0 P 0 FB 1 output active level high Figure 11 65 Example of Output Phase Switching by Means of UF VF WF Bit Settings 1 ...

Page 593: ...nverter Start Request Setting In complementary PWM mode an A D converter start request can be issued using a TGRA_3 compare match TCNT_4 underflow trough or compare match on a channel other than channels 3 and 4 When start requests using a TGRA_3 compare match are specified A D conversion can be started at the crest of the TCNT_3 count A D converter start requests can be set by setting the TTGE bi...

Page 594: ...ests are disabled by the settings of TIER_3 and TIER_4 along with under the conditions in which TGFA_3 and TCFV_4 flag settings by compare match never occur Before changing the skipping count be sure to clear the T3AEN and T4VEN bits to 0 to clear the skipping counter a Example of Interrupt Skipping Operation Setting Procedure Figure 11 67 shows an example of the interrupt skipping operation setti...

Page 595: ...count can be performed Figure 11 68 Periods during which Interrupt Skipping Count can be Changed b Example of Interrupt Skipping Operation Figure 11 69 shows an example of TGIA_3 interrupt skipping in which the interrupt skipping count is set to three by the 3ACOR bit and the T3AEN bit is set to 1 in the timer interrupt skipping set register TITCR TGIA_3 interrupt flag set signal Skipping counter ...

Page 596: ...While this setting is valid data is not transferred from the buffer register outside the buffer transfer enabled period Note that the buffer transfer enabled period depends on the T3AEN and T4VEN bit settings in the timer interrupt skipping set register TITCR Figure 11 72 shows the relationship between the T3AEN and T4VEN bit settings in TITCR and buffer transfer enabled period Note This function ...

Page 597: ...ER Bit BTE0 in TBTER 1 No data is transferred from the buffer register to the temporary register in the buffer transfer disabled period bits BTE1 and BTE0 in TBTER are set to 0 and 1 respectively 2 Data is transferred from the temporary register to the general register even in the buffer transfer disabled period 3 After buffer transfer is enabled data is transferred from the buffer register to the...

Page 598: ...ffer transfer enabled period Figure 11 71 Example of Operation when Buffer Transfer is Linked with Interrupt Skipping BTE1 1 and BTE0 0 Note The skipping count is set to three Buffer transfer enabled period T3AEN is set to 1 Buffer transfer enabled period T4VEN is set to 1 Buffer transfer enabled period T3AEN and T4VEN are set to 1 0 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 Skipping counter 3ACNT Skipping ...

Page 599: ...ters used in complementary PWM mode by means of the RWE bit in the timer read write enable register TRWER The applicable registers are some 21 in total of the registers in channels 3 and 4 shown in the following TCR_3 and TCR_4 TMDR_3 and TMDR_4 TIORH_3 and TIORH_4 TIORL_3 and TIORL_4 TIER_3 and TIER_4 TCNT_3 and TCNT_4 TGRA_3 and TGRA_4 TGRB_3 and TGRB_4 TOER TOCR TGCR TCDR and TDDR This function...

Page 600: ...st cycle A D converter start request delaying function Set the timing of transfer from cycle set buffer register Set linkage with interrupt skipping Enable A D converter start request delaying function A D converter start request delaying function 1 2 1 Set the cycle in the timer A D converter start request cycle buffer register TADCOBRA_4 or TADCOBRB_4 and timer A D converter start request cycle ...

Page 601: ...ated by writing data to the timer A D converter start request cycle set buffer registers TADCOBRA_4 and TADCOBRB_4 Data is transferred from the buffer registers to the respective cycle set registers at the timing selected with the BF1 and BF0 bits in the timer A D converter start request control register TADCR_4 A D Converter Start Request Delaying Function Linked with Interrupt Skipping A D conve...

Page 602: ...ipping clear the ITA3AE ITA4VE ITB3AE and ITB4VE bits in the timer A D converter start request control register TADCR to 0 TADCORA_4 TCNT_4 A D converter start request TRG4AN Note When the interrupt skipping count is set to two TGIA_3 interrupt skipping counter TCIV_4 interrupt skipping counter TGIA_3 A D request enabled period TCIV_4 A D request enabled period When linked with TGIA_3 and TCIV_4 i...

Page 603: ...counter TCIV_4 interrupt skipping counter TGIA_3 A D request enabled period TCIV_4 A D request enabled period When linked with TGIA_3 and TCIV_4 interrupt skipping When linked with TGIA_3 interrupt skipping When linked with TCIV_4 interrupt skipping TADCORA_4 TCNT_4 00 01 00 01 02 00 01 00 01 02 UT4AE 1 DT4AE 0 Figure 11 76 Example of A D Converter Start Request Signal TRG4AN Operation Linked with...

Page 604: ...g in TGR can be selected by TIOR Figure 11 77 shows an example in which TCNT is used as a free running counter without being cleared and the TCNT value is captured in TGR at the specified timing either crest or trough or both crest and trough Tdead Tdelay Upper arm signal Lower arm signal Inverter output monitor signal Dead time delay signal TGRA_4 3DE7 3E5B 3E5B 3ED3 3ED3 3F37 3F37 3FAF 3FAF 3DE7...

Page 605: ... fixed For details see section 6 Interrupt Controller INTC Table 11 55 lists the MTU2 interrupt sources Table 11 55 MTU2 Interrupts Channel Name Interrupt Source Interrupt Flag DMAC Activation Priority 0 TGIA_0 TGRA_0 input capture compare match TGFA_0 Possible High TGIB_0 TGRB_0 input capture compare match TGFB_0 Not possible TGIC_0 TGRC_0 input capture compare match TGFC_0 Not possible TGID_0 TG...

Page 606: ... 1 Input Capture Compare Match Interrupt An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture compare match on a particular channel The interrupt request is cleared by clearing the TGF flag to 0 The MTU2 has eighteen input capture compare match interrupts six for channel 0 four each for channels 3 and 4 and two ...

Page 607: ...ted at the trough of TCNT_4 count TCNT_4 H 0000 A D converter start request signal TRGAN is issued to the A D converter under either one of the following conditions When the TGFA flag in TSR is set to 1 by the occurrence of a TGRA input capture compare match on a particular channel while the TTGE bit in TIER is set to 1 When the TCNT_4 count reaches the trough TCNT_4 H 0000 during complementary PW...

Page 608: ...ter Start Request Delaying Function A D conversion will start if A D converter start signal TRG4AN from the MTU2 is selected as the trigger in the A D converter when TRG4AN is generated or if TRG4BN from the MTU2 is selected as the trigger in the A D converter when TRG4BN is generated Table 11 56 Interrupt Sources and A D Converter Start Request Signals Target Registers Interrupt Source A D Conver...

Page 609: ... normal mode and figure 11 80 shows TCNT count timing in external clock operation phase counting mode TCNT TCNT input clock Internal clock Pφ Falling edge Rising edge N 1 N N 1 Figure 11 78 Count Timing in Internal Clock Operation Pφ TCNT TCNT input clock External clock Falling edge Rising edge N 1 N N 1 Figure 11 79 Count Timing in External Clock Operation Pφ External clock TCNT input clock TCNT ...

Page 610: ...nerated the output value set in TIOR is output at the output compare output pin TIOC pin After a match between TCNT and TGR the compare match signal is not generated until the TCNT input clock is generated Figure 11 81 shows output compare output timing normal mode and PWM mode and figure 11 82 shows output compare output timing complementary PWM mode and reset synchronous PWM mode TGR TCNT TCNT i...

Page 611: ... N 1 TGR Compare match signal TIOC pin N Pφ Figure 11 82 Output Compare Output Timing Complementary PWM Mode Reset Synchronous PWM Mode 3 Input Capture Signal Timing Figure 11 83 shows input capture signal timing TCNT Input capture input N N 1 N 2 N N 2 TGR Input capture signal Pφ Figure 11 83 Input Capture Input Signal Timing ...

Page 612: ...shows the timing when counter clearing on compare match is specified and figure 11 85 shows the timing when counter clearing on input capture is specified Pφ TCNT Counter clear signal Compare match signal TGR N N H 0000 Figure 11 84 Counter Clear Timing Compare Match TCNT Counter clear signal Input capture signal TGR N H 0000 N Pφ Figure 11 85 Counter Clear Timing Input Capture ...

Page 613: ... Operation Timing Figures 11 86 to 11 88 show the timing in buffer operation TGRA TGRB Compare match buffer signal TCNT TGRC TGRD n N N n n 1 Pφ Figure 11 86 Buffer Operation Timing Compare Match TGRA TGRB TCNT Input capture signal TGRC TGRD N n n N 1 N N N 1 Pφ Figure 11 87 Buffer Operation Timing Input Capture ...

Page 614: ... n H 0000 Figure 11 88 Buffer Transfer Timing when TCNT Cleared 6 Buffer Transfer Timing Complementary PWM Mode Figures 11 89 to 11 91 show the buffer transfer timing in complementary PWM mode Buffer register TGRD_4 write signal Temporary register transfer signal TCNTS Pφ Temporary register n N n N H 0000 Figure 11 89 Transfer Timing from Buffer Register to Temporary Register TCNTS Stop ...

Page 615: ...er TGRD_4 write signal TCNTS Pφ Temporary register n N n N P x P H 0000 Figure 11 90 Transfer Timing from Buffer Register to Temporary Register TCNTS Operating Temporary register Buffer transfer signal TCNTS Pφ Compare register N n N P 1 P H 0000 Figure 11 91 Transfer Timing from Temporary Register to Compare Register ...

Page 616: ...upt Signal Timing 1 TGF Flag Setting Timing in Case of Compare Match Figure 11 92 shows the timing for setting of the TGF flag in TSR on compare match and TGI interrupt request signal timing TGR TCNT TCNT input clock N N N 1 Compare match signal TGF flag TGI interrupt Pφ Figure 11 92 TGI Interrupt Timing Compare Match ...

Page 617: ...09B0313 0050 2 TGF Flag Setting Timing in Case of Input Capture Figure 11 93 shows the timing for setting of the TGF flag in TSR on input capture and TGI interrupt request signal timing TGR TCNT Input capture signal N N TGF flag TGI interrupt Pφ Figure 11 93 TGI Interrupt Timing Input Capture ...

Page 618: ... TCIV interrupt request signal timing Figure 11 95 shows the timing for setting of the TCFU flag in TSR on underflow and TCIU interrupt request signal timing Overflow signal TCNT overflow TCNT input clock H FFFF H 0000 TCFV flag TCIV interrupt Pφ Figure 11 94 TCIV Interrupt Setting Timing Underflow signal TCNT underflow TCNT input clock H 0000 H FFFF TCFU flag TCIU interrupt Pφ Figure 11 95 TCIU I...

Page 619: ...e 11 96 shows the timing for status flag clearing by the CPU and figure 11 97 shows the timing for status flag clearing by the DMAC Status flag Write signal Address TSR address Interrupt request signal TSR write cycle T1 T2 Pφ Figure 11 96 Timing for Status Flag Clearing by CPU Interrupt request signal Flag clear signal Status flag Address Source address DMAC read cycle Destination address DMAC wr...

Page 620: ...states in the case of single edge detection and at least 2 5 states in the case of both edge detection The MTU2 will not operate properly at narrower pulse widths In phase counting mode the phase difference and overlap between the two input clocks must be at least 1 5 states and the pulse width must be at least 2 5 states Figure 11 98 shows the input clock conditions in phase counting mode Overlap...

Page 621: ...ter frequency is given by the following formula f Pφ N 1 Where f Counter frequency Pφ Peripheral clock operating frequency N TGR set value 11 7 4 Contention between TCNT Write and Clear Operations If the counter clear signal is generated in the T2 state of a TCNT write cycle TCNT clearing takes precedence and the TCNT write is not performed Figure 11 99 shows the timing in this case Counter clear ...

Page 622: ...ment Operations If incrementing occurs in the T2 state of a TCNT write cycle the TCNT write takes precedence and TCNT is not incremented Figure 11 100 shows the timing in this case TCNT input clock Write signal Address TCNT address TCNT TCNT write cycle T1 T2 N M TCNT write data Pφ Figure 11 100 Contention between TCNT Write and Increment Operations ...

Page 623: ...ch If a compare match occurs in the T2 state of a TGR write cycle the TGR write is executed and the compare match signal is also generated Figure 11 101 shows the timing in this case Compare match signal Write signal Address TGR address TCNT TGR write cycle T1 T2 N M TGR write data TGR N N 1 Pφ Figure 11 101 Contention between TGR Write and Compare Match ...

Page 624: ... T2 state of a TGR write cycle the data that is transferred to TGR by the buffer operation is the data after write Figure 11 102 shows the timing in this case Address Write signal Compare match signal Compare match buffer signal TGR write cycle T1 T2 Buffer register address N N M Buffer register write data Buffer register TGR Pφ Figure 11 102 Contention between Buffer Register Write and Compare Ma...

Page 625: ...sfer mode register TBTM if TCNT clear occurs in the T2 state of a TGR write cycle the data that is transferred to TGR by the buffer operation is the data before write Figure 11 103 shows the timing in this case Address Write signal TCNT clear signal Buffer transfer signal TGR write cycle T1 T2 Buffer register address N N M Buffer register write data Buffer register TGR Pφ Figure 11 103 Contention ...

Page 626: ...n input capture signal is generated in the T1 state of a TGR read cycle the data that is read will be the data in the buffer before input capture transfer Figure 11 104 shows the timing in this case Input capture signal Read signal Address TGR read cycle T1 T2 TGR Internal data bus TGR address Pφ N N M Figure 11 104 Contention between TGR Read and Input Capture ...

Page 627: ...e If an input capture signal is generated in the T2 state of a TGR write cycle the input capture operation takes precedence and the write to TGR is not performed Figure 11 105 shows the timing in this case Input capture signal Write signal Address TCNT TGR write cycle T1 T2 M TGR M TGR address Pφ Figure 11 105 Contention between TGR Write and Input Capture ...

Page 628: ...d Overflow Underflow Contention in Cascade Connection With timer counters TCNT1 and TCNT2 in a cascade connection when a contention occurs during TCNT_1 count during a TCNT_2 overflow underflow in the T2 state of the TCNT_2 write cycle the write to TCNT_2 is conducted and the TCNT_1 count signal is disabled At this point if there is match with TGRA_1 and the TCNT_1 value a compare signal is issued...

Page 629: ...TCNT_2 write data TCNT_2 address TCNT write cycle Address Write signal TCNT_2 TGRA_2 to TGRB_2 Ch2 compare match signal A B TCNT_1 input clock TCNT_1 TGRA_1 Ch1 compare match signal A TGRB_1 Ch1 input capture signal B TCNT_0 TGRA_0 to TGRD_0 Ch0 input capture signal A to D Pφ Figure 11 107 TCNT_2 Write and Overflow Underflow Contention with Cascade Connection ...

Page 630: ... TGRA_3 TCDR TDDR H 0000 TCNT_3 TCNT_4 Complementary PWM mode operation Complementary PWM mode operation Counter operation stop Complementary PMW restart Figure 11 108 Counter Value during Complementary PWM Mode Stop 11 7 14 Buffer Operation Setting in Complementary PWM Mode In complementary PWM mode conduct rewrites by buffer operation for the PWM cycle setting register TGRA_3 timer cycle data re...

Page 631: ... to 1 TGRC_3 functions as the buffer register for TGRA_3 At the same time TGRC_4 functions as the buffer register for TGRA_4 The TGFC bit and TGFD bit of TSR_3 and TSR_4 are not set when TGRC_3 and TGRD_3 are operating as buffer registers Figure 11 109 shows an example of operations for TGR_3 TGR_4 TIOC3 and TIOC4 with TMDR_3 s BFA and BFB bits set to 1 and TMDR_4 s BFA and BFB bits set to 0 TGRA_...

Page 632: ... when specifying TGR3A compare match for the counter clear source TCNT_3 and TCNT_4 count up to H FFFF then a compare match occurs with TGRA_3 and TCNT_3 and TCNT_4 are both cleared At this point TSR s overflow flag TCFV bit is not set Figure 11 110 shows a TCFV bit operation example in reset synchronous PWM mode with a set value for cycle register TGRA_3 of H FFFF when a TGRA_3 compare match has ...

Page 633: ...low and counter clearing occur simultaneously the TCFV TCFU flag in TSR is not set and TCNT clearing takes precedence Figure 11 111 shows the operation timing when a TGR compare match is specified as the clearing source and when H FFFF is set in TGR Counter clear signal TCNT TCNT input clock H FFFF H 0000 TGF TCFV Disabled MPφ Figure 11 111 Contention between Overflow and Counter Clearing ...

Page 634: ...chronized PWM Mode When making a transition from channel 3 or 4 normal operation or PWM mode 1 to reset synchronized PWM mode if the counter is halted with the output pins TIOC3B TIOC3D TIOC4A TIOC4C TIOC4B TIOC4D in the high level state followed by the transition to reset synchronized PWM mode and operation in that mode the initial pin output will not be correct When making a transition from norm...

Page 635: ...ode 11 7 22 Simultaneous Capture of TCNT_1 and TCNT_2 in Cascade Connection When timer counters 1 and 2 TCNT_1 and TCNT_2 are operated as a 32 bit counter in cascade connection the cascade counter value cannot be captured successfully even if input capture input is simultaneously done to TIOC1A and TIOC2A or to TIOC1B and TIOC2B This is because the input timing of TIOC1A and TIOC2A or of TIOC1B an...

Page 636: ...tialization method for each of these modes is described in this section 11 8 2 Reset Start Operation The MTU2 output pins TIOC are initialized low by a reset and in standby mode Since MTU2 pin function selection is performed by the pin function controller PFC when the PFC is set the MTU2 pin states at that point are output to the ports When MTU2 output is selected by the PFC immediately after a re...

Page 637: ... restarting in a different mode after re setting are shown below The MTU2 has six operating modes as stated above There are thus 36 mode transition combinations but some transitions are not available with certain channel and mode combinations Possible mode transition combinations are shown in table 11 57 Table 11 57 Mode Transition Combinations After Before Normal PWM1 PWM2 PCM CPWM RPWM Normal 1 ...

Page 638: ...GRD operate as buffer registers setting TIOR will not initialize the buffer register pins If initialization is required clear buffer mode carry out initialization then set buffer mode again In PWM mode 1 if either TGRC or TGRD operates as a buffer register setting TIOR will not initialize the TGRC pin To initialize the TGRC pin clear buffer mode carry out initialization then set buffer mode again ...

Page 639: ...gh Z Figure 11 113 Error Occurrence in Normal Mode Recovery in Normal Mode 1 After a reset MTU2 output is low and ports are in the high impedance state 2 After a reset the TMDR setting is for normal mode 3 For channels 3 and 4 enable output with TOER before initializing the pins with TIOR 4 Initialize the pins with TIOR The example shows initial high output with low output on compare match occurre...

Page 640: ... MTU2 4 TIOR 1 init 0 out 6 TSTR 1 7 Match 8 Error occurs 9 PFC PORT 10 TSTR 0 11 TMDR PWM1 12 TIOR 1 init 0 out 13 PFC MTU2 14 TSTR 1 MTU2 module output TIOC A TIOC B Port output PEn PEn Not initialized TIOC B n 0 to 15 High Z High Z Figure 11 114 Error Occurrence in Normal Mode Recovery in PWM Mode 1 1 to 10 are the same as in figure 11 113 11 Set PWM mode 1 12 Initialize the pins with TIOR In P...

Page 641: ... 9 PFC PORT 10 TSTR 0 11 TMDR PWM2 12 TIOR 1 init 0 out 13 PFC MTU2 14 TSTR 1 MTU2 module output TIOC A TIOC B Port output PEn PEn Not initialized cycle register n 0 to 15 High Z High Z Figure 11 115 Error Occurrence in Normal Mode Recovery in PWM Mode 2 1 to 10 are the same as in figure 11 113 11 Set PWM mode 2 12 Initialize the pins with TIOR In PWM mode 2 the cycle register pins are not initial...

Page 642: ...DR normal 3 TOER 1 5 PFC MTU2 4 TIOR 1 init 0 out 6 TSTR 1 7 Match 8 Error occurs 9 PFC PORT 10 TSTR 0 11 TMDR PCM 12 TIOR 1 init 0 out 13 PFC MTU2 14 TSTR 1 MTU2 module output TIOC A TIOC B Port output PEn PEn n 0 to 15 High Z High Z Figure 11 116 Error Occurrence in Normal Mode Recovery in Phase Counting Mode 1 to 10 are the same as in figure 11 113 11 Set phase counting mode 12 Initialize the p...

Page 643: ...0 out 12 TIOR disabled 13 TOER 0 14 TOCR 15 TMDR CPWM 16 TOER 1 17 PFC MTU2 18 TSTR 1 MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 High Z High Z High Z Figure 11 117 Error Occurrence in Normal Mode Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 11 113 11 Initialize the normal mode waveform generation section with TIOR 12 Disable operation of the normal mod...

Page 644: ...MTU2 4 TIOR 1 init 0 out 6 TSTR 1 7 Match 8 Error occurs 9 PFC PORT 10 TSTR 0 11 TIOR 0 init 0 out 12 TIOR disabled 13 TOER 0 14 TOCR 15 TMDR RPWM 16 TOER 1 17 PFC MTU2 18 TSTR 1 MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 High Z High Z High Z Figure 11 118 Error Occurrence in Normal Mode Recovery in Reset Synchronized PWM Mode 1 to 13 are the same as in figure 11 113 14 Selec...

Page 645: ... 0 to 15 High Z High Z Figure 11 119 Error Occurrence in PWM Mode 1 Recovery in Normal Mode 1 After a reset MTU2 output is low and ports are in the high impedance state 2 Set PWM mode 1 3 For channels 3 and 4 enable output with TOER before initializing the pins with TIOR 4 Initialize the pins with TIOR The example shows initial high output with low output on compare match occurrence In PWM mode 1 ...

Page 646: ... TOER 1 5 PFC MTU2 4 TIOR 1 init 0 out 6 TSTR 1 7 Match 8 Error occurs 9 PFC PORT 10 TSTR 0 11 TMDR PWM1 12 TIOR 1 init 0 out 13 PFC MTU2 14 TSTR 1 MTU2 module output TIOC A TIOC B Port output PEn PEn Not initialized TIOC B Not initialized TIOC B n 0 to 15 High Z High Z Figure 11 120 Error Occurrence in PWM Mode 1 Recovery in PWM Mode 1 1 to 10 are the same as in figure 11 119 11 Not necessary whe...

Page 647: ...STR 1 7 Match 8 Error occurs 9 PFC PORT 10 TSTR 0 11 TMDR PWM2 12 TIOR 1 init 0 out 13 PFC MTU2 14 TSTR 1 MTU2 module output TIOC A TIOC B Port output PEn PEn Not initialized TIOC B Not initialized cycle register n 0 to 15 High Z High Z Figure 11 121 Error Occurrence in PWM Mode 1 Recovery in PWM Mode 2 1 to 10 are the same as in figure 11 119 11 Set PWM mode 2 12 Initialize the pins with TIOR In ...

Page 648: ...TOER 1 5 PFC MTU2 4 TIOR 1 init 0 out 6 TSTR 1 7 Match 8 Error occurs 9 PFC PORT 10 TSTR 0 11 TMDR PCM 12 TIOR 1 init 0 out 13 PFC MTU2 14 TSTR 1 MTU2 module output TIOC A TIOC B Port output PEn PEn Not initialized TIOC B n 0 to 15 High Z High Z Figure 11 122 Error Occurrence in PWM Mode 1 Recovery in Phase Counting Mode 1 to 10 are the same as in figure 11 119 11 Set phase counting mode 12 Initia...

Page 649: ...OER 1 18 PFC MTU2 19 TSTR 1 MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 Not initialized TIOC3B Not initialized TIOC3D High Z High Z High Z Figure 11 123 Error Occurrence in PWM Mode 1 Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 11 119 11 Set normal mode for initialization of the normal mode waveform generation section 12 Initialize the PWM mode 1 wavef...

Page 650: ...1 7 Match 8 Error occurs 9 PFC PORT 10 TSTR 0 11 TMDR normal 12 TIOR 0 init 0 out 13 TIOR disabled 14 TOER 0 15 TOCR 16 TMDR RPWM 17 TOER 1 18 PFC MTU2 19 TSTR 1 MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 Not initialized TIOC3B Not initialized TIOC3D High Z High Z High Z Figure 11 124 Error Occurrence in PWM Mode 1 Recovery in Reset Synchronized PWM Mode 1 to 14 are the same ...

Page 651: ...cycle register n 0 to 15 High Z High Z Figure 11 125 Error Occurrence in PWM Mode 2 Recovery in Normal Mode 1 After a reset MTU2 output is low and ports are in the high impedance state 2 Set PWM mode 2 3 Initialize the pins with TIOR The example shows initial high output with low output on compare match occurrence In PWM mode 2 the cycle register pins are not initialized In the example TIOC A is t...

Page 652: ...SET 2 TMDR PWM2 3 TIOR 1 init 0 out 5 TSTR 1 4 PFC MTU2 6 Match 7 Error occurs 8 PFC PORT 9 TSTR 0 10 TMDR PWM1 11 TIOR 1 init 0 out 12 PFC MTU2 13 TSTR 1 MTU2 module output TIOC A TIOC B Port output PEn PEn Not initialized TIOC B Not initialized cycle register n 0 to 15 High Z High Z Figure 11 126 Error Occurrence in PWM Mode 2 Recovery in PWM Mode 1 1 to 9 are the same as in figure 11 125 10 Set...

Page 653: ...1 init 0 out 5 TSTR 1 4 PFC MTU2 6 Match 7 Error occurs 8 PFC PORT 9 TSTR 0 10 TMDR PWM2 11 TIOR 1 init 0 out 12 PFC MTU2 13 TSTR 1 MTU2 module output TIOC A TIOC B Port output PEn PEn Not initialized cycle register Not initialized cycle register n 0 to 15 High Z High Z Figure 11 127 Error Occurrence in PWM Mode 2 Recovery in PWM Mode 2 1 to 9 are the same as in figure 11 125 10 Not necessary when...

Page 654: ... counting mode after re setting 1 RESET 2 TMDR PWM2 3 TIOR 1 init 0 out 5 TSTR 1 4 PFC MTU2 6 Match 7 Error occurs 8 PFC PORT 9 TSTR 0 10 TMDR PCM 11 TIOR 1 init 0 out 12 PFC MTU2 13 TSTR 1 MTU2 module output TIOC A TIOC B Port output PEn PEn Not initialized cycle register n 0 to 15 High Z High Z Figure 11 128 Error Occurrence in PWM Mode 2 Recovery in Phase Counting Mode 1 to 9 are the same as in...

Page 655: ... module output TIOC A TIOC B Port output PEn PEn n 0 to 15 High Z High Z Figure 11 129 Error Occurrence in Phase Counting Mode Recovery in Normal Mode 1 After a reset MTU2 output is low and ports are in the high impedance state 2 Set phase counting mode 3 Initialize the pins with TIOR The example shows initial high output with low output on compare match occurrence 4 Set MTU2 output with the PFC 5...

Page 656: ...fter re setting 1 RESET 2 TMDR PCM 3 TIOR 1 init 0 out 5 TSTR 1 4 PFC MTU2 6 Match 7 Error occurs 8 PFC PORT 9 TSTR 0 10 TMDR PWM1 11 TIOR 1 init 0 out 12 PFC MTU2 13 TSTR 1 MTU2 module output TIOC A TIOC B Port output PEn PEn Not initialized TIOC B n 0 to 15 High Z High Z Figure 11 130 Error Occurrence in Phase Counting Mode Recovery in PWM Mode 1 1 to 9 are the same as in figure 11 129 10 Set PW...

Page 657: ...setting 1 RESET 2 TMDR PCM 3 TIOR 1 init 0 out 5 TSTR 1 4 PFC MTU2 6 Match 7 Error occurs 8 PFC PORT 9 TSTR 0 10 TMDR PWM2 11 TIOR 1 init 0 out 12 PFC MTU2 13 TSTR 1 MTU2 module output TIOC A TIOC B Port output PEn PEn n 0 to 15 High Z High Z Not initialized cycle register Figure 11 131 Error Occurrence in Phase Counting Mode Recovery in PWM Mode 2 1 to 9 are the same as in figure 11 129 10 Set PW...

Page 658: ... phase counting mode after re setting 1 RESET 2 TMDR PCM 3 TIOR 1 init 0 out 5 TSTR 1 4 PFC MTU2 6 Match 7 Error occurs 8 PFC PORT 9 TSTR 0 10 TMDR PCM 11 TIOR 1 init 0 out 12 PFC MTU2 13 TSTR 1 MTU2 module output TIOC A TIOC B Port output PEn PEn n 0 to 15 High Z High Z Figure 11 132 Error Occurrence in Phase Counting Mode Recovery in Phase Counting Mode 1 to 9 are the same as in figure 11 129 10...

Page 659: ...Z High Z High Z Figure 11 133 Error Occurrence in Complementary PWM Mode Recovery in Normal Mode 1 After a reset MTU2 output is low and ports are in the high impedance state 2 Select the complementary PWM output level and cyclic output enabling disabling with TOCR 3 Set complementary PWM 4 Enable channel 3 and 4 output with TOER 5 Set MTU2 output with the PFC 6 The count operation is started by TS...

Page 660: ...2 TOCR 3 TMDR CPWM 5 PFC MTU2 4 TOER 1 6 TSTR 1 7 Match 8 Error occurs 9 PFC PORT 10 TSTR 0 11 TMDR PWM1 12 TIOR 1 init 0 out 13 PFC MTU2 14 TSTR 1 MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 Not initialized TIOC3B Not initialized TIOC3D High Z High Z High Z Figure 11 134 Error Occurrence in Complementary PWM Mode Recovery in PWM Mode 1 1 to 10 are the same as in figure 11 133...

Page 661: ... setting when operation is restarted using the cycle and duty settings at the time the counter was stopped 1 RESET 2 TOCR 3 TMDR CPWM 5 PFC MTU2 4 TOER 1 6 TSTR 1 7 Match 8 Error occurs 9 PFC PORT 10 TSTR 0 11 PFC MTU2 12 TSTR 1 13 Match MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 High Z High Z High Z Figure 11 135 Error Occurrence in Complementary PWM Mode Recovery in Complem...

Page 662: ...PFC MTU2 4 TOER 1 6 TSTR 1 7 Match 8 Error occurs 9 PFC PORT 10 TSTR 0 11 TMDR normal 12 TOER 0 13 TOCR 14 TMDR CPWM 15 TOER 1 16 PFC MTU2 17 TSTR 1 MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 High Z High Z High Z Figure 11 136 Error Occurrence in Complementary PWM Mode Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 11 133 11 Set normal mode and make new ...

Page 663: ... Error occurs 9 PFC PORT 10 TSTR 0 11 TMDR normal 12 TOER 0 13 TOCR 14 TMDR RPWM 15 TOER 1 16 PFC MTU2 17 TSTR 1 MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 High Z High Z High Z Figure 11 137 Error Occurrence in Complementary PWM Mode Recovery in Reset Synchronized PWM Mode 1 to 10 are the same as in figure 11 133 11 Set normal mode MTU2 output goes low 12 Disable channel 3 an...

Page 664: ...rror Occurrence in Reset Synchronized PWM Mode Recovery in Normal Mode 1 After a reset MTU2 output is low and ports are in the high impedance state 2 Select the reset synchronized PWM output level and cyclic output enabling disabling with TOCR 3 Set reset synchronized PWM 4 Enable channel 3 and 4 output with TOER 5 Set MTU2 output with the PFC 6 The count operation is started by TSTR 7 The reset s...

Page 665: ...PFC MTU2 4 TOER 1 6 TSTR 1 7 Match 8 Error occurs 9 PFC PORT 10 TSTR 0 11 TMDR PWM1 12 TIOR 1 init 0 out 13 PFC MTU2 14 TSTR 1 MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 Not initialized TIOC3B Not initialized TIOC3D High Z High Z High Z Figure 11 139 Error Occurrence in Reset Synchronized PWM Mode Recovery in PWM Mode 1 1 to 10 are the same as in figure 11 138 11 Set PWM mode...

Page 666: ...TOER 1 6 TSTR 1 7 Match 8 Error occurs 9 PFC PORT 10 TSTR 0 11 TOER 0 12 TOCR 13 TMDR CPWM 14 TOER 1 15 PFC MTU2 16 TSTR 1 MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 High Z High Z High Z Figure 11 140 Error Occurrence in Reset Synchronized PWM Mode Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 11 138 11 Disable channel 3 and 4 output with TOER 12 Select...

Page 667: ...d in reset synchronized PWM mode after re setting 1 RESET 2 TOCR 3 TMDR RPWM 5 PFC MTU2 4 TOER 1 6 TSTR 1 7 Match 8 Error occurs 9 PFC PORT 10 TSTR 0 11 PFC MTU2 12 TSTR 1 13 Match MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 High Z High Z High Z High Z High Z High Z Figure 11 141 Error Occurrence in Reset Synchronized PWM Mode Recovery in Reset Synchronized PWM Mode 1 to 10 ar...

Page 668: ...Section 11 Multi Function Timer Pulse Unit 2 MTU2 Rev 0 50 May 18 2006 Page 638 of 1588 REJ09B0313 0050 ...

Page 669: ...rrupt request generation on compare match by DMAC setting When not in use the CMT can be stopped by halting its clock supply to reduce power consumption Figure 12 1 shows a block diagram of CMT CMSTR CMCSR_0 CMCOR_0 CMCNT_0 CMT CMI0 Pφ 8 Pφ 32 Pφ 128 Pφ 512 CMI1 CMCSR_1 CMCOR_1 CMCNT_1 Pφ 8 Pφ 32 Pφ 128 Pφ 512 Control circuit Clock selection Channel 0 Channel 1 Clock selection Control circuit CMST...

Page 670: ...match timer start register CMSTR R W H 0000 H FFFEC000 16 Compare match timer control status register_0 CMCSR_0 R W H 0000 H FFFEC002 16 Compare match counter_0 CMCNT_0 R W H 0000 H FFFEC004 8 16 0 Compare match constant register_0 CMCOR_0 R W H FFFF H FFFEC006 8 16 Compare match timer control status register_1 CMCSR_1 R W H 0000 H FFFEC008 16 Compare match counter_1 CMCNT_1 R W H 0000 H FFFEC00A ...

Page 671: ...de Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R W R W STR1 STR0 Bit Bit Name Initial Value R W Description 15 to 2 All 0 R Reserved These bits are always read as 0 The write value should always be 0 1 STR1 0 R W Count Start 1 Specifies whether compare match counter_1 operates or is stopped 0 CMCNT_1 count is stopped 1 CMC...

Page 672: ...ote Only 0 can be written to clear the flag after 1 is read CMF CMIE CKS 1 0 Bit Bit Name Initial Value R W Description 15 to 8 All 0 R Reserved These bits are always read as 0 The write value should always be 0 7 CMF 0 R W Compare Match Flag Indicates whether or not the values of CMCNT and CMCOR match 0 CMCNT and CMCOR values do not match Clearing condition When 0 is written to CMF after reading ...

Page 673: ...1 0 00 R W Clock Select These bits select the clock to be input to CMCNT from four internal clocks obtained by dividing the peripheral clock Pφ When the STR bit in CMSTR is set to 1 CMCNT starts counting on the clock selected with bits CKS 1 0 00 Pφ 8 01 Pφ 32 10 Pφ 128 11 Pφ 512 Note Only 0 can be written to clear the flag after 1 is read ...

Page 674: ...alized to H 0000 by a power on reset or in software standby mode but retains its previous value in module standby mode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W 12 2 4 Compare Match Constant Register CMCOR CMCOR is a 16 bit register that sets the interval up to a compare match with CMC...

Page 675: ...he CMIE bit in CMCSR is set to 1 at this time a compare match interrupt CMI is requested CMCNT then starts counting up again from H 0000 Figure 12 2 shows the operation of the compare match counter CMCOR H 0000 CMCNT value Time Counter cleared by compare match with CMCOR Figure 12 2 Counter Operation 12 3 2 CMCNT Count Timing One of four clocks Pφ 8 Pφ 32 Pφ 128 and Pφ 512 obtained by dividing the...

Page 676: ...ing routine If this operation is not carried out another interrupt will be generated The direct memory access controller DMAC can be set to be activated when a compare match interrupt is requested In this case an interrupt is not issued to the CPU If the setting to activate the DMAC has not been made an interrupt request is sent to the CPU The CMF bit is automatically cleared to 0 when data is tra...

Page 677: ...Pφ Counter clock Compare match signal Clock N 1 Figure 12 4 Timing of CMF Setting 12 4 3 Timing of Compare Match Flag Clearing The CMF bit in CMCSR is cleared by first reading as 1 then writing to 0 However in the case of the DMAC being activated the CMF bit is automatically cleared to 0 when data is transferred by the DMAC ...

Page 678: ...h signal is generated in the T2 cycle while writing to CMCNT clearing CMCNT has priority over writing to it In this case CMCNT is not written to Figure 12 5 shows the timing to clear the CMCNT counter CMCNT T1 T2 CMCNT H 0000 N Peripheral clock Pφ Address signal Internal write signal Counter clear signal CMCSR write cycle Figure 12 5 Conflict between Write and Compare Match Processes of CMCNT ...

Page 679: ...in the T2 cycle while writing to CMCNT in words the writing has priority over the count up In this case the count up is not performed Figure 12 6 shows the timing to write to CMCNT in words CMCNT T1 T2 CMCNT M N Peripheral clock Pφ Address signal Internal write signal CMCNT count up enable signal CMCSR write cycle Figure 12 6 Conflict between Word Write and Count Up Processes of CMCNT ...

Page 680: ... up In this case the count up is not performed The byte data on the other side which is not written to is also not counted and the previous contents are retained Figure 12 7 shows the timing when the count up occurs in the T2 cycle while writing to CMCNTH in bytes CMCNTH T1 T2 CMCNTH M N CMCNTL X X Peripheral clock Pφ Address signal Internal write signal CMCNT count up enable signal CMCSR write cy...

Page 681: ...chdog timer or interval timer 13 1 Features Can be used to ensure the clock oscillation settling time The WDT is used in leaving software standby mode or the temporary standby periods that occur when the clock frequency is changed Can switch between watchdog timer mode and interval timer mode Outputs WDTOVF signal in watchdog timer mode When the counter overflows in watchdog timer mode the WDTOVF ...

Page 682: ...k selector Clock Standby mode Peripheral clock Standby cancellation Reset control Clock selection Overflow Internal reset request Interrupt control Interrupt request Legend WTCSR WTCNT WRCSR Watchdog timer control status register Watchdog timer counter Watchdog reset control status register Note The internal reset signal can be generated by making a register setting Figure 13 1 Block Diagram of WD...

Page 683: ...e 653 of 1588 REJ09B0313 0050 13 2 Input Output Pin Table 13 1 shows the pin configuration of the WDT Table 13 1 Pin Configuration Pin Name Symbol I O Function Watchdog timer overflow WDTOVF Output Outputs the counter overflow signal in watchdog timer mode ...

Page 684: ...tchdog Timer Counter WTCNT WTCNT is an 8 bit readable writable register that is incremented by cycles of the selected clock signal When an overflow occurs it generates a watchdog timer overflow signal WDTOVF in watchdog timer mode and an interrupt in interval timer mode WTCNT is initialized to H 00 by a power on reset caused by the RES pin or in software standby mode Use word access to write to WT...

Page 685: ...rom that for other registers to prevent erroneous writes See section 13 3 4 Notes on Register Access for details 7 6 5 4 3 2 1 0 0 0 0 1 1 0 0 0 R W R W R W R R R W R W R W Bit Initial value R W IOVF WT IT TME CKS 2 0 Bit Bit Name Initial Value R W Description 7 IOVF 0 R W Interval Timer Overflow Indicates that WTCNT has overflowed in interval timer mode This flag is not set in watchdog timer mode...

Page 686: ...k Select These bits select the clock to be used for the WTCNT count from the eight types obtainable by dividing the peripheral clock Pφ The overflow period that is shown inside the parenthesis in the table is the value when the peripheral clock Pφ is 25 MHz Bits 2 to 0 Clock Ratio Overflow Cycle 000 1 Pφ 10 2 µs 001 1 64 Pφ 655 4 µs 010 1 128 Pφ 1 3 ms 011 1 256 Pφ 2 6 ms 100 1 512 Pφ 5 2 ms 101 1...

Page 687: ...erroneous writes See section 13 3 4 Notes on Register Access for details 7 6 5 4 3 2 1 0 0 0 0 1 1 1 1 1 R W R W R W R R R R R Bit Initial value R W WOVF RSTE RSTS Bit Bit Name Initial Value R W Description 7 WOVF 0 R W Watchdog Timer Overflow Indicates that the WTCNT has overflowed in watchdog timer mode This bit is not set in interval timer mode 0 No overflow 1 WTCNT has overflowed in watchdog t...

Page 688: ...tatus register WRCSR are more difficult to write to than other registers The procedures for reading or writing to these registers are given below 1 Writing to WTCNT and WTCSR These registers must be written by a word transfer instruction They cannot be written by a byte or longword transfer instruction When writing to WTCNT set the upper byte to H 5A and transfer the lower byte as the write data a...

Page 689: ...bits are not affected To write to the RSTE and RSTS bits the upper byte must be H 5A and the lower byte must be the write data The values of bits 6 and 5 of the lower byte are transferred to the RSTE and RSTS bits respectively The WOVF bit is not affected Address H FFFE0004 Address H FFFE0004 H A5 H 00 15 8 7 0 H 5A 15 8 7 0 Writing 0 to the WOVF bit Writing to the RSTE and RSTS bits Write data Fi...

Page 690: ... system in software standby mode and clock operation then stops 4 The WDT starts counting by detecting the edge change of the NMI signal 5 When the WDT count overflows the CPG starts supplying the clock and this LSI resumes operation The WOVF flag in WRCSR is not set when this happens 13 4 2 Changing the Frequency To change the frequency used by the PLL use the WDT When changing the frequency only...

Page 691: ...watchdog timer mode 3 While operating in watchdog timer mode rewrite the counter periodically to H 00 to prevent the counter from overflowing 4 When the counter overflows the WDT sets the WOVF flag in WRCSR to 1 and the WDTOVF signal is output externally figure 13 4 The WDTOVF signal can be used to reset the system The WDTOVF signal is output for 64 Pφ clock cycles 5 If the RSTE bit in WRCSR is se...

Page 692: ... signal WDTOVF signal WTCNT value WDTOVF and internal reset generated WT IT TME Timer mode select bit Timer enable bit H 00 written in WTCNT Time 128 Pφ clock cycles 64 Pφ clock cycles Note Internal reset signal occurs only when the RSTE bit is set to 1 Legend WT IT 1 TME 1 WOVF 1 WT IT 1 TME 1 Figure 13 4 Operation in Watchdog Timer Mode ...

Page 693: ...type of count clock in the CKS 2 0 bits in WTCSR and set the initial value of the counter in WTCNT 2 Set the TME bit in WTCSR to 1 to start the count in interval timer mode 3 When the counter overflows the WDT sets the IOVF bit in WTCSR to 1 and an interval timer interrupt request is sent to the INTC The counter then resumes counting H FF ITI ITI ITI ITI H 00 WTCNT value ITI Interval timer interru...

Page 694: ...me difference is referred to as timer variation This also applies to the timing of the first incrementation after WTCNT has been written to during timer operation 13 5 2 Prohibition against Setting H FF to WTCNT When the value in WTCNT reaches H FF the WDT assumes that an overflow has occurred Accordingly when H FF is set in WTCNT an interval timer interrupt or WDT reset will occur immediately reg...

Page 695: ...e bus is released or during DMAC burst transfer manual reset exception handling will be pended until the CPU acquires the bus mastership However if the duration from generation of the manual reset to the bus cycle end is equal to or longer than the duration of the internal manual reset activated the occurrence of the internal manual reset source is ignored instead of being pended and the manual re...

Page 696: ...Section 13 Watchdog Timer WDT Rev 0 50 May 18 2006 Page 666 of 1588 REJ09B0313 0050 ...

Page 697: ...ry format 64 Hz counter indicates the state of the RTC divider circuit between 64 Hz and 1 Hz Start stop function 30 second adjust function Alarm interrupt Frame comparison of seconds minutes hours date day of the week month and year can be used as conditions for the alarm interrupt Periodic interrupts the interrupt cycle may be 1 256 second 1 64 second 1 16 second 1 4 second 1 2 second 1 second o...

Page 698: ...YCNT RYRCNT RMONCNT Oscillator circuit RTC_X1 RTC_X2 RCR2 RCR3 RWKCNT RHRAR RMINAR RDAYAR RWKAR Externally connected circuit Prescaler 32 768 kHz 128 Hz ARM PRD CPU RCR1 RTC operation control circuit R64CNT RSECCNT RSECAR Count Interrupt signals RSECAR RMINAR RHRAR RWKAR RDAYAR RMONAR RYRAR RCR2 RCR3 Second alarm register Minute alarm register Hour alarm register Day of week alarm register Date al...

Page 699: ...nput Output Pin Table 14 1 shows the RTC pin configuration Table 14 1 Pin Configuration Pin Name Symbol I O Description RTC oscillator crystal pin RTC_X1 Input Connects 32 768 kHz crystal resonator for RTC RTC oscillator crystal pin RTC_X2 Output Connects 32 768 kHz crystal resonator for RTC ...

Page 700: ... FFFF 2008 8 Date counter RDAYCNT R W H xx H FFFF 200A 8 Month counter RMONCNT R W H xx H FFFF 200C 8 Year counter RYRCNT R W H xxxx H FFFF 200E 16 Second alarm register RSECAR R W H xx H FFFF 2010 8 Minute alarm register RMINAR R W H xx H FFFF 2012 8 Hour alarm register RHRAR R W H xx H FFFF 2014 8 Day of week alarm register RWKAR R W H xx H FFFF 2016 8 Date alarm register RDAYAR R W H xx H FFFF ...

Page 701: ...e read again after writing 0 to the CF bit in RCR1 since the read value is not valid After the RESET bit or ADJ bit in the RTC control register 2 RCR2 is set to 1 the RTC divider circuit is initialized and R64CNT is initialized 0 1 2 3 4 5 6 7 0 R R R R R R R R BIt Initial value R W 1Hz 2Hz 4Hz 8Hz 16Hz 32Hz 64Hz Bit Bit Name Initial Value R W Description 7 0 R Reserved This bit is always read as ...

Page 702: ...rite processing after stopping the count operation through the setting of the START bit in RCR2 0 1 2 3 4 5 6 7 0 R W R W R W R W R W R W R W R BIt Initial value R W 10 seconds 1 second Bit Bit Name Initial Value R W Description 7 0 R Reserved This bit is always read as 0 The write value should always be 0 6 to 4 10 seconds Undefined R W Counting Ten s Position of Seconds Counts on 0 to 5 for 60 s...

Page 703: ...rite processing after stopping the count operation through the setting of the START bit in RCR2 0 1 2 3 4 5 6 7 0 R W R W R W R W R W R W R W R BIt Initial value R W 10 minutes 1 minute Bit Bit Name Initial Value R W Description 7 0 R Reserved This bit is always read as 0 The write value should always be 0 6 to 4 10 minutes Undefined R W Counting Ten s Position of Minutes Counts on 0 to 5 for 60 m...

Page 704: ...ite processing after stopping the count operation through the setting of the START bit in RCR2 0 1 2 3 4 5 6 7 0 R W R W R W R W R W R W R 0 R BIt Initial value R W 10 hours 1 hour Bit Bit Name Initial Value R W Description 7 6 All 0 R Reserved These bits are always read as 0 The write value should always be 0 5 4 10 hours Undefined R W Counting Ten s Position of Hours Counts on 0 to 2 for ten s p...

Page 705: ...rrors occur Carry out write processing after stopping the count operation through the setting of the START bit in RCR2 0 1 2 3 4 5 6 7 0 R W R W R W R 0 R BIt Initial value R W 0 R 0 R 0 R Day Bit Bit Name Initial Value R W Description 7 to 3 All 0 R Reserved These bits are always read as 0 The write value should always be 0 2 to 0 Day Undefined R W Day of Week Counting Day of week is indicated wi...

Page 706: ...bit in RCR2 The range of date changes with each month and in leap years Confirm the correct setting Leap years are recognized by dividing the year counter RYRCNT values by 400 100 and 4 and obtaining a fractional result of 0 0 1 2 3 4 5 6 7 0 R W R W R W R 0 R BIt Initial value R W 10 days R W R W R W 1 day Bit Bit Name Initial Value R W Description 7 6 All 0 R Reserved These bits are always read ...

Page 707: ... occur Carry out write processing after stopping the count operation through the setting of the START bit in RCR2 Bit Bit Name Initial Value R W Description 7 to 5 All 0 R Reserved These bits are always read as 0 The write value should always be 0 4 10 months Undefined R W Counting Ten s Position of Months 3 to 0 1 month Undefined R W Counting One s Position of Months Counts on 0 to 9 once per mon...

Page 708: ... write processing after stopping the count operation through the setting of the START bit in RCR2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W BIt Initial value R W 1000 years 100 years 10 years 1 year Bit Bit Name Initial Value R W Description 15 to 12 1000 years Undefined R W Counting Thousand s Position of Years 11 to 8 100 years Undefine...

Page 709: ...n is performed only on those with ENB bits set to 1 and if each of those coincides an alarm flag of RCR1 is set to 1 The assignable range is from 00 through 59 ENB bits practically in BCD otherwise operation errors occur 0 1 2 3 4 5 6 7 0 R W R W R W R W R W R W R W R W BIt Initial value R W ENB 10 seconds 1 second Bit Bit Name Initial Value R W Description 7 ENB 0 R W When this bit is set to 1 a ...

Page 710: ...rmed only on those with ENB bits set to 1 and if each of those coincides an alarm flag of RCR1 is set to 1 The assignable range is from 00 through 59 ENB bits practically in BCD otherwise operation errors occur 0 1 2 3 4 5 6 7 0 R W R W R W R W R W R W R W R W BIt Initial value R W ENB 10 minutes 1 minute Bit Bit Name Initial Value R W Description 7 ENB 0 R W When this bit is set to 1 a comparison...

Page 711: ...NB bits set to 1 and if each of those coincides an alarm flag of RCR1 is set to 1 The assignable range is from 00 through 23 ENB bits practically in BCD otherwise operation errors occur 0 1 2 3 4 5 6 7 0 R W R W R W R W R W R W R W 0 R BIt Initial value R W ENB 10 hours 1 hour Bit Bit Name Initial Value R W Description 7 ENB 0 R W When this bit is set to 1 a comparison with the RHRCNT value is per...

Page 712: ... and if each of those coincides an alarm flag of RCR1 is set to 1 The assignable range is from 0 through 6 ENB bits practically in BCD otherwise operation errors occur R W ENB 0 1 2 3 4 5 6 7 0 R W R W R W 0 R BIt Initial value R W 0 R 0 R 0 R Day Bit Bit Name Initial Value R W Description 7 ENB 0 R W When this bit is set to 1 a comparison with the RWKCNT value is performed 6 to 3 All 0 R Reserved...

Page 713: ... bits set to 1 and if each of those coincides an alarm flag of RCR1 is set to 1 The assignable range is from 01 through 31 ENB bits practically in BCD otherwise operation errors occur R W ENB 0 1 2 3 4 5 6 7 0 R W R W R W 0 R BIt Initial value R W 10 days R W R W R W 1 day Bit Bit Name Initial Value R W Description 7 ENB 0 R W When this bit is set to 1 a comparison with the RDAYCNT value is perfor...

Page 714: ...et to 1 and if each of those coincides an alarm flag of RCR1 is set to 1 The assignable range is from 01 through 12 ENB bits practically in BCD otherwise operation errors occur R W ENB 0 1 2 3 4 5 6 7 0 R W R W R W 0 R BIt Initial value R W 0 R 10 months R W R W 1 month Bit Bit Name Initial Value R W Description 7 ENB 0 R W When this bit is set to 1 a comparison with the RMONCNT value is performed...

Page 715: ... 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W BIt Initial value R W 1000 years 100 years 10 years 1 year Bit Bit Name Initial Value R W Description 15 to 12 1000 years Undefined R W Thousand s position of years setting value 11 to 8 100 years Undefined R W Hundred s position of years setting value 7 to 4 10 years Undefined R W Ten s position o...

Page 716: ... AIE AF Bit Bit Name Initial Value R W Description 7 CF Undefined R W Carry Flag Status flag that indicates that a carry has occurred CF is set to 1 when a count up to 64 Hz occurs at the second counter carry or 64 Hz counter read A count register value read at this time cannot be guaranteed another read is required 0 No carry of 64 Hz counter by second counter or 64 Hz counter Clearing condition ...

Page 717: ...terrupts 0 An alarm interrupt is not generated when the AF flag is set to 1 1 An alarm interrupt is generated when the AF flag is set to 1 2 1 All 0 R Reserved These bits are always read as 0 The write value should always be 0 0 AF 0 R W Alarm Flag The AF flag is set when the alarm time which is set by an alarm register ENB bit in RSECAR RMINAR RHRAR RWKAR RDAYAR RMONAR or RYRAR is set to 1 and co...

Page 718: ... When set to 1 PEF generates periodic interrupts 0 Interrupts not generated with the period designated by the bits PES2 to PES0 Clearing condition When 0 is written to PEF 1 Interrupts generated with the period designated by the PES2 to PES0 bits Setting condition When an interrupt is generated with the period designated by the bits PES0 to PES2 or when 1 is written to the PEF flag 6 to 4 PES 2 0 ...

Page 719: ...uit RTC prescaler and R64CNT will be simultaneously reset This bit always reads 0 0 Runs normally 1 30 second adjustment 1 RESET 0 R W Reset Writing 1 to this bit initializes the divider circuit In this case the RESET bit is automatically reset to 0 after 1 is written to and the divider circuit RTC prescaler and R64CNT is reset Thus there is no need to write 1 to this bit This bit is always read a...

Page 720: ...m register comparison is performed only on those with ENB bits set to 1 and if each of those coincides an alarm flag of RCR1 is set to 1 0 1 2 3 4 5 6 7 0 R W 0 R 0 R 0 R 0 R 0 R 0 R 0 R BIt Initial value R W ENB Bit Bit Name Initial Value R W Description 7 ENB 0 R W When this bit is set to 1 comparison of the year alarm register RYRAR and the year counter RYRCNT is performed 6 to 0 All 0 R Reserv...

Page 721: ...the registers should be set after the power is turned on 14 4 2 Setting Time Figure 14 2 shows how to set the time when the clock is stopped Write 1 to RESET and 0 to START in the RCR2 register Order is irrelevant Write 1 to START in the RCR2 register Set seconds minutes hour day day of the week month and year Stop clock reset divider circuit Start clock Figure 14 2 Setting Time ...

Page 722: ...ite 0 to CIE in RCR1 Clear the carry flag Enable the carry interrupt Clear the carry flag Write 0 to CF in RCR1 Set AF in RCR1 to 1 so that alarm flag is not cleared Read RCR1 and check CF bit Write 0 to CIE in RCR1 a To read the time without using interrupts b To read the time using interrupts Figure 14 3 Reading Time If a carry occurs while reading the time the correct time will not be obtained ...

Page 723: ...e 14 4 Using Alarm Function Alarms can be generated using seconds minutes hours day of the week date month year or any combination of these Set the ENB bit in the register on which the alarm is placed to 1 and then set the alarm time in the lower bits Clear the ENB bit in the register on which the alarm is not placed to 0 When the clock and alarm times match 1 is set in the AF bit in RCR1 Alarm de...

Page 724: ...et by bits PES2 to PES0 in RCR2 When the time set by bits PES2 to PES0 has elapsed the PEF is set to 1 The PEF is cleared to 0 upon periodic interrupt generation or when bits PES2 to PES0 are set Periodic interrupt generation can be confirmed by reading this bit but normally the interrupt function is used Set PES2 to PES0 and clear PEF to 0 in RCR2 Clear PEF to 0 Set PES clear PEF Elapse of time s...

Page 725: ... wiring Take care when using a ground plane 4 The crystal oscillation stabilization time may differ depending on the mounted circuit component constants stray capacitance and so forth so a suitable value should be determined in consultation with the resonator manufacturer 5 Place the crystal resonator and load capacitors Cin and Cout as close as possible to the chip Make wiring length as short as ...

Page 726: ...Section 14 Realtime Clock RTC Rev 0 50 May 18 2006 Page 696 of 1588 REJ09B0313 0050 ...

Page 727: ...Data length 7 or 8 bits Stop bit length 1 or 2 bits Parity Even odd or none Receive error detection Parity framing and overrun errors Break detection Break is detected when a framing error is followed by at least one frame at the space 0 level low level It is also detected by reading the RxD level directly from the serial port register when a framing error occurs Clock synchronous serial communica...

Page 728: ...e on chip modem control functions RTS and CTS only channel 3 The quantity of data in the transmit and receive FIFO data registers and the number of receive errors of the receive data in the receive FIFO data register can be ascertained A time out error DR can be detected when receiving in asynchronous mode In asynchronous mode the base clock frequency can be either 16 or 8 times the bit rate When ...

Page 729: ...rity check Transmission reception control Baud rate generator Clock External clock Bus interface Peripheral bus SCRSR SCFRDR SCTSR SCFTDR SCSMR SCSCR SCEMR Legend SCFSR SCBRR SCSPTR SCFCR SCFDR SCLSR Receive shift register Receive FIFO data register Transmit shift register Transmit FIFO data register Serial mode register Serial control register Serial extension mode register Serial status register...

Page 730: ...he pin configuration of the SCIF Table 15 1 Pin Configuration Channel Pin Name Symbol I O Function Serial clock pins SCK0 to SCK3 I O Clock I O Receive data pins RxD0 to RxD3 Input Receive data input 0 to 3 Transmit data pins TxD0 to TxD3 Output Transmit data output Request to send pin RTS3 I O Request to send 3 Clear to send pin CTS3 I O Clear to send ...

Page 731: ... FIFO data count register_0 SCFDR_0 R H 0000 H FFFE801C 16 Serial port register_0 SCSPTR_0 R W H 0050 H FFFE8020 16 Line status register_0 SCLSR_0 R W 2 H 0000 H FFFE8024 16 0 Serial extension mode register_0 SCEMR_0 R W H 0000 H FFFE8028 16 Serial mode register_1 SCSMR_1 R W H 0000 H FFFE8800 16 Bit rate register_1 SCBRR_1 R W H FF H FFFE8804 8 Serial control register_1 SCSCR_1 R W H 0000 H FFFE8...

Page 732: ... 0000 H FFFE9024 16 2 Serial extension mode register_2 SCEMR_2 R W H 0000 H FFFE9028 16 Serial mode register_3 SCSMR_3 R W H 0000 H FFFE9800 16 Bit rate register_3 SCBRR_3 R W H FF H FFFE9804 8 Serial control register_3 SCSCR_3 R W H 0000 H FFFE9808 16 Transmit FIFO data register_3 SCFTDR_3 W Undefined H FFFE980C 8 Serial status register_3 SCFSR_3 R W 1 H 0060 H FFFE9810 16 Receive FIFO data regis...

Page 733: ...r write to SCRSR directly 7 6 5 4 3 2 1 0 Bit Initial value R W 15 3 2 Receive FIFO Data Register SCFRDR SCFRDR is a 16 byte FIFO register that stores serial receive data The SCIF completes the reception of one byte of serial data by moving the received data from the receive shift register SCRSR into SCFRDR for storage Continuous reception is possible until 16 bytes are stored The CPU can read but...

Page 734: ... cannot read from or write to SCTSR directly 7 6 5 4 3 2 1 0 Bit Initial value R W 15 3 4 Transmit FIFO Data Register SCFTDR SCFTDR is a 16 byte FIFO register that stores data for serial transmission When the SCIF detects that the transmit shift register SCTSR is empty it moves transmit data written in the SCFTDR into SCTSR and starts serial transmission Continuous serial transmission is performed...

Page 735: ...l value R W C A CHR PE O E STOP CKS 1 0 Bit Bit Name Initial Value R W Description 15 to 8 All 0 R Reserved These bits are always read as 0 The write value should always be 0 7 C A 0 R W Communication Mode Selects whether the SCIF operates in asynchronous or clock synchronous mode 0 Asynchronous mode 1 Clock synchronous mode 6 CHR 0 R W Character Length Selects 7 bit or 8 bit data length in asynch...

Page 736: ...ven or odd parity when parity bits are added and checked The O E setting is used only in asynchronous mode and only when the parity enable bit PE is set to 1 to enable parity addition and checking The O E setting is ignored in clock synchronous mode or in asynchronous mode when parity addition and checking is disabled 0 Even parity 1 1 Odd parity 2 Notes 1 If even parity is selected the parity bit...

Page 737: ...1 it is treated as a stop bit but if the second stop bit is 0 it is treated as the start bit of the next incoming character 0 One stop bit When transmitting a single 1 bit is added at the end of each transmitted character 1 Two stop bits When transmitting two 1 bits are added at the end of each transmitted character 2 0 R Reserved This bit is always read as 0 The write value should always be 0 1 0...

Page 738: ...uld always be 0 7 TIE 0 R W Transmit Interrupt Enable Enables or disables the transmit FIFO data empty interrupt TXI requested when the serial transmit data is transferred from the transmit FIFO data register SCFTDR to the transmit shift register SCTSR when the quantity of data in the transmit FIFO register becomes less than the specified number of transmission triggers and when the TDFE flag in t...

Page 739: ...ror interrupt ERI and break interrupt BRI requests are disabled 1 Receive FIFO data full interrupt RXI receive error interrupt ERI and break interrupt BRI requests are enabled Note RXI interrupt requests can be cleared by reading the DR or RDF flag after it has been set to 1 then clearing the flag to 0 or by clearing RIE to 0 ERI or BRI interrupt requests can be cleared by reading the ER BR or ORE...

Page 740: ...t in SCSMR and SCFCR and reset the receive FIFO before setting RE to 1 3 REIE 0 R W Receive Error Interrupt Enable Enables or disables the receive error ERI interrupts and break BRI interrupts The setting of REIE bit is valid only when RIE bit is set to 0 0 Receive error interrupt ERI and break interrupt BRI requests are disabled 1 Receive error interrupt ERI and break interrupt BRI requests are e...

Page 741: ...erial clock output is set in clock synchronous mode set the C A bit in SCSMR to 1 and then set CKE 1 0 Asynchronous mode 00 Internal clock SCK pin used for input pin input signal is ignored 01 Internal clock SCK pin used for clock output The output clock frequency is either 16 or 8 times the bit rate 10 External clock SCK pin used for clock input The input clock frequency is either 16 or 8 times t...

Page 742: ...R R R R W R W R W R W R R R W R W Bit Initial value R W Note Only 0 can be written to clear the flag after 1 is read PER 3 0 FER 3 0 ER TEND TDFE BRK FER PER RDF DR Bit Bit Name Initial Value R W Description 15 to 12 PER 3 0 0000 R Number of Parity Errors Indicate the quantity of data including a parity error in the receive data stored in the receive FIFO data register SCFRDR The value indicated b...

Page 743: ...tions ER is set to 1 when the stop bit is 0 after checking whether or not the last stop bit of the received data is 1 at the end of one data receive operation 2 ER is set to 1 when the total number of 1s in the receive data plus parity bit does not match the even odd parity specified by the O E bit in SCSMR Notes 1 Clearing the RE bit to 0 in SCSCR does not affect the ER bit which retains its prev...

Page 744: ...ress Clearing condition TEND is cleared to 0 when 0 is written after 1 is read from TEND after transmit data is written in SCFTDR 1 End of transmission Setting conditions TEND is set to 1 when the chip is a power on reset TEND is set to 1 when TE is cleared to 0 in the serial control register SCSCR TEND is set to 1 when SCFTDR does not contain receive data when the last bit of a one byte serial ch...

Page 745: ...fied transmission trigger number is written to SCFTDR after 1 is read from TDFE and then 0 is written TDFE is cleared to 0 when DMAC is activated by transmit FIFO data empty interrupt TXI and write data exceeding the specified transmission trigger number to SCFTDR 1 The quantity of transmit data in SCFTDR is less than or equal to the specified transmission trigger number Setting conditions TDFE is...

Page 746: ...ace 0 in the subsequent receive data Note When a break is detected transfer of the receive data H 00 to SCFRDR stops after detection When the break ends and the receive signal becomes mark 1 the transfer of receive data resumes 3 FER 0 R Framing Error Indication Indicates a framing error in the data read from the next receive FIFO data register SCFRDR in asynchronous mode 0 No receive framing erro...

Page 747: ...e FIFO data register SCFRDR in asynchronous mode 0 No receive parity error occurred in the next data read from SCFRDR Clearing conditions PER is cleared to 0 when the chip undergoes a power on reset PER is cleared to 0 when no parity error is present in the next data read from SCFRDR 1 A receive parity error occurred in the next data read from SCFRDR Setting condition PER is set to 1 when a parity...

Page 748: ...eceive data in SCFRDR becomes less than the specified receive trigger number after 1 is read from RDF and then 0 is written RDF is cleared to 0 when DMAC is activated by receive FIFO data full interrupt RXI and read SCFRDR until the quantity of receive data in SCFRDR becomes less than the specified receive trigger number 1 The quantity of receive data in SCFRDR is more than the specified receive t...

Page 749: ...ins in SCFRDR after receiving ended normally Clearing conditions DR is cleared to 0 when the chip undergoes a power on reset DR is cleared to 0 when all receive data are read after 1 is read from DR and then 0 is written DR is cleared to 0 when all receive data are read after DMAC is activated by receive FIFO data full interrupt RXI 1 Next receive data has not been received Setting condition DR is...

Page 750: ...different values can be set in three channels 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W Bit Initial value R W The SCBRR setting is calculated as follows Asynchronous mode N N N N 106 1 Operation on a base clock with a frequency of 16 times the bit rate 106 1 Operation on a base clock with a frequency of 8 times the bit rate 106 1 Operation on a base clock with a frequency of ...

Page 751: ... CKS 0 0 Pφ 0 0 1 Pφ 4 0 1 2 Pφ 16 1 0 3 Pφ 64 1 1 The bit rate error in asynchronous mode is given by the following formula Error Error Error Error 1 1 1 1 100 Operation on a base clock with a frequency of 16 times the bit rate 100 Operation on a base clock with a frequency of 8 times the bit rate 100 Operation on a base clock with a frequency of 16 times the bit rate 100 Operation on a base cloc...

Page 752: ...nd SCBRR Settings Asynchronous Mode BGDM 0 ABCS 0 1 Pφ MHz 8 9 8304 10 12 Bit Rate bit s n N Error n N Error n N Error n N Error 110 2 141 0 03 2 174 0 26 2 177 0 25 2 212 0 03 150 2 103 0 16 2 127 0 00 2 129 0 16 2 155 0 16 300 1 207 0 16 1 255 0 00 2 64 0 16 2 77 0 16 600 1 103 0 16 1 127 0 00 1 129 0 16 1 155 0 16 1200 0 207 0 16 0 255 0 00 1 64 0 16 1 77 0 16 2400 0 103 0 16 0 127 0 00 0 129 0...

Page 753: ...4 0 70 3 70 0 03 3 86 0 31 150 2 159 0 00 2 191 0 00 2 207 0 16 2 255 0 00 300 2 79 0 00 2 95 0 00 2 103 0 16 2 127 0 00 600 1 159 0 00 1 191 0 00 1 207 0 16 1 255 0 00 1200 1 79 0 00 1 95 0 00 1 103 0 16 1 127 0 00 2400 0 159 0 00 0 191 0 00 0 207 0 16 0 255 0 00 4800 0 79 0 00 0 95 0 00 0 103 0 16 0 127 0 00 9600 0 39 0 00 0 47 0 00 0 51 0 16 0 63 0 00 19200 0 19 0 00 0 23 0 00 0 25 0 16 0 31 0 ...

Page 754: ... 44 3 108 0 08 3 126 0 31 150 3 64 0 16 3 77 0 16 3 79 0 00 3 92 0 46 300 2 129 0 16 2 155 0 16 2 159 0 00 2 186 0 08 600 2 64 0 16 2 77 0 16 2 79 0 00 2 92 0 46 1200 1 129 0 16 1 155 0 16 1 159 0 00 1 186 0 08 2400 1 64 0 16 1 77 0 16 1 79 0 00 1 92 0 46 4800 0 129 0 16 0 155 0 16 0 159 0 00 0 186 0 08 9600 0 64 0 16 0 77 0 16 0 79 0 00 0 92 0 46 19200 0 32 1 36 0 38 0 16 0 39 0 00 0 46 0 61 3125...

Page 755: ... MHz 30 33 Bit Rate bit s n N Error n N Error 110 3 132 0 13 3 145 0 33 150 3 97 0 35 3 106 0 39 300 2 194 0 16 2 214 0 07 600 2 97 0 35 2 106 0 39 1200 1 194 0 16 1 214 0 07 2400 1 97 0 35 1 106 0 39 4800 0 194 1 36 0 214 0 07 9600 0 97 0 35 0 106 0 39 19200 0 48 0 35 0 53 0 54 31250 0 29 0 00 0 32 0 00 38400 0 23 1 73 0 26 0 54 Note Settings with an error of 1 or less are recommended ...

Page 756: ...9 500 2 249 3 124 3 223 3 233 3 255 1 k 2 124 2 249 3 111 3 116 3 125 2 5 k 1 199 2 99 2 178 2 187 2 200 5 k 1 99 1 199 2 89 2 93 2 100 10 k 0 199 1 99 1 178 1 187 1 200 25 k 0 79 0 159 1 71 1 74 1 80 50 k 0 39 0 79 0 143 0 149 0 160 100 k 0 19 0 39 0 71 0 74 0 80 250 k 0 7 0 15 29 0 31 500 k 0 3 0 7 14 0 15 1 M 0 1 0 3 0 7 2 M 0 0 0 1 Legend Blank No setting possible Setting possible but error oc...

Page 757: ...k input is used when tScyc 12tpcyc Note Make sure that the electrical characteristics of this LSI and that of a connected LSI are satisfied Table 15 6 Maximum Bit Rates for Various Frequencies with Baud Rate Generator Asynchronous Mode Settings Pφ MHz BGDM ABCS n N Maximum Bit Rate bits s 0 0 0 250000 0 1 0 0 500000 0 0 0 500000 8 1 1 0 0 1000000 0 0 0 307200 0 1 0 0 614400 0 0 0 614400 9 8304 1 1...

Page 758: ...800 19 6608 1 1 0 0 2457600 0 0 0 625000 0 1 0 0 1250000 0 0 0 1250000 20 1 1 0 0 2500000 0 0 0 750000 0 1 0 0 1500000 0 0 0 1500000 24 1 1 0 0 3000000 0 0 0 768000 0 1 0 0 1536000 0 0 0 1536000 24 576 1 1 0 0 3072000 0 0 0 896875 0 1 0 0 1793750 0 0 0 1793750 28 7 1 1 0 0 3587500 0 0 0 937500 0 1 0 0 1875000 0 0 0 1875000 30 1 1 0 0 3750000 0 0 0 1031250 0 1 0 0 2062500 0 0 0 2062500 33 1 1 0 0 4...

Page 759: ...rnal Input Clock MHz ABCS Maximum Bit Rate bits s 0 125000 8 2 0000 1 250000 0 153600 9 8304 2 4576 1 307200 0 187500 12 3 0000 1 375000 0 230400 14 7456 3 6864 1 460800 0 250000 16 4 0000 1 500000 0 307200 19 6608 4 9152 1 614400 0 312500 20 5 0000 1 625000 0 375000 24 6 0000 1 750000 0 384000 24 576 6 1440 1 768000 0 448436 28 7 4 9152 1 896872 0 468750 30 7 5000 1 937500 0 515625 33 8 2500 1 10...

Page 760: ... 15 3 9 FIFO Control Register SCFCR SCFCR resets the quantity of data in the transmit and receive FIFO data registers sets the trigger data quantity and contains an enable bit for loop back testing SCFCR can always be read and written to by the CPU 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W RSTRG...

Page 761: ... 12 111 14 Receive FIFO Data Trigger Set the quantity of receive data which sets the receive data full RDF flag in the serial status register SCFSR The RDF flag is set to 1 when the quantity of receive data stored in the receive FIFO register SCFRDR is increased more than the set trigger number shown below Asynchronous mode Clock synchronous mode 00 1 01 4 10 8 11 14 00 1 01 2 10 8 11 14 7 6 RTRG ...

Page 762: ...FE flag is set to 1 3 MCE 0 R W Modem Control Enable Enables modem control signals CTS and RTS For channels 0 to 2 in clock synchronous mode MCE bit should always be 0 0 Modem signal disabled 1 Modem signal enabled Note CTS is fixed at active 0 regardless of the input value and RTS is also fixed at 0 2 TFRST 0 R W Transmit FIFO Data Register Reset Disables the transmit data in the transmit FIFO da...

Page 763: ...TDR with the upper 8 bits and the quantity of receive data in SCFRDR with the lower 8 bits SCFDR can always be read by the CPU 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R Bit Initial value R W T 4 0 R 4 0 Bit Bit Name Initial Value R W Description 15 to 13 All 0 R Reserved These bits are always read as 0 The write value should always be 0 1...

Page 764: ...it Initial value R W RTSIO RTSDT CTSIO CTSDT SCKIO SCKDT SPB2IOSPB2DT Bit Bit Name Initial Value R W Description 15 to 8 All 0 R Reserved These bits are always read as 0 The write value should always be 0 7 RTSIO 0 R W RTS Port Input Output Indicates input or output of the serial port RTS pin When the RTS pin is actually used as a port outputting the RTSDT bit value the MCE bit in SCFCR should be ...

Page 765: ... read from the CTSDT bit regardless of the CTSIO bit setting However CTS input output must be set in the PFC 0 Input output data is low level 1 Input output data is high level 3 SCKIO 0 R W SCK Port Input Output Indicates input or output of the serial port SCK pin When the SCK pin is actually used as a port outputting the SCKDT bit value the CKE 1 0 bits in SCSCR should be cleared to 0 0 SCKDT bit...

Page 766: ...be cleared to 0 0 SPB2DT bit value not output to TxD pin 1 SPB2DT bit value output to TxD pin 0 SPB2DT 0 R W Serial Port Break Data Indicates the input data of the RxD pin and the output data of the TxD pin used as serial ports Input output is specified by the SPB2IO bit When the TxD pin is set to output the SPB2DT bit value is output to the TxD pin The RxD pin status is read from the SPB2DT bit r...

Page 767: ...ad as 0 The write value should always be 0 0 ORER 0 R W Overrun Error Indicates the occurrence of an overrun error 0 Receiving is in progress or has ended normally 1 Clearing conditions ORER is cleared to 0 when the chip is a power on reset ORER is cleared to 0 when 0 is written after 1 is read from ORER 1 An overrun error has occurred 2 Setting condition ORER is set to 1 when the next serial rece...

Page 768: ...s 0 The write value should always be 0 7 BGDM 0 R W Baud Rate Generator Double Speed Mode When the BGDM bit is set to 1 the baud rate generator in the SCIF operates in double speed mode This bit is valid only when asynchronous mode is selected by setting the C A bit in SCSMR to 0 and an internal clock is selected as a clock source and the SCK pin is set as an input pin by setting the CKE 1 0 bits ...

Page 769: ...s selected by the combination of the CKE1 and CKE0 bits in the serial control register SCSCR as shown in table 15 10 1 Asynchronous Mode Data length is selectable 7 or 8 bits Parity bit is selectable So is the stop bit length 1 or 2 bits The combination of the preceding selections constitutes the communication format and character length In receiving it is possible to detect framing errors parity ...

Page 770: ... chip baud rate generator and outputs this clock to external devices as the synchronous clock When an external clock is selected the SCIF operates on the input external synchronous clock not using the on chip baud rate generator Table 15 9 SCSMR Settings and SCIF Communication Formats SCSMR Settings SCIF Communication Format Bit 7 C A Bit 6 CHR Bit 5 PE Bit 3 STOP Mode Data Length Parity Bit Stop ...

Page 771: ...rnal Outputs a clock with a frequency 16 8 times the bit rate 10 External Inputs a clock with frequency 16 8 times the bit rate 0 11 Asynchronous Setting prohibited 0x Internal Outputs the serial clock 10 External Inputs the serial clock 1 11 Clock synchronous Setting prohibited Legend x Don t care Note When using the baud rate generator in double speed mode BGMD 1 select asynchronous mode by sett...

Page 772: ... communication the communication line is normally held in the mark high state The SCIF monitors the line and starts serial communication when the line goes to the space low state indicating a start bit One serial character consists of a start bit low data LSB first parity bit high or low and stop bit high in that order When receiving in asynchronous mode the SCIF synchronizes at the falling edge o...

Page 773: ... mode register SCSMR Table 15 11 Serial Communication Formats Asynchronous Mode SCSMR Bits Serial Transmit Receive Format and Frame Length CHR PE STOP 1 2 3 4 5 6 7 8 9 10 11 12 0 0 0 START 8 bit data STOP 0 0 1 START 8 bit data STOP STOP 0 1 0 START 8 bit data P STOP 0 1 1 START 8 bit data P STOP STOP 1 0 0 START 7 bit data STOP 1 0 1 START 7 bit data STOP STOP 1 1 0 START 7 bit data P STOP 1 1 1...

Page 774: ...ialization Asynchronous Mode Before transmitting or receiving clear the TE and RE bits to 0 in the serial control register SCSCR then initialize the SCIF as follows When changing the operation mode or the communication format always clear the TE and RE bits to 0 before following the procedure given below Clearing TE to 0 initializes the transmit shift register SCTSR Clearing TE and RE to 0 however...

Page 775: ...d RE bits in SCSCR to 1 and set the TIE RIE and REIE bits End of initialization Set the clock selection in SCSCR Be sure to clear bits TIE RIE TE and RE to 0 Set the data transfer format in SCSMR Write a value corresponding to the bit rate into SCBRR Not necessary if an external clock is used Sets PFC for external pins used Set as RxD input at receiving and TxD at transmission However no setting f...

Page 776: ...transmit data write Read SCFSR and check that the TDFE flag is set to 1 then write transmit data to SCFTDR and read 1 from the TDFE and TEND flags then clear to 0 The quantity of transmit data that can be written is 16 transmit trigger set number 2 Serial transmission continuation procedure To continue serial transmission read 1 from the TDFE flag to confirm that writing is possible then write dat...

Page 777: ...data bytes in SCFTDR falls below the transmit trigger number set in the FIFO control register SCFCR the TDFE flag is set If the TIE bit in the serial control register SCSR is set to 1 at this time a transmit FIFO data empty interrupt TXI request is generated The serial transmit data is sent from the TxD pin in the following order A Start bit One bit 0 is output B Transmit data 8 bit or 7 bit data ...

Page 778: ...errupt request Figure 15 5 Example of Transmit Operation 8 Bit Data Parity 1 Stop Bit 4 When modem control is enabled in channel 3 transmission can be stopped and restarted in accordance with the CTS input value When CTS is set to 1 if transmission is in progress the line goes to the mark state after transmission of one frame When CTS is set to 0 the next transmit data is output starting from the ...

Page 779: ... SCFSR and the ORER flag in SCLSR to identify any error perform the appropriate error handling then clear the DR ER BRK and ORER flags to 0 In the case of a framing error a break can also be detected by reading the value of the RxD pin 2 SCIF status check and receive data read Read SCFSR and check that RDF flag 1 then read the receive data in SCFRDR read 1 from the RDF flag and then clear the RDF ...

Page 780: ... ORER 1 Yes No No No Whether a framing error or parity error has occurred in the receive data that is to be read from the receive FIFO data register SCFRDR can be ascertained from the FER and PER bits in the serial status register SCFSR When a break signal is received receive data is not transferred to SCFRDR while the BRK flag is set However note that the last data in SCFRDR is H 00 and the break...

Page 781: ...e transferred from the receive shift register SCRSR to SCFRDR C Overrun check The SCIF checks that the ORER flag is 0 indicating that the overrun error has not occurred D Break check The SCIF checks that the BRK flag is 0 indicating that the break state is not set If all the above checks are passed the receive data is stored in SCFRDR Note When a parity error or a framing error occurs reception is...

Page 782: ...pt handler ERI interrupt request generated by receive error Idle state mark state Figure 15 9 Example of SCIF Receive Operation 8 Bit Data Parity 1 Stop Bit 5 When modem control is enabled in channel 3 the RTS signal is output when SCFRDR is empty When RTS is 0 reception is possible When RTS is 1 this indicates that SCFRDR exceeds the number set for the RTS output active trigger Figure 15 10 shows...

Page 783: ...igure 15 11 shows the general format in clock synchronous serial communication Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 LSB MSB Don t care Don t care One unit of transfer data character or frame Serial data Serial clock Note High except in continuous transfer Figure 15 11 Data Format in Clock Synchronous Communication In clock synchronous serial communication each data bit is output on the ...

Page 784: ...nsmitted or received character When the SCIF is not transmitting or receiving the clock signal remains in the high state When only receiving the clock signal outputs while the RE bit of SCSCR is 1 and the number of data in receive FIFO is more than the receive FIFO data trigger number 3 Transmitting and Receiving Data SCIF Initialization Clock Synchronous Mode Before transmitting receiving or chan...

Page 785: ...to 1 and set TIE RIE and REIE bits End of initialization Leave the TE and RE bits cleared to 0 until the initialization almost ends Be sure to clear the TIE RIE TE and RE bits to 0 Set the data transfer format in SCSMR Set CKE 1 0 Write a value corresponding to the bit rate into SCBRR This is not necessary if an external clock is used Sets PFC for external pins used Set as RxD input at receiving a...

Page 786: ...t data to SCFTDR and clear TDFE flag in SCFSR to 0 All data transmitted Read TEND flag in SCFSR TEND 1 Clear TE bit in SCSCR to 0 End of transmission No Yes No Yes No Yes 1 SCIF status check and transmit data write Read SCFSR and check that the TDFE flag is set to 1 then write transmit data to SCFTDR and clear the TDFE flag to 0 2 Serial transmission continuation procedure To continue serial trans...

Page 787: ...trol register SCSR is set to 1 at this time a transmit FIFO data empty interrupt TXI request is generated If clock output mode is selected the SCIF outputs eight synchronous clock pulses If an external clock source is selected the SCIF outputs data in synchronization with the input clock Data is output from the TxD pin in order from the LSB bit 0 to the MSB bit 7 3 The SCIF checks the SCFTDR trans...

Page 788: ...the ORER flag to 0 Reception cannot be resumed while the ORER flag is set to 1 2 SCIF status check and receive data read Read SCFSR and check that RDF 1 then read the receive data in SCFRDR and clear the RDF flag to 0 The transition of the RDF flag from 0 to 1 can also be identified by a receive FIFO data full interrupt RXI 3 Serial reception continuation procedure To continue serial reception rea...

Page 789: ...rrun error is detected further reception is prevented 3 After setting RDF to 1 if the receive FIFO data full interrupt enable bit RIE is set to 1 in SCSCR the SCIF requests a receive data full interrupt RXI If the ORER bit is set to 1 and the receive data full interrupt enable bit RIE or the receive error interrupt enable bit REIE in SCSCR is also set to 1 the SCIF requests a break interrupt BRI F...

Page 790: ...so be identified by a transmit FIFO data empty interrupt TXI 2 Receive error handling Read the ORER flag in SCLSR to identify any error perform the appropriate error handling then clear the ORER flag to 0 Reception cannot be resumed while the ORER flag is set to 1 3 SCIF status check and receive data read Read SCFSR and check that RDF flag 1 then read the receive data in SCFRDR and clear the RDF f...

Page 791: ... CPU When an RXI request is enabled by the RIE bit and the RDF flag or the DR flag in SCFSR is set to 1 an RXI interrupt request is generated The DMAC can be activated and data transfer performed by this RXI interrupt request At this time an interrupt request is not sent to the CPU The RXI interrupt request caused by the DR flag is generated only in asynchronous mode When the RIE bit is set to 0 a...

Page 792: ...ains more than the transmit trigger number of transmit data bytes The number of transmit data bytes in SCFTDR can be found from the upper 8 bits of the FIFO data count register SCFDR 15 6 2 SCFRDR Reading and RDF Flag The RDF flag in the serial status register SCFSR is set when the number of receive data bytes in the receive FIFO data register SCFRDR has become equal to or greater than the receive...

Page 793: ...t register SCSPTR This feature can be used to send a break signal Until TE bit is set to 1 enabling transmission after initializing the TxD pin does not work During the period mark status is performed by the SPB2DT bit Therefore the SPB2IO and SPB2DT bits should be set to 1 high level output To send a break signal during serial transmission clear the SPB2DT bit to 0 designating low level then clea...

Page 794: ...Mode Operation on a Base Clock with a Frequency 16 Times the Bit Rate The receive margin in asynchronous mode can therefore be expressed as shown in equation 1 Equation 1 M 0 5 L 0 5 F 1 F 100 1 2N D 0 5 N Where M Receive margin N Ratio of clock frequency to bit rate N 16 or 8 D Clock duty D 0 to 1 0 L Frame length L 9 to 12 F Absolute deviation of clock frequency From equation 1 if F 0 D 0 5 and ...

Page 795: ...is used receive margin is decreased as calculated using equation 1 in section 15 6 6 Receive Data Sampling Timing and Receive Margin Asynchronous Mode If the desired bit rate can be set simply by setting SCBRR and the CKS1and CKS0 bits in SCSMR it is recommended to use the base clock frequency within a bit period 16 times the bit rate by setting the ABCS bit in SCEMR to 0 If an internal clock is s...

Page 796: ...Section 15 Serial Communication Interface with FIFO SCIF Rev 0 50 May 18 2006 Page 766 of 1588 REJ09B0313 0050 ...

Page 797: ...e and bidirectional mode Synchronous serial communication with devices with different clock polarity and clock phase Choice of 8 16 32 bit width of transmit receive data Full duplex communication capability The shift register is incorporated enabling transmission and reception to be executed simultaneously Consecutive serial communication Choice of LSB first or MSB first transfer Choice of a clock...

Page 798: ...Pφ 32 Pφ 64 Pφ 128 Pφ 256 Clock selector Peripheral bus Bus interface SCS SSI Shiftout Shiftin SSOEI SSTXI SSTEI Legend SSCRH SSCRL SSCR2 SSMR SSER SSSR SSTDR0 to SSTDR3 SSRDR0 to SSRDR3 SSTRSR SS control register H SS control register L SS control register 2 SS mode register SS enable register SS status register SS transmit data registers 0 to 3 SS receive data registers 0 to 3 SS shift register ...

Page 799: ...J09B0313 0050 16 2 Input Output Pins Table 16 1 shows the SSU pin configuration Table 16 1 Pin Configuration Channel Symbol I O Function SSCK0 SSCK1 I O SSU clock input output SSI0 SSI1 I O SSU data input output SSO0 SSO1 I O SSU data input output 0 1 SCS0 SCS1 I O SSU chip select input output ...

Page 800: ...0 SSTDR1_0 R W H 00 H FFFE7007 8 SS transmit data register 2_0 SSTDR2_0 R W H 00 H FFFE7008 8 16 SS transmit data register 3_0 SSTDR3_0 R W H 00 H FFFE7009 8 SS receive data register 0_0 SSRDR0_0 R H 00 H FFFE700A 8 16 SS receive data register 1_0 SSRDR1_0 R H 00 H FFFE700B 8 SS receive data register 2_0 SSRDR2_0 R H 00 H FFFE700C 8 16 0 SS receive data register 3_0 SSRDR3_0 R H 00 H FFFE700D 8 SS...

Page 801: ...R R W R W MSS BIDE SOL SOLP CSS 1 0 Bit Bit Name Initial Value R W Description 7 MSS 0 R W Master Slave Device Select Selects that this module is used in master mode or slave mode When master mode is selected transfer clocks are output from the SSCK pin When the CE bit in SSSR is set this bit is automatically cleared 0 Slave mode is selected 1 Master mode is selected 6 BIDE 0 R W Bidirectional Mod...

Page 802: ... data output is changed to low 1 Serial data output is changed to high 3 SOLP 1 R W SOL Bit Write Protect When changing the output level of serial data set the SOL bit to 1 or clear the SOL bit to 0 after clearing the SOLP bit to 0 using the MOV instruction 0 Output level can be changed by the SOL bit 1 Output level cannot be changed by the SOL bit This bit is always read as 1 2 1 R Reserved This ...

Page 803: ...the register is accessed 1 Flags are cleared when DMAC transfer is completed 6 SSUMS 0 R W Selects transfer mode from SSU mode and clock synchronous mode 0 SSU mode 1 Clock synchronous mode 5 SRES 0 R W Software Reset Setting this bit to 1 forcibly resets the SSU internal sequencer After that this bit is automatically cleared The ORER TEND TDRE RDRF and CE bits in SSSR and the TE and RE bits in SS...

Page 804: ...al Value R W Description 7 MLS 0 R W MSB First LSB First Select Selects that the serial data is transmitted in MSB first or LSB first 0 LSB first 1 MSB first 6 CPOS 0 R W Clock Polarity Select Selects the SSCK clock polarity 0 High output in idle mode and low output in active mode 1 Low output in idle mode and high output in active mode 5 CPHS 0 R W Clock Phase Select Only for SSU Mode Selects the...

Page 805: ...ER SSER performs transfer receive control of synchronous serial communication and setting of interrupt enable Bit Initial value R W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R W R W R R R W R W R W R W TE RE TEIE TIE RIE CEIE Bit Bit Name Initial Value R W Description 7 TE 0 R W Transmit Enable When this bit is set to 1 transmission is enabled 6 RE 0 R W Receive Enable When this bit is set to 1 reception is...

Page 806: ... a status flag register for interrupts Bit Initial value R W 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 0 R R W R R R W R W R W R W ORER TEND TDRE RDRF CE Bit Bit Name Initial Value R W Description 7 0 R Reserved This bit is always read as 0 The write value should always be 0 6 ORER 0 R W Overrun Error If the next data is received while RDRF 1 an overrun error occurs indicating abnormal termination SSRDR store...

Page 807: ...the last bit of transmit data is transmitted while the TENDSTS bit in SSCR2 is set to 1 and the TDRE bit is set to 1 Clearing conditions When writing 0 after reading TEND 1 When writing data to SSTDR 2 TDRE 1 R W Transmit Data Empty Indicates whether or not SSTDR contains transmit data Setting conditions When the TE bit in SSER is 0 When data is transferred from SSTDR to SSTRSR and SSTDR is ready ...

Page 808: ...ndicates that a conflict error has occurred when 0 is externally input to the SCS pin with SSUMS 0 SSU mode and MSS 1 master mode If the SCS pin level changes to 1 with SSUMS 0 SSU mode and MSS 0 slave mode an incomplete error occurs because it is determined that a master device has terminated the transfer Data reception does not continue while the CE bit is set to 1 Serial transmission also does ...

Page 809: ...the serial data output pin is used as a TTL or an NMOS open drain output Pins to output serial data differ according to the register setting For details section 16 4 3 Relationship between Data Input Output Pins and Shift Register 0 TTL output 1 NMOS open drain output 6 SSCKOS 0 R W SSCK Pin Open Drain Select Selects whether the SSCK pin is used as a TTL or an NMOS open drain output 0 TTL output 1...

Page 810: ...to SSTDR3 SSTDR is an 8 bit register that stores transmit data When 8 bit data length is selected by bits DATS1 and DATS0 in SSCRL SSTDR0 is valid When 16 bit data length is selected SSTDR0 and SSTDR1 are valid When 32 bit data length is selected SSTDR0 to SSTDR3 are valid The SSTDR that has not been enabled must not be accessed When the SSU detects that SSTRSR is empty it transfers the transmit d...

Page 811: ...id When 16 bit data length is selected SSRDR0 and SSRDR1 are valid When 32 bit data length is selected SSRDR0 to SSRDR3 are valid The SSRDR that has not been enabled must not be accessed When the SSU has received 1 byte data it transfers the received serial data from SSTRSR to SSRDR where it is stored After this SSTRSR is ready for reception Since SSTRSR and SSRDR function as a double buffer in th...

Page 812: ...ansmits and receives serial data When data is transferred from SSTDR to SSTRSR bit 0 of transmit data is bit 0 in the SSTDR contents MLS 0 LSB first communication and is bit 7 in the SSTDR contents MLS 1 MSB first communication The SSU transfers data from the LSB bit 0 in SSTRSR to the SSO pin to perform serial data transmission In reception the SSU sets serial data that has been input via the SSI...

Page 813: ...s an input pin 16 4 2 Relationship of Clock Phase Polarity and Data The relationship of clock phase polarity and transfer data depends on the combination of the CPOS and CPHS bits in SSMR when the value of the SSUMS bit in SSCRL is 0 Figure 16 2 shows the relationship When SSUMS 1 the CPHS setting is invalid although the CPOS setting is valid Setting the MLS bit in SSMR selects either MSB first or...

Page 814: ... figure 16 3 1 The SSU transmits serial data from the SSI pin and receives serial data from the SSO pin when operating with BIDE 0 and MSS 0 standard slave mode see figure 16 3 2 The SSU transmits and receives serial data from the SSO pin regardless of master or slave mode when operating with BIDE 1 bidirectional mode see figures 16 3 3 and 4 However even if both the TE and RE bits are set to 1 tr...

Page 815: ...1 When SSUMS 0 BIDE 0 standard mode MSS 1 TE 1 and RE 1 SSCK Shift register SSTRSR SSO SSI SSCK Shift register SSTRSR SSO SSI 2 When SSUMS 0 BIDE 0 standard mode MSS 0 TE 1 and RE 1 4 When SSUMS 0 BIDE 1 bidirectional mode MSS 0 and either TE or RE 1 3 When SSUMS 0 BIDE 1 bidirectional mode MSS 1 and either TE or RE 1 5 When SSUMS 1 and MSS 1 6 When SSUMS 1 and MSS 0 Figure 16 3 Relationship betwe...

Page 816: ...ommunication modes and input output pin functions are shown in tables 16 5 to 16 7 Table 16 5 Communication Modes and Pin States of SSI and SSO Pins Register Setting Pin State Communication Mode SSUMS BIDE MSS TE RE SSI SSO 0 0 0 0 1 Input SSU communication mode 1 0 Output 1 Output Input 1 0 1 Input 1 0 Output 1 Input Output 0 1 0 0 1 Input SSU bidirectional communication mode 1 0 Output 1 0 1 Inp...

Page 817: ... 1 0 1 Output 1 0 0 Clock synchronous communication mode 1 Input 1 0 1 Output Legend Not used as SSU pin but can be used as an I O port Table 16 7 Communication Modes and Pin States of SCS Pin Register Setting Pin State Communication Mode SSUMS MSS CSS1 CSS0 SCS 0 0 x x Input SSU communication mode 1 0 0 0 1 Input 1 0 Automatic input output 1 1 Output Clock synchronous communication mode 1 x x x L...

Page 818: ... not change the values of the RDRF and ORER bits and SSRDR Those bits retain the previous values Start setting initial values 1 2 3 4 End Set PFC for external pins to be used SSCK SSI SSO and SCS Clear the SSUMS bit in SSCRL to 0 and specify bits DATS1 and DATS0 Specify the MSS BIDE SOL SCKS CSS1 and CSS0 bits in SSCRH Specify the MLS CPOS CPHS CKS2 CKS1 and CKS0 bits in SSMR Specify TEIE TIE RIE ...

Page 819: ...to 1 clears the TDRE bit in SSSR to 0 and the SSTDR contents are transferred to SSTRSR After that the SSU sets the TDRE bit to 1 and starts transmission At this time if the TIE bit in SSER is set to 1 a TXI interrupt is generated When 1 frame data has been transferred with TDRE 0 the SSTDR contents are transferred to SSTRSR to start the next frame transmission When the 8th bit of transmit data has...

Page 820: ...t 7 Bit 0 Bit 7 Bit 0 Bit 7 Bit 0 Bit 7 Bit 0 Bit 7 Bit 0 Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 SSO TDRE TEND LSI operation User operation LSI operation User operation LSI operation User operation TXI interrupt generated TEI interrupt generated TEI interrupt generated TXI interrupt generated Data written to SSTDR0 Data written to SSTDR0 and SSTDR1 Data written to SSTDR0...

Page 821: ...ritten to SSTDR The TDRE bit is automatically cleared to 0 by writing data to SSTDR 4 Procedure for data transmission end To end data transmission confirm that the TEND bit is cleared to 0 After completion of transmitting the last bit clear the TE bit to 0 Note Hatching boxes represent SSU internal operations Initial setting Read the TDRE bit in SSSR TDRE 1 Yes Yes No No No Write transmit data to ...

Page 822: ...the SCS pin and a transfer clock is input to the SSCK pin the SSU receives data in synchronization with the transfer clock When 1 frame data has been received the RDRF bit in SSSR is set to 1 and the receive data is stored in SSRDR At this time if the RIE bit in SSER is set to 1 an RXI interrupt is generated The RDRF bit is automatically cleared to 0 by reading SSRDR When the RDRF bit has been set...

Page 823: ...t 4 Bit 4 Bit 5 Bit 5 Bit 6 Bit 6 Bit 7 Bit 7 LSI operation Dummy read SSRDR0 Dummy read SSRDR0 Read SSRDR0 User operation LSI operation User operation LSI operation User operation SSRDR0 LSB first transmission SSRDR0 MSB first transmission RXI interrupt generated RXI interrupt generated RXI interrupt generated Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit...

Page 824: ...uing single reception wait for time of tSUcyc while the RDRF flag is set to 1 and then read receive data in SSRDR The next single reception starts after reading receive data in SSRDR 5 To complete reception To complete reception read receive data after clearing the RE bit to 0 When reading SSRDR without clearing the RE bit reception is resumed No Yes Yes No Start Initial setting Dummy read SSRDR R...

Page 825: ... reception is performed combining the data transmission and data reception as mentioned above The data transmission reception is started by writing transmit data to SSTDR with TE RE 1 Before switching transmission mode TE 1 or reception mode RE 1 to transmission reception mode TE RE 1 clear the TE and RE bits to 0 When starting the transfer confirm that the TEND RDRF and ORER bits are cleared to 0...

Page 826: ...ate and write transmit data Write transmit data to SSTDR after reading and confirming that the TDRE bit in SSSR is 1 The TDRE bit is automatically cleared to 0 and transmission reception is started by writing data to SSTDR 3 Check the SSU state Read SSSR confirming that the RDRF bit is 1 A change of the RDRF bit from 0 to 1 can be notified by RXI interrupt 4 Receive error processing When a receive...

Page 827: ... pin within the period a conflict error occurs At this time the CE bit in SSSR is set to 1 and the MSS bit is cleared to 0 Note While the CE bit is set to 1 transmission or reception is not resumed Clear the CE bit to 0 before resuming the transmission or reception CE Data written to SSTDR Conflict error detection period Worst time for internally clocking SCS MSS Internal signal for transfer enabl...

Page 828: ...1 clearing the RE bit to 0 does not change the values of the RDRF and ORER bits and SSRDR Those bits retain the previous values Start setting initial values 1 2 3 4 End Set PFC for external pins to be used SSCK SSI SSO and SCS Set the SSUMS bit in SSCRL to 1 and specify bits DATS1 and DATS0 Specify bits MSS and SCKS in SSCRH Specify the CPOS CKS2 CKS1 and CKS0 bits in SSMR Specify the TEIE TIE RIE...

Page 829: ...SU sets the TDRE bit to 1 and starts transmission At this time if the TIE bit in SSER is set to 1 a TXI interrupt is generated When 1 frame data has been transferred with TDRE 0 the SSTDR contents are transferred to SSTRSR to start the next frame transmission When the 8th bit of transmit data has been transferred with TDRE 1 the TEND bit in SSSR is set to 1 and the state is retained At this time i...

Page 830: ...he TDRE bit is automatically cleared to 0 by writing data to SSTDR 4 Procedure for data transmission end To end data transmission confirm that the TEND bit is cleared to 0 After completion of transmitting the last bit clear the TE bit to 0 Note Hatching boxes represent SSU internal operations Initial setting Read the TDRE bit in SSSR TDRE 1 Yes Yes No No No Write transmit data to SSTDR TDRE automa...

Page 831: ...is set to 1 and the receive data is stored in SSRDR At this time if the RIE bit is set to 1 an RXI interrupt is generated The RDRF bit is automatically cleared to 0 by reading SSRDR When the RDRF bit has been set to 1 at the 8th rising edge of the transfer clock the ORER bit in SSSR is set to 1 This indicates that an overrun error OEI has occurred At this time data reception is stopped While the O...

Page 832: ...reception is not resumed 3 To complete reception To complete reception read receive data after clearing the RE bit to 0 When reading SSRDR without clearing the RE bit reception is resumed No Yes Yes No Start Initial setting Read SSSR RDRF 1 ORER 1 Consecutive data reception Read received data in SSRDR RDRF automatically cleared RE 0 Read receive data in SSRDR End reception Overrun error processing...

Page 833: ... reception is performed combining the data transmission and data reception as mentioned above The data transmission reception is started by writing transmit data to SSTDR with TE RE 1 Before switching transmission mode TE 1 or reception mode RE 1 to transmission reception mode TE RE 1 clear the TE and RE bits to 0 When starting the transfer confirm that the TEND RDRF and ORER bits are cleared to 0...

Page 834: ...transmit data Write transmit data to SSTDR after reading and confirming that the TDRE bit in SSSR is 1 The TDRE bit is automatically cleared to 0 and transmission reception is started by writing data to SSTDR 3 Check the SSU state Read SSSR confirming that the RDRF bit is 1 A change of the RDRF bit from 0 to 1 can be notified by RXI interrupt 4 Receive error processing When a receive error occurs ...

Page 835: ...ector address and both a transmit data register empty and a transmit end interrupts are allocated to the SSTXI vector address the interrupt source should be decided by their flags Table 16 8 lists the interrupt sources When an interrupt condition shown in table 16 8 is satisfied an interrupt is requested Clear the interrupt source by CPU or DMAC data transfer Table 16 8 SSU Interrupt Sources Abbre...

Page 836: ... 0050 16 6 Usage Note 16 6 1 Module Standby Mode Setting The SSU operation can be disabled or enabled using the standby control register The initial setting is for SSU operation to be halted Access to registers is enabled by clearing module standby mode For details refer to section 28 Power Down Modes ...

Page 837: ...when receiving Automatic loading of acknowledge bit when transmitting Bit synchronization function In master mode the state of SCL is monitored per bit and the timing is synchronized automatically If transmission reception is not yet possible set the SCL to low until preparations are completed Six interrupt sources Transmit data empty including slave address match transmit end receive data full in...

Page 838: ...sion circuit Arbitration decision circuit Noise canceler Noise filter Output control Output control Transmission reception control circuit I2C bus control register 1 I2C bus control register 2 I2C bus mode register I2C bus status register I2C bus interrupt enable register I2C bus transmit data register I2C bus receive data register I2C bus shift register Slave address register NF2CYC register Lege...

Page 839: ...CL3 I O I 2 C serial clock input output Serial data SDA0 to SDA3 I O I 2 C serial data input output Figure 17 2 shows an example of I O pin connections to external circuits PVcc PVcc SCL in SCL out SCL SDA in SDA out SDA SCL SDA SCL in SCL out SCL SDA in SDA out SDA SCL in SCL out SCL SDA in SDA out SDA Note Turn on off PVcc for the I2C bus power supply and for this LSI simultaneously Master Slave...

Page 840: ...register 1 ICCR1_1 R W H 00 H FFFEE400 8 I 2 C bus control register 2 ICCR2_1 R W H 7D H FFFEE401 8 I 2 C bus mode register ICMR_1 R W H 38 H FFFEE402 8 I 2 C bus interrupt enable register ICIER_1 R W H 00 H FFFEE403 8 I 2 C bus status register ICSR_1 R W H 00 H FFFEE404 8 Slave address register SAR_1 R W H 00 H FFFEE405 8 I 2 C bus transmit data register ICDRT_1 R W H FF H FFFEE406 8 I 2 C bus re...

Page 841: ...er NF2CYC_3 R W H 00 H FFFEEC08 8 17 3 1 I 2 C Bus Control Register 1 ICCR1 ICCR1 is an 8 bit readable writable register that enables or disables the I 2 C bus interface 3 controls transmission or reception and selects master or slave mode transmission or reception and transfer clock frequency in master mode ICCR1 is initialized to H 00 by a power on reset 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R W R W R...

Page 842: ...on is issued in slave receive mode match the slave address set to SAR and the 8th bit is set to 1 TRS is automatically set to 1 If an overrun error occurs in master receive mode with the clocked synchronous serial format MST is cleared and the mode changes to slave receive mode Operating modes are described below according to MST and TRS combination When clocked synchronous serial format is select...

Page 843: ... kHz 298 kHz 317 kHz 397 kHz 1 Pφ 92 181 kHz 217 kHz 272 kHz 290 kHz 362 kHz 1 0 Pφ 100 167 kHz 200 kHz 250 kHz 267 kHz 333 kHz 1 Pφ 108 154 kHz 185 kHz 231 kHz 247 kHz 309 kHz 1 0 0 0 Pφ 176 94 7 kHz 114 kHz 142 kHz 152 kHz 189 kHz 1 Pφ 208 80 1 kHz 96 2 kHz 120 kHz 128 kHz 160 kHz 1 0 Pφ 256 65 1 kHz 78 1 kHz 97 7 kHz 104 kHz 130 kHz 1 Pφ 288 57 9 kHz 69 4 kHz 86 8 kHz 92 6 kHz 116 kHz 1 0 0 Pφ ...

Page 844: ...ead as 0 With the I 2 C bus format this bit is set to 1 when the SDA level changes from high to low under the condition of SCL high assuming that the start condition has been issued This bit is cleared to 0 when the SDA level changes from low to high under the condition of SCL high assuming that the stop condition has been issued Write 1 to BBSY and 0 to SCP to issue a start condition Follow this ...

Page 845: ...ct Controls change of output level of the SDA pin by modifying the SDAO bit To change the output level clear SDAO and SDAOP to 0 or set SDAO to 1 and clear SDAOP to 0 This bit is always read as 1 3 SCLO 1 R SCL Output Level Monitors SCL output level When SCLO is 1 SCL pin outputs high When SCLO is 0 SCL pin outputs low 2 1 R Reserved This bit is always read as 1 The write value should always be 1 ...

Page 846: ...it Bit Name Initial Value R W Description 7 MLS 0 R W MSB First LSB First Select 0 MSB first 1 LSB first Set this bit to 0 when the I 2 C bus format is used 6 0 R Reserved This bit is always read as 0 The write value should always be 0 5 4 All 1 R Reserved These bits are always read as 1 The write value should always be 1 3 BCWP 1 R W BC Write Protect Controls the BC 2 0 modifications When modifyi...

Page 847: ...n B 000 the setting should be made while the SCL pin is low The value returns to B 000 at the end of a data transfer including the acknowledge bit These bits are cleared by a power on reset and in software standby mode and module standby mode These bits are also cleared by setting the IICRST bit of ICCR2 to 1 With the clocked synchronous serial format these bits should not be modified 2 to 0 BC 2 ...

Page 848: ...data empty interrupt request TXI is disabled 1 Transmit data empty interrupt request TXI is enabled 6 TEIE 0 R W Transmit End Interrupt Enable Enables or disables the transmit end interrupt TEI at the rising of the ninth clock while the TDRE bit in ICSR is 1 TEI can be canceled by clearing the TEND bit or the TEIE bit to 0 0 Transmit end interrupt request TEI is disabled 1 Transmit end interrupt r...

Page 849: ...ction interrupt request STPI when the STOP bit in ICSR is set 0 Stop condition detection interrupt request STPI is disabled 1 Stop condition detection interrupt request STPI is enabled 2 ACKE 0 R W Acknowledge Bit Judgment Select 0 The value of the receive acknowledge bit is ignored and continuous transfer is performed 1 If the receive acknowledge bit is 1 continuous transfer is halted 1 ACKBR 0 R...

Page 850: ...y Clearing conditions When 0 is written in TDRE after reading TDRE 1 When data is written to ICDRT Setting conditions When data is transferred from ICDRT to ICDRS and ICDRT becomes empty When TRS is set When the start condition including retransmission is issued When slave mode is changed from receive mode to transmit mode 6 TEND 0 R W Transmit End Clearing conditions When 0 is written in TEND aft...

Page 851: ...receive data is transferred from ICDRS to ICDRR 4 NACKF 0 R W No Acknowledge Detection Flag Clearing condition When 0 is written in NACKF after reading NACKF 1 Setting condition When no acknowledge is detected from the receive device in transmission while the ACKE bit in ICIER is 1 3 STOP 0 R W Stop Condition Detection Flag Clearing condition When 0 is written in STOP after reading STOP 1 Setting ...

Page 852: ...ons If the internal SDA and SDA pin disagree at the rise of SCL in master transmit mode When the SDA pin outputs high in master mode while a start condition is detected When the final bit is received with the clocked synchronous format while RDRF 1 1 AAS 0 R W Slave Address Recognition Flag In slave receive mode this flag is set to 1 if the first frame following a start condition matches bits SVA ...

Page 853: ...W Description 7 to 1 SVA 6 0 0000000 R W Slave Address These bits set a unique address in these bits differing form the addresses of other slave devices connected to the I 2 C bus 0 FS 0 R W Format Select 0 I 2 C bus format is selected 1 Clocked synchronous serial format is selected 17 3 7 I 2 C Bus Transmit Data Register ICDRT ICDRT is an 8 bit readable writable register that stores the transmit ...

Page 854: ...CDRR is a receive only register therefore the CPU cannot write to this register 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 R R R R R R R R Bit Initial value R W 17 3 9 I 2 C Bus Shift Register ICDRS ICDRS is a register that is used to transfer receive data In transmission data is transferred from ICDRT to ICDRS and the data is sent from the SDA pin In reception data is transferred from ICDRS to ICDRR after d...

Page 855: ...l value R W PRS NF2 CYC Bit Bit Name Initial Value R W Description 7 to 2 All 0 R Reserved These bits are always read as 0 The write value should always be 0 1 PRS 0 R W Pulse Width Ratio Select Specifies the ratio of the high level period to the low level period for the SCL signal 0 The ratio of high to low is 0 5 to 0 5 1 The ratio of high to low is about 0 4 to 0 6 0 NF2CYC 0 R W Noise Filterin...

Page 856: ...rmat FS 0 b I2C bus format Start condition retransmission FS 0 n Transfer bit count n 1 to 8 m Transfer frame count m 1 n1 and n2 Transfer bit count n1 and n2 1 to 8 m1 and m2 Transfer frame count m1 and m2 1 Figure 17 3 I 2 C Bus Formats SDA SCL S SLA R W A 9 8 1 7 9 8 1 7 9 8 1 7 DATA A DATA A P Figure 17 4 I 2 C Bus Timing Legend S Start condition The master device drives SDA from high to low w...

Page 857: ...nd R W to ICDRT At this time TDRE is automatically cleared to 0 and data is transferred from ICDRT to ICDRS TDRE is set again 4 When transmission of one byte data is completed while TDRE is 1 TEND in ICSR is set to 1 at the rise of the 9th transmit clock pulse Read the ACKBR bit in ICIER and confirm that the slave device has been selected Then write second byte data to ICDRT When ACKBR is 1 the sl...

Page 858: ...o ICDRT second byte User processing Bit 7 Slave address Address R W Data 1 Data 1 Data 2 Address R W Bit 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Figure 17 5 Master Transmit Mode Operation Timing 1 TDRE TEND ICDRT ICDRS 1 9 2 3 4 5 6 7 8 9 A A A 6 Issue stop condition Clear TEND 7 Set slave receive mode SCL Master output SDA Master output SDA Slave output Bit 7 Bit 6 Data n Data n Bit 5 B...

Page 859: ...ified by ACKBT in ICIER to SDA at the 9th receive clock pulse 3 After the reception of first frame data is completed the RDRF bit in ICSR is set to 1 at the rise of 9th receive clock pulse At this time the receive data is read by reading ICDRR and RDRF is cleared to 0 4 The continuous reception is performed by reading ICDRR every time RDRF is set If 8th receive clock pulse falls after reading ICDR...

Page 860: ...e Master receive mode Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 User processing Data 1 Data 1 Figure 17 7 Master Receive Mode Operation Timing 1 RDRF RCVD ICDRS ICDRR 1 9 2 3 4 5 6 7 8 9 A A A Data n 1 Data n Data n Data n 1 5 Read ICDRR after setting RCVD 6 Issue stop condition 7 Read ICDRR and clear RCVD 8 Set slave receive mode SCL Master output SDA Master output SDA Slave output Bit 7 Bi...

Page 861: ...elect slave receive mode and wait until the slave address matches 2 When the slave address matches in the first frame following detection of the start condition the slave device outputs the level specified by ACKBT in ICIER to SDA at the rise of the 9th clock pulse At this time if the 8th bit data R W is 1 the TRS bit in ICCR1 and the TDRE bit in ICSR are set to 1 and the mode changes to slave tra...

Page 862: ...SCL Master output Slave receive mode Slave transmit mode SDA Master output SDA Slave output SCL Slave output Bit 7 Bit 7 Data 1 Data 1 Data 2 Data 3 Data 2 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 2 Write data to ICDRT data 1 2 Write data to ICDRT data 2 2 Write data to ICDRT data 3 User processing Figure 17 9 Slave Transmit Mode Operation Timing 1 ...

Page 863: ...5 6 7 8 9 TRS ICDRT A A Data n SCL Master output SDA Master output SDA Slave output SCL Slave output Bit 7 Slave transmit mode Slave receive mode Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 3 Clear TEND 5 Clear TDRE 4 Read ICDRR dummy read after clearing TRS User processing Figure 17 10 Slave Transmit Mode Operation Timing 2 ...

Page 864: ... detection of the start condition the slave device outputs the level specified by ACKBT in ICIER to SDA at the rise of the 9th clock pulse At the same time RDRF in ICSR is set to read ICDRR dummy read Since the read data show the slave address and R W it is not used 3 Read ICDRR every time RDRF is set If 8th receive clock pulse falls while RDRF is 1 SCL is fixed low until ICDRR is read The change ...

Page 865: ...format by setting the FS bit in SAR to 1 When the MST bit in ICCR1 is 1 the transfer clock output from SCL is selected When MST is 0 the external clock input is selected 1 Data Transfer Format Figure 17 13 shows the clocked synchronous serial transfer format The transfer data is output from the fall to the fall of the SCL clock and the data at the rising edge of the SCL clock is guaranteed The MLS...

Page 866: ...R1 Initial setting 2 Set the TRS bit in ICCR1 to select the transmit mode Then TDRE in ICSR is set 3 Confirm that TDRE has been set Then write the transmit data to ICDRT The data is transferred from ICDRT to ICDRS and TDRE is set automatically The continuous transmission is performed by writing data to ICDRT every time TDRE is set When changing from transmit mode to receive mode clear TRS while TD...

Page 867: ...byte can be received so the clock is continually output The continuous reception is performed by reading ICDRR every time RDRF is set When the 8th clock is risen while RDRF is 1 the overrun is detected and AL OVE in ICSR is set At this time the previous reception data is retained in ICDRR 4 To stop receiving when MST 1 set RCVD in ICCR1 to 1 then read ICDRR Then SCL is fixed high after receiving t...

Page 868: ... User processing Data 1 Data 1 Data 2 Data 2 Data 3 2 Set MST when outputting the clock 3 Read ICDRR 3 Read ICDRR Figure 17 15 Receive Mode Operation Timing 1 2 3 4 5 6 7 8 000 SCL MST RCVD 111 110 101 100 011 010 001 000 SDA Input Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 BC2 to BC0 2 Set MST 3 Set the RCVD bit after checking if BC2 1 Figure 17 16 Operation Timing For Receiving One Byte MST...

Page 869: ...r SDA input signal is sampled on the peripheral clock When NF2CYC is set to 0 this signal is not passed forward to the next circuit unless the outputs of both latches agree When NF2CYC is set to 1 this signal is not passed forward to the next circuit unless the outputs of three latches agree If they do not agree the previous value is held C Q D C Q D C Q 1 0 D NF2CYC SCL or SDA input signal Intern...

Page 870: ...in ICSR Clear TDRE in ICSR End Write transmit data in ICDRT Transmit mode No Yes TDRE 1 Last byte STOP 1 No No No No No Yes Yes TEND 1 Yes Yes Yes 1 Test the status of the SCL and SDA lines 2 Set master transmit mode 3 Issue the start condition 4 Set the first byte slave address R W of transmit data 5 Wait for 1 byte to be transmitted 6 Test the acknowledge transferred from the specified slave dev...

Page 871: ...mit device 3 Dummy read ICDDR 4 Wait for 1 byte to be received 5 Check whether it is the last receive 1 6 Read the receive data 7 Set acknowledge of the final byte Disable continuous reception RCVD 1 8 Read the final byte 1 of received data 9 Wait for the last byte to be receive 10 Clear the STOP flag 11 Issue the stop condition 12 Wait for the creation of stop condition 13 Read the last byte of r...

Page 872: ...ear TEND in ICSR Clear TRS in ICCR1 to 0 Dummy read ICDRR Clear TDRE in ICSR End 1 Clear the AAS flag 2 Set transmit data for ICDRT except for the last byte 3 Wait for ICDRT empty 4 Set the last byte of transmit data 5 Wait for the last byte to be transmitted 6 Clear the TEND flag 7 Set slave receive mode 8 Dummy read ICDRR to release the SCL 9 Clear the TDRE flag No No Yes TEND 1 1 2 3 4 5 6 7 8 ...

Page 873: ...Clear the AAS flag 2 Set acknowledge to the transmit device 3 Dummy read ICDRR 4 Wait for 1 byte to be received 5 Check whether it is the last receive 1 6 Read the receive data 7 Set acknowledge of the last byte 8 Read the last byte 1 of receive data 9 Wait the last byte to be received 10 Read for the last byte of receive data Note When the size of receive data is only one byte in reception steps ...

Page 874: ... recognition STPI STOP 1 STIE 1 NACK detection Arbitration lost overrun error NAKI NACKF 1 AL 1 NAKIE 1 When the interrupt condition described in table 17 4 is 1 the CPU executes an interrupt exception handling Note that a TXI or RXI interrupt can activate the DMAC if the setting for DMAC activation has been made In such a case an interrupt request is not sent to the CPU Interrupt sources should b...

Page 875: ...municates by bit with synchronization Figure 17 22 shows the timing of the bit synchronous circuit and table 17 5 shows the time when the SCL output changes from low to Hi Z then SCL is monitored SCL VIH Time for monitoring SCL on board SCL monitor timing reference clock Internal SCL Figure 17 22 Bit Synchronous Circuit Timing Table 17 5 Time for Monitoring SCL CKS3 CKS2 Time for Monitoring SCL 1 ...

Page 876: ...Section 17 I2 C Bus Interface 3 IIC3 Rev 0 50 May 18 2006 Page 846 of 1588 REJ09B0313 0050 ...

Page 877: ...ls Operating mode Non compressed mode The non compressed mode supports serial audio streams divided by channels Serves as both a transmitter and a receiver Capable of using serial bus format Asynchronous transfer takes place between the data buffer and the shift register It is possible to select a value as the dividing ratio for the clock used by the serial bus interface It is possible to control ...

Page 878: ...3 0050 Figure 18 1 shows a schematic diagram of the four channels in the SSI module AUDIO_X1 AUDIO_X2 AUDIO_CLK SSIWS0 SSISCK0 SSI0 SSIDATA0 EXTAL XTAL CKIO SSIWS1 SSISCK1 SSI1 SSIDATA1 SSIWS2 SSISCK2 SSI2 SSIDATA2 SSIWS3 SSISCK3 SSI3 SSIDATA3 Figure 18 1 Schematic Diagram of SSI Module ...

Page 879: ...SSITDR SSIRDR SSI module DMA request Interrupt request Peripheral bus Data buffer Barrel shifter Control circuit Bit counter Serial clock control Divider LSB MSB Shift register CKIO Oscillation circuit EXTAL XTAL AUDIO_X2 AUDIO_CLK AUDIO_X1 SSICR SSISR SSITDR SSIRDR Control register Status register Transmit data register Receive data register Legend Oscillation circuit Figure 18 2 Block Diagram of...

Page 880: ... I O Serial data input output SSISCK1 1 I O Serial bit clock SSIWS1 1 I O Word selection SSIDATA1 1 I O Serial data input output SSISCK2 1 I O Serial bit clock SSIWS2 1 I O Word selection SSIDATA2 1 I O Serial data input output SSISCK3 1 I O Serial bit clock SSIWS3 1 I O Word selection SSIDATA3 1 I O Serial data input output AUDIO_CLK 1 Input External clock for audio entering oversampling clock 25...

Page 881: ...atus register 1 SSISR_1 R W H 02000003 H FFFEC804 32 Transmit data register 1 SSITDR_1 R W H 00000000 H FFFEC808 32 1 Receive data register 1 SSIRDR_1 R H 00000000 H FFFEC80C 32 Control register 2 SSICR_2 R W H 00000000 H FFFED000 32 Status register 2 SSISR_2 R W H 02000003 H FFFED004 32 Transmit data register 2 SSITDR_2 R W H 00000000 H FFFED008 32 2 Receive data register 2 SSIRDR_2 R H 00000000 ...

Page 882: ...nitial value R W Bit Initial value R W DMEM UIEN OIEN IIEN DIEN CHNL 1 0 DWL 2 0 SWL 2 0 SCKD SWSD SCKP SWSP SPDP SDTA PDTA DEL CKDV 2 0 MUEN TRMD EN Bit Bit Name Initial Value R W Description 31 to 29 All 0 R Reserved The read value is not guaranteed The write value should always be 0 28 DMEN 0 R W DMA Enable Enables disables the DMA request 0 DMA request is disabled 1 DMA request is enabled 27 U...

Page 883: ...Having one channel per system word 01 Having two channels per system word 10 Having three channels per system word 11 Having four channels per system word 21 to 19 DWL 2 0 000 R W Data Word Length Indicates the number of bits in a data word 000 8 bits 001 16 bits 010 18 bits 011 20 bits 100 22 bits 101 24 bits 110 32 bits 111 Reserved 18 to 16 SWL 2 0 000 R W System Word Length Indicates the numbe...

Page 884: ...prohibited 13 SCKP 0 R W Serial Bit Clock Polarity 0 SSIWS and SSIDATA change at the SSISCK falling edge sampled at the SCK rising edge 1 SSIWS and SSIDATA change at the SSISCK rising edge sampled at the SCK falling edge SCKP 0 SCKP 1 SSIDATA input sampling SSISCK rising edge SSISCK falling edge timing at the time of reception TRMD 0 SSIDATA output change SSISCK falling edge SSISCK rising edge tim...

Page 885: ...mode and SSITDR in transmit mode 0 Parallel data SSITDR SSIRDR is left aligned 1 Parallel data SSITDR SSIRDR is right aligned DWL 000 with a data word length of 8 bits the PDTA setting is ignored All data bits in SSIRDR or SSITDR are used on the audio serial bus Four data words are transmitted or received at each 32 bit access The first data word is derived from bits 7 to 0 the second from bits 15...

Page 886: ...its are ignored or reserved DWL 010 011 100 101 with a data word length of 18 20 22 or 24 bits PDTA 1 right aligned The data bits used in SSIRDR or SSITDR are the following Bits the number of bits in the data word length specified by DWL minus 1 to 0 i e if DWL 011 then DWL 20 and bits 19 to 0 are used in either SSIRDR or SSITDR All other bits are ignored or reserved DWL 110 with a data word lengt...

Page 887: ... frequency Oversampling clock frequency 4 011 Serial bit clock frequency Oversampling clock frequency 8 100 Serial bit clock frequency Oversampling clock frequency 16 101 Serial bit clock frequency Oversampling clock frequency 6 110 Serial bit clock frequency Oversampling clock frequency 12 111 Setting prohibited Note Oversampling clock is selected by the setting of the SCSR bits in the PFC For de...

Page 888: ...ined Un defined 0 0 1 1 R R R R R R R R R R R R R R R R Bit Initial value R W Bit Initial value R W Note Can be read from or written to Writing 0 initializes the bit but writing 1 is ignored DMRQ UIRQ OIRQ IIRQ DIRQ CHNO 1 0 SWNO IDST Bit Bit Name Initial Value R W Description 31 to 29 All 0 R Reserved The read value is not guaranteed The write value should always be 0 28 DMRQ 0 R DMA Request Stat...

Page 889: ...Q 1 SSIRDR was read before there was new unread data indicated by the DMRQ or DIRQ bit This can lead to the same received sample being stored twice by the host leading to potential corruption of multi channel data TRMD 1 Transmit mode If UIRQ 1 SSITDR did not have data written to it before it was required for transmission This will lead to the same sample being transmitted once more and a potentia...

Page 890: ...ntial corruption of multi channel data TRMD 1 Transmit mode If OIRQ 1 SSITDR had data written to it before it was transferred to the shift register This will lead to the loss of a sample and a potential corruption of multi channel data Note When overflow error occurs the current data in the data buffer of this module is overwritten by the next incoming data from the SSI interface 25 IIRQ 1 R Idle ...

Page 891: ...de 0 No unread data in SSIRDR 1 Unread data in SSIRDR TRMD 1 Transmit mode 0 Transmit buffer is full 1 Transmit buffer is empty and requires data to be written to SSITDR 23 to 4 Undefined R Reserved The read value is undefined The write value should always be 0 3 2 CHNO 1 0 00 R Channel Number These bits show the current channel number TRMD 0 Receive mode CHNO indicates which channel the data in S...

Page 892: ...s status flag indicates that the serial bus activity has stopped This bit is cleared if EN 1 and the serial bus are currently active This bit is automatically set to 1 under the following conditions SSI Master transmitter SWSD 1 and TRMD 1 This bit is set to 1 if all the data in the system word to be transmitted has been written to SSITDR and if the EN bit is cleared to end the system word current...

Page 893: ... 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W Bit Initial value R W 18 3 4 Receive Data Register SSIRDR SSIRDR is a 32 bit register that stores receive messages Data in this register is transferred from the shift register each time data word is received...

Page 894: ... formats in either mode The bus format can be selected from one of the eight major modes shown in table 18 3 Table 18 3 Bus Format for SSI Module Non Compressed Slave Receiver Non Compressed Slave Transmitter Non Compressed Master Receiver Non Compressed Master Transmitter TRMD 0 1 0 1 CPEN 0 0 0 0 SCKD 0 0 1 1 SWSD 0 0 1 1 EN MUEN DIEN IIEN OIEN UIEN Control Bits DEL PDTA SDTA SPDP SWSP SCKP SWL ...

Page 895: ...these signals do not conform to the format specified in the configuration fields of the SSI module operation is not guaranteed 3 Master Receiver This mode allows the module to receive serial data from another device The clock and word select signals are internally derived from the AUDIO_CLK input clock The format of these signals is defined in the configuration fields of the SSI module If the inco...

Page 896: ...ord length prev sample MSB LSB 1 LSB MSB LSB 1 LSB next sample System word 1 data word 1 System word 2 data word 2 SSISCK SSIWS SSIDATA SCKP 0 SWSP 0 DEL 0 CHNL 00 System word length data word length Figure 18 3 Philips Format without Padding MSB LSB MSB LSB Next System word 1 System word 2 Data word 1 Data word 2 Padding Padding SSISCK SSIWS SSIDATA SCKP 0 SWSP 0 DEL 0 CHNL 00 SPDP 0 SDTA 0 Syste...

Page 897: ...ATA SCKP 0 SWSP 0 DEL 1 CHNL 00 SPDP 0 SDTA 0 System word length data word length System word 1 System word 2 Data word 1 Data word 2 Padding Padding Figure 18 5 Sony Format Transmitted and received in the order of padding bits and serial data Matsushita Format MSB LSB System word 1 System word 2 Data word 1 Data word 2 Padding Padding MSB LSB Prev SSISCK SSIWS SSIDATA SCKP 0 SWSP 0 DEL 1 CHNL 00 ...

Page 898: ...s the number of padding bits for each of the valid setting If setting is not valid is indicated instead of a number Table 18 4 The Number of Padding Bits for Each Valid Setting Padding Bits Per System Word DWL 2 0 000 001 010 011 100 101 110 CHNL 1 0 Decoded Channels per System Word SWL 2 0 Decoded Word Length 8 16 18 20 22 24 32 000 8 0 001 16 8 0 010 24 16 8 6 4 2 0 011 32 24 16 14 12 10 8 0 100...

Page 899: ... 101 110 CHNL 1 0 Decoded Channels per System Word SWL 2 0 Decoded Word Length 8 16 18 20 22 24 32 000 8 001 16 010 24 0 011 32 8 100 48 24 0 101 64 40 16 10 4 110 128 104 80 74 68 62 56 32 10 3 111 256 232 208 202 196 190 184 160 000 8 001 16 010 24 011 32 0 100 48 16 101 64 32 0 110 128 96 64 56 48 40 32 0 11 4 111 256 224 192 184 176 168 160 128 ...

Page 900: ...on is arbitrary and is just for demonstration purposes only MSB LSB Data word 1 MSB LSB MSB LSB MSB LSB Data word 2 Data word 3 Data word 4 System word 1 System word 2 MSB LSB Data word 1 MSB LSB MSB LSB MSB LSB Data word 2 Data word 3 Data word 4 System word 1 System word 2 LSB MSB SSISCK SSIWS SSIDATA SCKP 0 SWSP 0 DEL 0 CHNL 01 SPDP don t care SDTA don t care System word length data word length...

Page 901: ...hese bits are not mutually exclusive but some combinations may not be useful for any other device These configuration bits are described below with reference to figure 18 10 SSISCK SSIWS SSIDATA Key for this and following diagrams 0 0 0 0 0 0 means a low level on the serial bus padding or mute 0 means a high level on the serial bus padding 1 Arrow head indicates sampling point of receiver Bit n in...

Page 902: ...l TD28 TD31 TD31 TD30 TD29 TD28 TD31 TD30 TD29 TD28 As basic sample format configuration except SCKP 1 Figure 18 11 Inverted Clock Inverted Word Select SSISCK SSIWS SSIDATA 0 0 0 0 0 0 1st Channel 2nd Channel TD28 TD31 TD31 TD30 TD29 TD28 TD31 TD30 TD29 TD28 As basic sample format configuration except SWSP 1 Figure 18 12 Inverted Word Select Inverted Padding Polarity SSISCK SSIWS SSIDATA TD28 TD31...

Page 903: ...the Order of Serial Data and Padding Bits without Delay As basic sample format configuration except SDTA 1 and DEL 1 0 0 0 TD28 0 0 TD29 0 TD31 TD30 TD29 TD28 TD31 TD30 TD29 TD28 SSISCK SSIWS SSIDATA 1st Channel 2nd Channel Figure 18 15 Transmitting and Receiving in the Order of Serial Data and Padding Bits without Delay Transmitting and Receiving in the Order of Padding Bits and Serial Data witho...

Page 904: ...iguration except PDTA 1 0 0 0 0 0 0 TD3 TD0 TD3 TD2 TD1 TD0 TD3 TD2 TD1 TD0 SSISCK SSIWS SSIDATA 1st Channel 2nd Channel Figure 18 17 Parallel Right Aligned with Delay Mute Enabled As basic sample format configuration except MUEN 1 TD data ignored 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSISCK SSIWS SSIDATA 1st Channel 2nd Channel Figure 18 18 Mute Enabled ...

Page 905: ...ive EN 0 IDST 0 EN 0 IDST 1 Reset Figure 18 19 Operation Modes 1 Configuration Mode This mode is entered after the module is released from reset All required configuration fields in the control register should be defined in this mode before the SSI module is enabled by setting the EN bit Setting the EN bit causes the module to enter the module enabled mode 2 Module Enabled Mode Operation of the mo...

Page 906: ...ing the interrupts that the SSI module generates to supply data as required This mode has a higher interrupt load as the module is only double buffered and will require data to be written at least every system word period When disabling the module the SSI clock must remain present until the SSI module is in idle state indicated by the IIRQ bit Figure 18 20 shows the transmit operation in DMA contr...

Page 907: ...terrupts enable Idle interrupt Wait for idle interrupt from SSI module End Yes No No Yes Yes No EN 1 DMEN 1 UIEN 1 OIEN 1 EN 0 DMEN 0 UIEN 0 OIEN 0 IIEN 1 Release from reset set SSICR configuration bits Set up DMA controller to provide transmission data as required DMAC End of Tx data Note If the SSI encounters an error interrupt underflow overflow go back to the start in the flowchart again Defin...

Page 908: ... disable data interrupts disable error interrupts enable Idle interrupt Wait for Idle interrupt from SSI module End No Yes Yes No EN 1 DIEN 1 UIEN 1 OIEN 1 Use SSI status register bits to realign data after underflow overflow EN 0 DIEN 0 UIEN 0 OIEN 0 IIEN 1 Load data of channel n For n CHNL 1 x 2 Loop Next channel Release from reset set SSICR configuration bits Define TRMD EN SCKD SWSD MUEN DEL P...

Page 909: ...n reception can be controlled either by DMA or interrupt Figures 18 22 and 18 23 show the flow of operation When disabling the SSI module the SSI clock must be kept supplied until the IIRQ bit is in idle state Note Input clock from the SSISCK pin when SCKD 0 Input clock from the AUDIO_CLK pin or AUDIO_X1 and AUDIO_X2 pins when SCKD 1 ...

Page 910: ...rrupts enable Idle interrupt Wait for idle interrupt from SSI module End Yes No No Yes Yes No EN 1 DMEN 1 UIEN 1 OIEN 1 EN 0 DMEN 0 UIEN 0 OIEN 0 IIEN 1 Setup DMA controller to transfer data from SSI module to memory Release from reset define SSICR configuration bits DMAC End of Rx data Define TRMD EN SCKD SWSD MUEN DEL PDTA SDTA SPDP SWSP SCKP SWL DWL CHNL Note If the SSI encounters an error inte...

Page 911: ...able error interrupts enable idle interrupt Wait for idle interrupt from SSI module End Yes No Yes No EN 1 DIEN 1 UIEN 1 OIEN 1 Use SSI status register bits to realign data after underflow overflow EN 0 DIEN 0 UIEN 0 OIEN 0 IIEN 1 Read data from receive data register Release from reset define SSICR configuration bits SSI error interrupt Receive more data Define TRMD EN SCKD SWSD MUEN DEL PDTA SDTA...

Page 912: ...re for the transfer and stop without having to reconfigure the bus bridge BBG DMAC 1 Set SSICR DMEN 0 disabling a DMA request to stop the DMA transfer 2 Wait for SSISR DIRQ 1 transmit mode the transmit buffer is empty using a polling interrupt or the like 3 With SSICR EN 0 disabling an SSI module operation stop the transfer 4 Before attempting another transfer make sure that SSISR IDST 1 is reache...

Page 913: ...er uses the bit clock that was input to the SSISCK pin If the serial clock direction is set to output SCKD 1 the SSI module is in clock master mode and the shift register uses the bit clock that was input from the AUDIO_CLK pin or AUDIO_X1 and AUDIO_X2 pins or the bit clock that is generated by dividing them This input clock is then divided by the ratio in the serial oversampling clock divide rati...

Page 914: ...d with the overflow error interrupt or overflow error status flag the OIRQ bit in SSISR write 0 to the EN bit in SSICR and DMEN bit to disable DMA in the SSI module thus stopping the operation In this case the controller setting should also be stopped After this write 0 to the OIRQ bit to clear the overflow status set DMA again and restart the transfer 18 5 2 Note on Using Oversampling Clock To us...

Page 915: ...del is described in some detail It is not the intention of this document to describe the implementation of the programming interface but to simply present the interface to the underlying CAN functionality The document places no constraints upon the implementation of the RCAN TL1 module in terms of process packaging or power supply criteria These issues are resolved where appropriate in implementat...

Page 916: ...ilboxes Programmable CAN data rate up to 1MBit s Transmit message queuing with internal priority sorting mechanism against the problem of priority inversion for real time applications Data buffer access without SW handshake requirement in reception Flexible micro controller interface Flexible interrupt structure 16 bit free running timer with flexible clock sources and pre scaler 3 Timer Compare M...

Page 917: ... Mailbox27 Mailbox28 Mailbox29 Mailbox30 Mailbox31 Mailbox0 Mailbox1 Mailbox2 Mailbox3 Mailbox4 Mailbox5 Mailbox6 Mailbox7 Mailbox8 Mailbox9 Mailbox10 Mailbox11 Mailbox12 Mailbox13 Mailbox14 Mailbox15 Mailbox16 Mailbox17 Mailbox18 Mailbox19 Mailbox20 Mailbox21 Mailbox22 Mailbox23 Mailbox24 Mailbox25 Mailbox26 Mailbox27 Mailbox28 Mailbox29 Mailbox30 Mailbox31 Mailbox0 Mailbox1 Mailbox2 Mailbox3 Mai...

Page 918: ...lbox has the following information RAM CAN message control identifier rtr ide etc CAN message data for CAN Data frames Local Acceptance Filter Mask for reception Registers CAN message control dlc Time Stamp for message reception transmission 3 bit wide Mailbox Configuration Disable Automatic Re Transmission bit Auto Transmission for Remote Request bit New Message Control bit Tx Trigger Time Mailbo...

Page 919: ...tion derived from the system clock or can be programmed to be incremented with one nominal bit timing of CAN Bus Contains registers such as TCNTR TTCR0 CMAX_TEW RETROFF TSR CCR CYCTR RFMK TCMR0 TCMR1 TCMR2 and TTTSEL CAN Interface This block conforms to the requirements for a CAN Bus Data Link Controller which is specified in Ref 2 4 It fulfils all the functions of a standard DLC as specified by t...

Page 920: ...rview The purpose of this programming interface is to allow convenient effective access to the CAN bus for efficient message transfer Please bear in mind that the user manual reports all settings allowed by the RCAN TL1 IP Different use of RCAN TL1 is not allowed 19 3 1 Memory Map The diagram of the memory map is shown below ...

Page 921: ...Pending Register RFPR1 Remote Frame Pending Register RFPR0 Mailbox Interrupt Mask Register MBIMR1 Mailbox Interrupt Mask Register MBIMR0 Unread Message Status Register UMSR1 Unread Message Status Register UMSR0 Reference Trigger Offset Register RFTROFF Timer Trigger Control Register0 TTCR0 Timer Status Register TSR Timer Compare Match Register 2 TCMR2 Tx Trigger Time Selection Register TTTSEL Cycl...

Page 922: ... bytes 2 bytes 0 Receive Only 100 103 104 107 108 10F 110 111 112 113 No No 1 120 123 124 127 128 12F 130 131 132 133 No No 2 140 143 144 147 148 14F 150 151 152 153 No No 3 160 163 164 167 168 16F 170 171 172 173 No No 4 180 183 184 187 188 18F 190 191 192 193 No No 5 1A0 1A3 1A4 1A7 1A8 1AF 1B0 1B1 1B2 1B3 No No 6 1C0 1C3 1C4 1C7 1C8 1CF 1D0 1D1 1D2 1D3 No No 7 1E0 1E3 1E4 1E7 1E8 1EF 1F0 1F1 1F...

Page 923: ...408 40F 410 411 No 414 415 416 417 25 420 423 424 427 428 42F 430 431 No 434 435 436 437 26 440 443 444 447 448 44F 450 451 No 454 455 456 457 27 460 463 464 467 468 46F 470 471 No 474 475 476 477 28 480 483 484 487 488 48F 490 491 No 494 495 496 497 29 4A0 4A3 4A4 4A7 4A8 4AF 4B0 4B1 No 4B4 4B5 4B6 4B7 30 4C0 4C3 4C4 4C7 4C8 4CF 4D0 4D1 4D2 4D3 Local Time 4D4 4D5 No 31 4E0 4E3 4E4 4E7 4E8 4EF 4F0...

Page 924: ...at SOF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 RTR IDE 0 0 NMC ATX DART DLC 3 0 EXTID 15 0 STDID 10 0 EXTID 17 16 MBC 2 0 MSG_DATA_1 MSG_DATA_3 MSG_DATA_5 MSG_DATA_7 EXTID_ LAFM 17 16 IDE_ LAFM 0 0 STDID_LAFM 10 0 EXTID_LAFM 15 0 0 0 0 0 MSG_DATA_0 first Rx Tx Byte MSG_DATA_2 MSG_DATA_4 MSG_DATA_6 MSG_DATA_0 first Rx Tx Byte MSG_DATA_2 MSG_DATA_4 MSG_DATA_6 Address Data Bus Access Size Field Name ...

Page 925: ...Tx Byte MSG_DATA_2 MSG_DATA_4 MSG_DATA_6 Address Data Bus Access Size Field Name H 100 N 32 H 102 N 32 H 104 N 32 H 106 N 32 H 108 N 32 H 10A N 32 H 10C N 32 H 10E N 32 H 110 N 32 Word LW Word Word LW Word Byte Word LW Byte Word Byte Word LW Byte Word Byte Word Control 0 LAFM Data Control 1 Control 1 Trigger Time TT control Tx Triggered Time TTT MB23 to 16 MB without timestamp MSG_DATA_0 first Rx ...

Page 926: ...te Word LW Byte Word Byte Word Word Word Control 0 LAFM Data Control 1 TimeStamp Trigger Time Control 1 TimeStamp MB30 Time Reference Transmitssion in Time Trigger mode MB31 Time Reference Reception in Time Trigger mode EXTID 15 0 STDID 10 0 MSG_DATA_1 MSG_DATA_3 MSG_DATA_5 MSG_DATA_7 MSG_DATA_0 first Rx Tx Byte MSG_DATA_2 MSG_DATA_4 MSG_DATA_6 H 100 N 32 H 102 N 32 H 104 N 32 H 106 N 32 H 108 N 3...

Page 927: ...will never be set When a Remote Frame is received the CPU can be notified by the corresponding RFPR set or IRR 2 Remote Frame Receive Interrupt however as RCAN TL1 needs to transmit the current message as a Data Frame the RTR bit remains unchanged Important In order to support automatic answer to remote frame when MBC 001 bin is used and ATX 1 the RTR flag must be programmed to zero to allow data ...

Page 928: ...R or RFPR bit is already set does not store the new message but maintains the old one and sets the UMSR correspondent bit When this bit is set to 1 the Mailbox of which the RXPR or RFPR bit is already set overwrites with the new message and sets the UMSR correspondent bit Important Please note that if a remote frame is overwritten with a data frame or vice versa could be that both RXPR and RFPR fl...

Page 929: ...ever be set despite receiving a Remote Frame When a Remote Frame is received the CPU will be notified by the corresponding RFPR set however as RCAN TL1 needs to transmit the current message as a Data Frame the RTR bit remains unchanged Important Please note that in case of overrun condition UMSR flag set when the Mailbox has its NMC 0 the message received is discarded In case a remote frame is cau...

Page 930: ...box 0 is fixed to 1 by hardware This is to ensure that MB0 cannot be configured to transmit Messages MBC 2 MBC 1 MBC 0 Data Frame Transmit Remote Frame Transmit Data Frame Receive Remote Frame Receive Remarks 0 0 0 Yes Yes No No Not allowed for Mailbox 0 Time Triggered transmission can be used 0 0 1 Yes Yes No Yes Can be used with ATX Not allowed for Mailbox 0 LAFM can be used 0 1 0 No No Yes Yes ...

Page 931: ...Field It allows a Mailbox to accept more than one identifier The LAFM is comprised of two 16 bit read write areas as follows Word LW Word H 104 N 32 H 106 N 32 LAFM Field 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXTID_ LAFM 17 16 IDE_ LAFM 0 0 STDID_LAFM 10 0 EXTID_LAFM 15 0 Figure 19 4 Acceptance filter If a bit is set in the LAFM then the corresponding bit of a received CAN identifier is ignored wh...

Page 932: ... bit for the CAN IDE bit IDE_LAFM Description 0 Corresponding IDE bit is cared 1 Corresponding IDE bit is don t cared 3 Message Data Fields Storage for the CAN message data that is transmitted or received MSG_DATA 0 corresponds to the first data byte that is transmitted or received The bit order on the CAN bus is bit 7 through to bit 0 When CMAX 3 b111 MBC 30 3 b000 and TXPR 30 is set Mailbox 30 i...

Page 933: ...e a useful function to monitor if messages are received transmitted within expected schedule Timestamp 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R TS15 TS14 TS13 TS12 TS11 TS7 TS6 TS5 TS10 TS9 TS8 TS4 TS3 TS2 TS1 TS0 Message Receive For received messages of Mailbox 15 to 0 Timestamp always captures the CYCTR Cycle Time...

Page 934: ...e TTT and TT control are comprised of two 16 bit read write areas as follows Mailbox 30 doesn t have TT control and works as Time_Ref Mailbox 30 to 24 can be used for reception if not used for transmission in TT mode However they cannot join the event trigger transmission queue when the TT mode is used Tx Trigger Time 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 ...

Page 935: ...first 16 bit area specifies the time that triggers the transmission of the message in cycle time The second 16 bit area specifies the basic cycle in the system matrix where the transmission must start Offset and the frequency for periodic transmission When the internal TTT register matches to the CYCTR value and the internal Offset matches to CCR value transmission is attempted from the correspond...

Page 936: ...Mailbox 30 TTW is fixed to 01 Offset to 00 and rep_factor to 0 The following tables report the combinations for the rep_factor and the offset Rep_factor Description 3 b000 Every basic cycle initial value 3 b001 Every two basic cycle 3 b010 Every four basic cycle 3 b011 Every eight basic cycle 3 b100 Every sixteen basic cycle 3 b101 Every thirty two basic cycle 3 b110 Every sixty four basic cycle o...

Page 937: ...tial Offset 2 nd Basic Cycles 6 b000010 Initial Offset 3 rd Basic Cycles 6 b000011 Initial Offset 4 th Basic Cycles 6 b000100 Initial Offset 5 th Basic Cycles 6 b111110 Initial Offset 63 rd Basic Cycles 6 b111111 Initial Offset 64 th Basic Cycles The following relation must be maintained Cycle_Count_Maximum 1 Repeat_Factor Offset Cycle_Count_Maximum 2 CMAX 1 Repeat_Factor 2 rep_factor ...

Page 938: ..._factor 3 b010 Repeat_Factor 4 CMAX 3 b100 Cycle_Count_Max 15 CCR 0 System Matrix offset 1 offset 1 offset 1 CCR 1 CCR 2 CCR 3 CCR 4 CCR 5 CCR 6 CCR 7 CCR 12 CCR 13 CCR 14 CCR 15 Repeat_Factor Figure 19 8 System Matrix The Tx Trigger Time must be set in ascending order Please bear in mind that a minimum difference of TEW s width between Tx Trigger Times is allowed ...

Page 939: ...nterrupt Register 008 IRR Word Interrupt Mask Register 00A IMR Word Error Counter Register 00C TEC REC Word Figure 19 9 RCAN TL1 control registers 1 Master Control Register MCR The Master Control Register MCR is a 16 bit read write register that controls RCAN TL1 MCR Address H 000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 R W R W R R R R W R W R W R W R W R W R R R W R ...

Page 940: ... as RCAN TL1 enters BusOff Bit14 MCR14 Description 0 RCAN TL1 remains in BusOff for normal recovery sequence 128 x 11 Recessive Bits Initial value 1 RCAN TL1 moves directly into Halt Mode after it enters BusOff if MCR6 is set This bit can be modified only in reset mode Bit 13 Reserved The written value should always be 0 and the returned value is 0 Bit 12 Reserved The written value should always b...

Page 941: ...the RCAN TL1 does not automatically cancel the sleep mode RCAN TL1 cannot store the message that wakes it up Note This bit can be modified only Reset or Halt mode Bit7 MCR7 Description 0 Auto wake by CAN bus activity disabled Initial value 1 Auto wake by CAN bus activity enabled Bit 6 Halt during Bus Off MCR6 MCR6 enables or disables entering Halt mode immediately when MCR1 is set during Bus Off T...

Page 942: ...er in Sleep mode That allows the CPU to clear all pending interrupts before entering sleep mode Once all interrupts are cleared RCAN TL1 must leave the Halt mode and enter Sleep mode simultaneously by writing MCR 5 1 and MCR 1 0 at the same time Bit 5 MCR5 Description 0 RCAN TL1 sleep mode released Initial value 1 Transition to RCAN TL1 sleep mode enabled Bit 4 Reserved The written value should al...

Page 943: ...regardless of MCR6 RCAN TL1 will enter Halt Mode within one Bit Time If MCR6 is set a halt request during Bus Off will be also processed within one Bit Time Otherwise the full Bus Off recovery sequence will be performed beforehand Entering the Halt Mode can be notified by IRR0 and GSR4 If both MCR14 and MCR6 are set MCR1 is automatically set as soon as RCAN TL1 enters BusOff In the Halt mode the R...

Page 944: ...en made and RCAN TL1 needs to be configured The Reset Request is equivalent to a Power On Reset but controlled by Software Bit 0 MCR0 Description 0 Clear Reset Request 1 CAN Interface reset mode transition request Initial value 2 General Status Register GSR The General Status Register GSR is a 16 bit read only register that indicates the status of RCAN TL1 GSR Address H 002 15 14 13 12 11 10 9 8 7...

Page 945: ...reflects the status of the CAN engine and not of the full RCAN TL1 IP RCAN TL1 exits sleep mode and can be accessed once MCR5 is cleared The CAN engine exits sleep mode only after two additional transmission clocks on the CAN Bus Bit 4 GSR4 Description 0 RCAN TL1 is not in the Halt state or Sleep state Initial value 1 Halt mode if MCR1 1 or Sleep mode if MCR5 1 Setting condition If MCR1 is set and...

Page 946: ...ransmission is in progress 1 Setting condition Not in Bus Off and no transmission in progress Initial value Bit 1 Transmit Receive Warning Flag GSR1 Flag that indicates an error warning Bit 1 GSR1 Description 0 Reset condition When TEC 96 and REC 96 or Bus Off Initial value 1 Setting condition When 96 TEC 256 or 96 REC 256 Note REC is incremented during Bus Off to count the recurrences of 11 reces...

Page 947: ...10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R R W R W R W R R R W R W R R R R W TSG1 3 0 TSG2 2 0 SJW 1 0 BSP Bit Initial value R W Bits 15 to 12 Time Segment 1 TSG1 3 0 BCR1 15 12 These bits are used to set the segment TSEG1 PRSEG PHSEG1 to compensate for edges on the CAN Bus with a positive phase error A value from 4 to 16 time quanta can be set Bit 15 TSG1 3 Bit 14 TS...

Page 948: ...ime quanta 1 1 1 PHSEG2 8 time quanta Bits 7 and 6 Reserved The written value should always be 0 and the returned value is 0 Bits 5 and 4 ReSynchronisation Jump Width SJW 1 0 BCR0 5 4 These bits set the synchronisation jump width Bit 5 SJW 1 Bit 4 SJW 0 Description 0 0 Synchronisation Jump width 1 time quantum Initial value 0 1 Synchronisation Jump width 2 time quanta 1 0 Synchronisation Jump widt...

Page 949: ...0 0 2 X peripheral bus clock Initial value 0 0 0 0 0 0 0 1 4 X peripheral bus clock 0 0 0 0 0 0 1 0 6 X peripheral bus clock 2 register value 1 X peripheral bus clock 1 1 1 1 1 1 1 1 512 X peripheral bus clock Requirements of Bit Configuration Register SYNC_SEG PRSEG PHSEG1 TSEG1 1 bit time 8 25 quanta 1 4 16 2 8 TSEG2 Quantum PHSEG2 SYNC_SEG Segment for establishing synchronisation of nodes on th...

Page 950: ... register values The 1 in the above formula is for the Sync Seg which duration is 1 time quanta fCLK Peripheral Clock BCR Setting Constraints TSEG1min TSEG2 SJWmax SJW 1 to 4 8 TSEG1 TSEG2 1 25 time quanta TSEG1 TSEG2 1 7 is not allowed TSEG2 2 These constraints allow the setting range shown in the table below for TSEG1 and TSEG2 in the Bit Configuration Register The number in the table shows poss...

Page 951: ...4 1 4 1 4 1 4 1 4 1010 11 1 2 1 3 1 4 1 4 1 4 1 4 1 4 1011 12 1 2 1 3 1 4 1 4 1 4 1 4 1 4 1100 13 1 2 1 3 1 4 1 4 1 4 1 4 1 4 1101 14 1 2 1 3 1 4 1 4 1 4 1 4 1 4 1110 15 1 2 1 3 1 4 1 4 1 4 1 4 1 4 1111 16 1 2 1 3 1 4 1 4 1 4 1 4 1 4 Example 1 To have a Bit rate of 500Kbps with a frequency of fclk 40MHz it is possible to set BRP 3 TSEG1 6 TSEG2 3 Then the configuration to write is BCR1 5200 and BC...

Page 952: ...Description 0 Timer Compare Match has not occurred to the TCMR1 Initial value Clearing condition Writing 1 1 Timer Compare Match has occurred to the TCMR1 Setting condition TCMR1 matches to Cycle Time TCMR1 CYCTR Bit 14 Timer Compare Match Interrupt 0 IRR14 Indicates that a Compare Match condition occurred to the Timer Compare Match Register 0 TCMR0 When the value set in the TCMR0 matches to Local...

Page 953: ... test modes Time reference message with Next_is_Gap has been received in time trigger mode including test modes Message error has occurred in test mode Bit 12 Bus activity while in sleep mode IRR12 IRR12 indicates that a CAN bus activity is present While the RCAN TL1 is in sleep mode and a dominant bit is detected on the CAN bus this bit is set This interrupt is cleared by writing a 1 to this bit ...

Page 954: ...when CMAX 0 this interrupt is set at every basic cycle Bit 10 IRR10 Description 0 A new system matrix is not starting initial value Clearing condition Writing 1 1 Cycle counter reached zero Setting condition Reception transmission of time reference message is successfully completed when CMAX 3 b111 and CCR 0 Bit 9 Message Overrun Overwrite Interrupt Flag IRR9 Flag indicating that a message has bee...

Page 955: ...message data for the next transmission In Time Trigger mode TXPR for the Mailboxes from 30 to 24 is not cleared after a successful transmission in order to keep transmitting at each programmed basic cycle In effect this bit is set by an OR ed signal of the TXACK and ABACK bits not masked by the corresponding MBIMR flag Therefore this bit is automatically cleared when all the TXACK and ABACK bits a...

Page 956: ...eaves the bus off condition and needs to be explicitly cleared by S W The S W is expected to read the GSR0 to judge whether RCAN TL1 is in the bus off or error active status It is cleared by writing a 1 to this bit position even if the node is still bus off Writing a 0 has no effect Bit 6 IRR6 Description 0 Clearing condition Writing 1 Initial value 1 Enter Bus off state caused by transmit error o...

Page 957: ...ndicating that a remote frame has been received in a mailbox This bit is set if at least one receive mailbox with related MBIMR not set contains a remote frame transmission request This bit is automatically cleared when all bits in the Remote Frame Receive Pending Register RFPR are cleared It is also cleared by writing a 1 to all the correspondent bit position in MBIMR Writing to this bit has no e...

Page 958: ...t mode must be used beforehand Please refer to the MCR5 description and Figure 19 15 Halt Mode Sleep Mode IRR0 is set by the transition from 0 to 1 of GSR3 or GSR4 or by transition from Halt mode to Sleep mode So IRR0 is not set if RCAN TL1 enters Halt mode again right after exiting from Halt mode without GSR4 being cleared Similarly IRR0 is not set by direct transition from Sleep mode to Halt Req...

Page 959: ...t the interrupt signal is not generated although setting the corresponding IRR bit is still performed Bit 15 0 IMRn Description 0 Corresponding IRR is not masked IRQ is generated for interrupt conditions 1 Corresponding interrupt of IRR is masked Initial value 6 Transmit Error Counter TEC and Receive Error Counter REC The Transmit Error Counter TEC and Receive Error Counter REC is a 16 bit read wr...

Page 960: ...C2 TEC1 TEC0 REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 Note It is only possible to write the value in test mode when TST 2 0 in MCR is 3 b100 REC is incremented during Bus Off to count the recurrences of 11 recessive bits as requested by the Bus Off recovery sequence 19 3 4 RCAN TL1 Mailbox Registers The following sections describe RCAN TL1 Mailbox registers that control flag individual Mailboxes Th...

Page 961: ...e 0 032 TXACK0 Word 034 036 Abort Acknowledge 1 038 ABACK1 Word LW Abort Acknowledge 0 03A ABACK0 Word 03C 03E Data Frame Receive Pending 1 040 RXPR1 Word LW Data Frame Receive Pending 0 042 RXPR0 Word 044 046 Remote Frame Receive Pending 1 048 RFPR1 Word LW Remote Frame Receive Pending 0 04A RFPR0 Word 04C 04E Mailbox Interrupt Mask Register 1 050 MBIMR1 Word LW Mailbox Interrupt Mask Register 0 ...

Page 962: ...Operation Temp TXPR1 TXPR0 H 020 H 022 upper word read 16 bit Peripheral bus TXPR0 is stored into Temp when TXPR1 is read consecutive access lower word read 16 bit Peripheral bus Temp is read instead of TXPR0 Temp TXPR1 TXPR0 H 020 H 022 The TXPR1 controls Mailbox 31 to Mailbox 16 and the TXPR0 controls Mailbox 15 to Mailbox 1 The CPU may set the TXPR bits to affect any message being considered fo...

Page 963: ...rity scheme MCR2 0 the highest priority message is always presented for transmission in an intelligent way even under circumstances such as bus arbitration losses or errors on the CAN bus Please refer to the Application Note for details When the RCAN TL1 changes the state of any TXPR bit position to a 0 an empty slot interrupt IRR8 may be generated This indicates that either a successful or an abo...

Page 964: ...te It is possible only to write a 1 for a Mailbox configured as transmitter Bit 15 to 1 Indicates that the corresponding Mailbox is requested to transmit a CAN Frame The bit 15 to 1 corresponds to Mailbox 15 to 1 respectively When multiple bits are set the order of the transmissions is governed by the MCR2 CAN ID or Mailbox number Bit 15 1 TXPR0 Description 0 Transmit message idle state in corresp...

Page 965: ...t however if the transmission fails due to a bus arbitration loss or an error on the bus the CAN controller clears the corresponding TXPR TXCR bit and sets the corresponding ABACK bit If an attempt is made by the CPU to clear a mailbox transmission that is not transmit pending it has no effect In this case the CPU will be not able at all to set the TXCR flag TXCR1 15 14 13 12 11 10 9 8 7 6 5 4 3 2...

Page 966: ...etion of transmit message cancellation automatically cleared 1 Transmission cancellation request made for corresponding mailbox Bit 0 This bit is always 0 as this is a receive only mailbox Writing a 1 to this bit position has no effect and always read back as a 0 3 Transmit Acknowledge Register TXACK1 TXACK0 The TXACK1 and TXACK0 are 16 bit read conditionally write registers These registers are us...

Page 967: ... 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W TXACK0 15 1 Note Only when writing a 1 to clear Bit 15 to 1 Notifies that the requested transmission of the corresponding Mailbox has been finished successfully The bit 15 to 1 corresponds to Mailbox 15 to 1 respectively Bit 15 1 TXACK0 Description 0 Clearing Co...

Page 968: ...0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W ABACK1 15 0 Note Only when writing a 1 to clear Bit 15 to 0 Notifies that the requested transmission cancellation of the corresponding Mailbox has been performed successfully The bit 15 to 0 corresponds to Mailbox 31 to 16 respectively Bit 15 0 ABACK1 Description 0 Clearing Condition Writing 1 Initial value 1 Corresponding Mai...

Page 969: ...e bit may be cleared by writing a 1 to the corresponding bit position Writing a 0 has no effect However the bit may only be set if the mailbox is configured by its MBC Mailbox Configuration to receive Data Frames When a RXPR bit is set it also sets IRR1 Data Frame Received Interrupt Flag if its MBIMR Mailbox Interrupt Mask Register is not set and the interrupt signal is generated if IMR1 is not se...

Page 970: ... W R W R W R W R W R W R W R W R W R W R W R W R W RXPR0 15 0 Note Only when writing a 1 to clear Bit 15 to 0 Configurable receive mailbox locations corresponding to each mailbox position from 15 to 0 respectively Bit 15 0 RXPR0 Description 0 Clearing Condition Writing 1 Initial value 1 Corresponding Mailbox received a CAN Data Frame Setting Condition Completion of Data Frame receive on correspond...

Page 971: ... sets IRR2 Remote Frame Receive Interrupt Flag if its MBIMR Mailbox Interrupt Mask Register is not set and the interrupt signal is generated if IMR2 is not set Please note that these bits are only set by receiving Remote Frames and not by receiving Data frames RFPR1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R...

Page 972: ...R 1 and IRR 2 and IRR 9 but does not prevent the setting of the corresponding bit in the RXPR or RFPR or UMSR Similarly when a mailbox has been configured for transmission a mask prevents the generation of an Interrupt signal and setting of an Mailbox Empty Interrupt due to successful transmission or abortion of transmission IRR 8 however it does not prevent the RCAN TL1 from clearing the correspo...

Page 973: ...est from IRR1 IRR2 IRR8 IRR9 disabled initial value 8 Unread Message Status Register UMSR This register is a 32 bit read conditionally write register and it records the mailboxes whose contents have not been accessed by the CPU prior to a new message being received If the CPU has not cleared the corresponding bit in the RXPR or RFPR when a new message for that mailbox is received the corresponding...

Page 974: ...ge is received before RXPR or RFPR is cleared UMSR0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W UMSR0 15 0 Note Only when writing a 1 to clear Bit 15 to 0 Indicate that an unread received message has been overwritten or overrun condition has occurred for Mailboxes 15 to 0 Bit 15 0 UMSR0 ...

Page 975: ...R Word 16 Timer Counter Register 08C TCNTR Word 16 Cycle Time Register 090 CYCTR Word 16 Reference Mark Register 094 RFMK Word 16 Timer Compare Match Register 0 098 TCMR0 Word 16 Timer Compare Match Register 1 09C TCMR1 Word 16 Timer Compare Match Register 2 0A0 TCMR2 Word 16 Tx Trigger Time Selection Register 0A4 TTTSEL Word 16 Figure 19 12 RCAN TL1 Timer registers 1 Time Trigger Control Register...

Page 976: ...amp for Mailboxes 30 and 31 Bit14 TTCR0 14 Description 0 CYCTR 15 0 is used for the TimeStamp in Mailboxes 15 to 1 initial value 1 CCR 5 0 CYCTR 15 6 is used for the TimeStamp in Mailboxes 15 to 1 Bit 13 Cancellation by TCMR2 The messages in the transmission queue are cancelled by setting TXCR when both this bit and bit12 are set and compare match occurs when RCAN TL1 is not in the Halt status cau...

Page 977: ... 0 IRR14 isn t set by TCMR0 compare match initial value 1 IRR14 is set by TCMR0 compare match Bits 9 to 7 Reserved The written value should always be 0 and the returned value is 0 Bit 6 Timer Clear Set Control by TCMR0 Specifies if the Timer is to be cleared and set to H 0000 when the TCMR0 matches to the TCNTR Please note that the TCMR0 is also capable to generate an interrupt signal to the CPU v...

Page 978: ... 2 X Source Clock 0 0 0 0 1 0 3 X Source Clock 0 0 0 0 1 1 4 X Source Clock 0 0 0 1 0 0 5 X Source Clock 1 1 1 1 1 1 64 X Source Clock 2 Cycle Maximum Tx Enable Window Register CMAX_TEW This register is a 16 bit read write register CMAX specifies the maximum value for the cycle counter CCR for TT Transmissions to set the number of basic cycles in the matrix system When the Cycle Counter reaches th...

Page 979: ... Maximum 31 1 1 0 Cycle Count Maximum 63 1 1 1 CCR is cleared and RCAN TL1 is in event trigger mode initial value Important Please set CMAX 3 b111 when event trigger mode is used Bits 7 to 4 Reserved The written value should always be 0 and the returned value is 0 Bit 3 to 0 Tx Enable Window TEW Indicates the width of Tx Enable Window TEW H 00 shows the width is one nominal Bit Timing All values f...

Page 980: ...3 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R R R R R R R R RFTROFF 7 0 Bit Initial value R W Bit 15 to 8 Indicate the value of Reference Trigger Offset Bits 7 to 0 Reserved The written value should always be 0 and the returned value is 0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Description 0 0 0 0 0 0 0 0 Ref_trigger_offset 0 initial value 0...

Page 981: ...ect Bit 4 Start of New System Matrix TSR4 Indicates that a new system matrix is starting When CCR 0 this bit is set at the successful completion of reception transmission of time reference message Bit4 TSR4 Description 0 A new system matrix is not starting initial value Clearing condition Writing 1 to IRR10 Cycle Counter Overflow Interrupt 1 Cycle counter reached zero Setting condition When the Cy...

Page 982: ...ch has occurred to the TCMR1 Setting condition TCMR1 matches to Cycle Time TCMR1 CYCTR if TTCR0 bit11 1 Bit 1 Timer Compare Match Flag 0 TSR1 Indicates that a Compare Match condition occurred to the Compare Match Register 0 TCMR0 When the value set in the TCMR0 matches to the Timer value TCMR0 TCNTR this bit is set if TTCR0 bit10 1 Please note that this bit is read only and is cleared when IRR14 T...

Page 983: ...ed in different fashions depending if RCAN TL1 is programmed to work as a potential time master or as a time slave If RCAN TL1 is working as potential time master CCR is Incremented by one every time the cycle time CYCTR matches to Tx Trigger Time of Mailbox 30 or Overwritten with the value contained in MSG_DATA_0 5 0 of Mailbox 31 when a valid reference message is received If RCAN TL1 is working ...

Page 984: ...en the enabling of the timer and the moment where TCNTR starts incrementing This is caused by the internal logic used for the pre scaler TCNTR Address H 08C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W TCNTR 15 0 Note The register can be written only when enabled in TTCR0 15 Write operati...

Page 985: ...t signals clearing setting the Timer value only supported by TCMR0 or clear the transmission messages in the queue only supported by TCMR2 TCMR0 is compared with TCNTR however TCMR1 and TCMR2 are compared with CYCTR The value used for the compare can be configured independently for each register In order to set flags TTCR0 bit 12 10 needs to be set In Time Trigger mode TTCR0 bit6 has to be cleared...

Page 986: ...5 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W TCMR0 15 0 Bit 15 to 0 Timer Compare Match Register TCMR0 Indicates the value of TCNTR when compare match occurs TCMR1 Address H 09C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W R W R ...

Page 987: ...ation algorithm is shown in figure 19 13 Please note that this register is only indented for test and diagnosis When not in test mode this register must not be written to and the returned value is not guaranteed TTTSEL Address H 0A4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R W R W R W R W R W R W R W R R R R R R R R TTTSEL 14 8 Bit Initial value R W Note Only one bit...

Page 988: ...000 CYCTR TTT25 or MBC 25 0x000 CYCTR TTT26 or MBC 26 0x000 CYCTR TTT27 or MBC 27 0x000 CYCTR TTT28 or MBC 28 0x000 CYCTR TTT29 or MBC 29 0x000 MB25 MB26 reception transmission of reference message CYCTR TTT30 or MBC 30 0x000 or reception of reference message MB27 MB28 MB29 MB30 reset Figure 19 13 TTTSEL modification algorithm ...

Page 989: ...in Normal mode The following table is examples for test modes Test Mode can be selected only while in configuration mode The user must then exit the configuration mode ensuring BCR0 BCR1 is set in order to run the selected test mode Bit10 TST2 Bit9 TST1 Bit8 TST0 Description 0 0 0 Normal Mode initial value 0 0 1 Listen Only Mode Receive Only Mode 0 1 0 Self Test Mode 1 External 0 1 1 Self Test Mod...

Page 990: ...uts only recessive bits and CRxn n A B C pin is disabled Write Error Counter TEC REC can be written in this mode RCAN TL1 can be forced to become an Error Passive mode by writing a value greater than 127 into the Error Counters The value written into TEC is used to write into REC so only the same value can be set to these registers Similarly RCAN TL1 can be forced to become an Error Warning by wri...

Page 991: ...n Tx_Rx Mode Set TXPR to start transmission or stay idle to receive Configure MCR 15 Clear MCR 0 Clear Required IMR Bits RCAN TL1 Timer Reg Setting Set Bit Timing BCR Mailbox Setting STD ID EXT ID LAFM DLC RTR IDE MBC MBIMR DART ATX NMC Tx Trigger Time Message Data 2 IRR 0 1 GSR 3 1 automatically Transmission_Reception Tx_Rx Mode Receive 3 Transmit 3 Timer Start 4 Notes 1 SW reset could be perform...

Page 992: ...tion will occurs when the CAN Bus is idle or in intermission After RCAN TL1 transit to Halt Mode GSR4 is set Once the configuration is completed the Halt request needs to be released RCAN TL1 will join CAN Bus activity after the detection of 11 recessive bits on the CAN Bus Sleep mode When RCAN TL1 is in sleep mode the clock for the main blocks of the IP is stopped in order to reduce power consump...

Page 993: ...n Mode GSR 4 1 User monitor User monitor Yes IRR 0 1 Write MCR 1 1 Write IRR 0 1 Hardware operation Manual operation IRR 0 1 IRR 12 1 Write IRR 0 1 IRR 0 0 IRR 0 0 MCR 5 0 Write IRR 12 1 IRR 12 0 Write MCR 1 0 MCR 5 1 Halt Request Sleep Request Write IRR 12 1 IRR 12 0 Write MCR 5 0 No CAN Bus Activity Yes Sleep Mode Sequence flow No GSR4 0 Yes No MCR 7 1 Yes No CLK is STOP Only MCR GSR IRR IMR can...

Page 994: ... Halt Mode clear MCR5 1 clear MCR5 set MCR1 4 Sleep Mode set MCR5 clear MCR1 2 Figure 19 15 Halt Mode Sleep Mode Notes 1 MCR5 can be cleared by automatically by detecting a dominant bit on the CAN Bus if MCR7 is set or by writing 0 2 MCR1 is cleared in SW Clearing MCR1 and setting MCR5 have to be carried out by the same instruction 3 MCR1 must not be cleared in SW before GSR4 is set MCR1 can be se...

Page 995: ...register Flag_ register Mailbox ctrl0 LAFM Mailbox data Mailbox ctrl1 Mailbox Trigger Time TT control Reset yes yes yes yes yes yes yes yes yes Transmission Reception Halt Request yes yes no 1 yes yes no 1 yes 2 yes 2 no 1 yes 2 yes 2 Halt yes yes no 1 yes yes yes yes yes yes Sleep yes yes no no no no no no no Notes 1 No hardware protection 2 When TXPR is not set ...

Page 996: ...currently no transmission request made No TXPR flags set No No No Yes Yes Yes RCAN TL1 is in Tx_Rx Mode MBC x 0 Write 1 to the TXPR x bit at any desired time Internal Arbitration x Highest Priority Transmission Start Mailbox x is ready to be updated for next transmission Clear TXACK x Waiting for Interrupt Waiting for Interrupt TXACK x set CAN Bus Arbitration End Of Frame CAN Bus IRR8 set Update M...

Page 997: ... 1 At crc delimiter internal arbitration to search next message transmitted starts 2 2 Operations for both transmission and reception starts at SOF Because of a reception frame with higher priority RCAN TL1 becomes receiver Therefore Reception is carried out instead of transmitting Frame 3 3 1 At crc delimiter internal arbitration to search next message transmitted starts 3 2 Operations for both t...

Page 998: ...riggered Mailboxes TXPR is not cleared to support periodic transmission Roles of Registers The user registers of RCAN TL1 can be used to handle the main functions requested by the TTCAN standard TCNTR Local Time RFMK Ref_Mark CYCTR Cycle Time TCNTR RFMK RFTROFF Ref_Trigger_Offset for Mailbox 30 Mailbox 31 Mailbox dedicated to the reception of time reference message Mailbox 30 Mailbox dedicated to ...

Page 999: ...Cycle Time to monitor users specified events TCMR2 Watch_Trigger compare match with Cycle Time This can be programmed to abort all pending transmissions TTW Specifies the attribute of a time window used for transmission TTTSEL Specifies the next Mailbox waiting for transmission Time Master Time Slave RCAN TL1 can be programmed to work as a potential time master of the network or as a time slave Th...

Page 1000: ...bedded in the received Reference Message is copied to CCR If Next_is_Gap 1 IRR13 is set 2 When a Time Reference message is transmitted from Mailbox 30 the value of TCNTR stored into an internal register at the SOF is copied into Ref_Mark CCR is incremented when TTT of Mailbox 30 matches with CYCTR CCR is embedded into the first data byte of the time reference message Data0 7 6 CCR 5 0 Setting Tx T...

Page 1001: ...by RCAN TL1 NOT supported by RCAN TL1 TTT24 and TTT25 CCR 0 Mailbox 24 Tx Mailbox 25 Tx Mailbox 24 Tx Mailbox 25 Tx CCR 1 CCR 2 CCR 3 TTT25 Mailbox 24 Tx Mailbox 25 Tx Mailbox 24 Tx Mailbox 25 Tx Figure 19 18 Limitation on Tx Trigger Time The value of TCMR2 as Watch_Trigger has to be larger than TTT Mailbox 30 which shows the length of a basic cycle Figure 19 19 and Figure 19 20 show examples of c...

Page 1002: ...25 Time_Mark 3 TTT in MB26 Time_Mark 4 TTT in MB27 Time_Mark 5 TTT in MB28 Time_Mark 6 TTT in MB29 Time_Ref TTT in MB30 Time_Mark 1 TTT in MB24 Time_Mark 2 TTT in MB25 Time_Mark 3 TTT in MB26 Time_Mark 4 TTT in MB27 Time_Mark 5 TTT in MB28 Time_Mark 6 TTT in MB29 Time_Ref TTT in MB30 Time_Mark 1 TTT in MB24 Time_Mark 2 TTT in MB25 Time_Mark 3 TTT in MB26 Time_Mark 4 TTT in MB27 Time_Mark 5 TTT in ...

Page 1003: ...n MB30 CCR isn t incremented unlike time master copy CCR from received time reference Normal Operation L Figure 19 20 Time Slave Function to be implemented by software Some of the TTCAN functions need to be implemented in software The main details are reported hereafter Please refer to ISO 11898 4 for more details Change from Init_Watch_Trigger to Watch_Trigger RCAN TL1 offers the two registers TC...

Page 1004: ...alue Set TXPR for Mailbox 30 Write H 4000 into TTTSEL Enable the TCNTR timer through the bit 15 of TTCR0 Move to Transmission_Reception mode Wait for the reception or transmission of a valid reference message or for TCMR0 match If the local time reaches the value of TCMR0 the Init_Watch_Trigger is reached and the application needs to set TXCR for Mailbox 30 and start again If the reference message...

Page 1005: ...rrupt Waiting for Interrupt Figure 19 21 Message transmission request S W has to ensure that a message is updated before a Tx trigger for transmission occurs When the CYCTR reaches to TTT Tx Trigger Time of a Mailbox and CCR matches with the programmed cycle for transmission RCAN TL1 immediately transfers the message into the Tx buffer At this point RCAN TL1 will attempt a transmission within the ...

Page 1006: ...sic cycle This could cause a scheduling problem TXPR is not automatically cleared for periodic transmission If a periodic transmission needs to be cancelled the corresponding TXCR bit needs to be set by the application Example of Time Triggered System The following diagram shows a simple example of how time trigger system works using RCAN TL1 in time slave mode TTT24 TTT25 TTT26 TTT27 TTT28 TTT29 ...

Page 1007: ...11 CMAX 3 b011 TXPR 30 0 During merged arbitrating window request by time triggered transmission is served in the way of FCFS First Come First Served For example if Mailbox 25 cannot be transmitted between Tx Trigger Time 25 TTT25 and TTT26 Mailbox 25 has higher priority than Mailbox 26 between TTT26 and 28 MBC needs to be set into 3 b111 in order to disable time triggered transmission If RCAN TL1...

Page 1008: ...e TEW counter Transmission request for MBI Transmitted message Delay 1 Bit Timing 8 clocks to 2 Bit Timings 11 clocks n n 1 n 2 2 3 1 0 n n n 1 n 2 n 3 n 4 n 2 n 1 n n n 1 n 2 n 3 n 4 n 2 n 1 n n n 1 n 2 n 3 n 4 n 2 n 1 n n 1 n n 1 n 4 n 5 n 3 n 2 2 SOF 0 0 2 1 Figure 19 23 Timing Diagram of Timer During merged arbitrating window event trigger transmission is served after completion of time trigge...

Page 1009: ... Note that in the case that the TXPR is not set for the Mailbox which is assigned to close the Merged Arbitrating Window MAW then the MAW will still be closed at the end of the TEW following the TTT of the assigned Mailbox Please refer to Table Roles of Mailboxes in section 19 3 2 Mailbox Structure ...

Page 1010: ... CAN ID Received Compare ID with Mailbox N LAFM N if MBC is config to receive Store Mailbox Number N and go back to idle state Store Message by Overwriting Set UMSR Set IRR9 if MBIMR N 0 Generate Interrupt Signal if IMR9 0 Set RXPR N RFPR N Set IRR1 IRR2 if MBIMR N 0 Generate Interrupt Signal if IMR1 IMR2 0 Reject Message Set UMSR Set IRR9 if MBIMR N 0 Generate Interrupt Signal if IMR9 0 Set RXPR ...

Page 1011: ... ID LAFM of 2 or more Mailboxes the higher numbered Mailbox will always store the relevant messages and the lower numbered Mailbox will never receive messages Therefore the settings of the identifiers and LAFMs need to be carefully selected With regards to the reception of data and remote frames described in the above flow diagram the clearing of the UMSR flag after the reading of IRR is to detect...

Page 1012: ... the end of the reception transmission and also RCAN TL1 will not be able to receive transmit messages during the Halt state In case RCAN TL1 is in the Bus Off state the transition to halt state depends on the configuration of the bit 6 of MCR and also bit and 14 of MCR Change configuration ID RTR IDE LAFM Data DLC NMC ATX DART MBC of receiver box or Change receiver box to transmitter box The conf...

Page 1013: ... 1 Halt Mode Is RCAN TL1 Transmitter Receiver or Bus Off Generate interrupt IRR0 Read IRR0 GSR4 as 1 RCAN TL1 is in Halt Mode Change ID or MBC of Mailbox Clear MCR1 RCAN TL1 is in Tx_Rx Mode Yes No The shadowed boxes need to be done by S W host processor Finish current session Figure 19 25 Change ID of receive box or Change receive box to transmit box ...

Page 1014: ...ssion IRR7 Unread message overwrite overrun IRR9 Start of new system matrix IRR10 TCMR2 compare match IRR11 Bus activity while in sleep mode IRR12 Timer overrun Next_is_Gap reception message error IRR13 TCMR0 compare match IRR14 TCMR1 compare match IRR15 Data frame reception IRR1 3 Possible 4 RMn0 1 2 RMn1 1 2 Remote frame reception IRR2 3 SLEn 1 Message transmission transmission disabled slot emp...

Page 1015: ...automatically An interrupt request due to a receive interrupt from the RCAN TL1 cannot be sent to the CPU in this case Figure 19 26 shows a DMAC transfer flowchart DMAC initialization DMAC enable register setting DMAC register information setting End of DMAC transfer RXPR and RFPR flags clearing Yes END Message reception in RCAN TL1 mailbox 0 Interrupt to CPU Transfer counter 0 or DISEL 1 Yes DMAC...

Page 1016: ... IC is necessary to connect this LSI to a CAN bus A Renesas HA13721 transceiver IC and its compatible products are recommended Figure 19 27 shows a sample connection diagram MODE Rxd Txd NC CANH Vcc CANL GND CRxn Legend NC No Connection n 0 1 CTxn This LSI CAN bus 120 Ω 120 Ω Vcc HA13721 Figure 19 27 High Speed CAN Interface Using HA13721 ...

Page 1017: ...he RCAN TL1 in this LSI Using RCAN TL1 as a 2 channel module channels 0 and 1 Each channel has 32 Mailboxes Using RCAN TL1 as a 1 channel module channels 0 and 1 functioning as a single channel When the second method is used see section 19 9 1 Notes on Port Setting for Multiple Channels Used as Single Channel Figures 19 28 and 19 29 show connection examples for individual port settings CTx0 RCAN0 ...

Page 1018: ...etwork RCAN TL1 Rev 0 50 May 18 2006 Page 988 of 1588 REJ09B0313 0050 CTx0 CRx0 CTx1 CRx1 PB9 PB8 RCAN0 32 Mailboxes RCAN1 32 Mailboxes Figure 19 29 Connection Example when Using RCAN TL1 as 1 Channel Module 64 Mailboxes 1 Channel ...

Page 1019: ...ield in response to a message channel 0 has transmitted Channel 1 receives a message which channel 0 has transmitted on the CAN bus and then transmits an ACK in the ACK field After that channel 0 receives the ACK To avoid this make channel 1 which is not currently used for transmission the listen only mode TST 2 0 B 001 or the reset state MCR0 1 With this setting only a channel which transmits a m...

Page 1020: ...Section 19 Controller Area Network RCAN TL1 Rev 0 50 May 18 2006 Page 990 of 1588 REJ09B0313 0050 ...

Page 1021: ...ngle mode A D conversion on one channel Multi mode A D conversion on one to four channels or on one to eight channels Scan mode Continuous A D conversion on one to four channels or on one to eight channels Data registers 8 Conversion results are held in a 16 bit data register for each channel Sample and hold function A D conversion start methods 3 Software Conversion start trigger from multi funct...

Page 1022: ...t trigger from MTU2 AVss ADCSR AVcc ADDRA ADDRB ADDRC ADDRD Multiplexer Control circuit Comparator Sample and hold circuit 10 bit A D Successive approximation register Peripheral bus ADCSR ADDRA ADDRB ADDRC ADDRD Legend A D control status register A D data register A A D data register B A D data register C A D data register D ADDRE ADDRF ADDRG ADDRH A D data register E A D data register F A D data...

Page 1023: ...round pin AVss Input Analog ground pin and A D conversion reference ground Analog reference voltage pin AVref Input A D converter reference voltage pin Analog input pin 0 AN0 Input Analog input pin 1 AN1 Input Analog input pin 2 AN2 Input Analog input pin 3 AN3 Input Analog input pin 4 AN4 Input Analog input pin 5 AN5 Input Analog input pin 6 AN6 Input Analog input pin 7 AN7 Input Analog input A D...

Page 1024: ...ze A D data register A ADDRA R H 0000 H FFFE5800 16 A D data register B ADDRB R H 0000 H FFFE5802 16 A D data register C ADDRC R H 0000 H FFFE5804 16 A D data register D ADDRD R H 0000 H FFFE5806 16 A D data register E ADDRE R H 0000 H FFFE5808 16 A D data register F ADDRF R H 0000 H FFFE580A 16 A D data register G ADDRG R H 0000 H FFFE580C 16 A D data register H ADDRH R H 0000 H FFFE580E 16 A D c...

Page 1025: ...rved bits that are always read as 0 Access to ADDR in 8 bit units is prohibited ADDR must always be accessed in 16 bit units Table 20 3 indicates the pairings of analog input channels and ADDR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R Bit Initial value R W R R R R R R R R R R R R Bit Bit Name Initial Value R W Description 15 to 6 All 0 R Bit data 10 bits 5 to 0 ...

Page 1026: ...ST TRGS 3 0 CKS 1 0 MDS 2 0 CH 2 0 Bit Bit Name Initial Value R W Description 15 ADF 0 R W A D End Flag Status flag indicating the end of A D conversion Clearing conditions Cleared by reading ADF while ADF 1 then writing 0 to ADF Cleared when DMAC is activated by ADI interrupt and ADDR is read Setting conditions A D conversion ends in single mode A D conversion ends for the selected channels in mu...

Page 1027: ...performed until this bit is cleared to 0 by software by a power on reset as well as by a transition to deep standby mode software standby mode or module standby mode 12 0 R Reserved This bit is always read as 0 The write value should always be 0 11 to 8 TRGS 3 0 0000 R W Timer Trigger Select These bits enable or disable starting of A D conversion by a trigger signal 0000 Start of A D conversion by...

Page 1028: ...Conversion time 138 states maximum clock Pφ 4 01 Conversion time 274 states maximum clock Pφ 8 10 Conversion time 546 states maximum clock Pφ 16 11 Setting prohibited 5 to 3 MDS 2 0 000 R W Multi scan Mode These bits select the operating mode for A D conversion 0xx Single mode 100 Multi mode A D conversion on 1 to 4 channels 101 Multi mode A D conversion on 1 to 8 channels 110 Scan mode A D conver...

Page 1029: ...0 AN0 000 AN0 001 AN1 001 AN0 AN1 001 AN0 AN1 010 AN2 010 AN0 to AN2 010 AN0 to AN2 011 AN3 011 AN0 to AN3 011 AN0 to AN3 100 AN4 100 AN4 100 AN0 to AN4 101 AN5 101 AN4 AN5 101 AN0 to AN5 110 AN6 110 AN4 to AN6 110 AN0 to AN6 111 AN7 111 AN4 to AN7 111 AN0 to AN7 2 to 0 CH 2 0 000 R W Note These bits must be set so that ADCSR_0 and ADCSR_1 do not have the same analog inputs Legend x Don t care Not...

Page 1030: ...rsion for the selected channel starts when the ADST bit in ADCSR is set to 1 by software MTU2 or external trigger input 2 When A D conversion is completed the A D conversion result is transferred to the A D data register corresponding to the channel 3 After A D conversion has completed the ADF bit in ADCSR is set to 1 If the ADIE bit is set to 1 at this time an ADI interrupt request is generated 4...

Page 1031: ... D conversion is started ADST 1 2 When A D conversion is completed the A D conversion result is transferred into ADDRB At the same time the ADF flag is set to 1 the ADST bit is cleared to 0 and the A D converter becomes idle 3 Since ADF 1 and ADIE 1 an ADI interrupt is requested 4 The A D interrupt handling routine starts 5 The routine reads ADF 1 and then writes 0 to the ADF flag 6 The routine re...

Page 1032: ...Channel 3 AN3 operating Waiting Waiting Clear A D conversion result 1 A D conversion result 2 Note Vertical arrows indicate instruction execution by software Read conversion result Read conversion result Waiting Waiting Set Set Set Clear Conversion time 1 Conversion time 2 Waiting Waiting A D conversion starts Figure 20 2 Example of A D Converter Operation Single Mode One Channel AN1 Selected ...

Page 1033: ... to the ADF bit A D conversion is to be performed once on all the specified channels The conversion results are transferred for storage into the A D data registers corresponding to the channels When the operating mode or analog input channel selection must be changed during A D conversion to prevent incorrect operation first clear the ADST bit to 0 to halt A D conversion After making the necessary...

Page 1034: ...rating Channel 1 AN1 operating Channel 2 AN2 operating Channel 3 AN3 operating Set Clear A D conversion result 2 A D conversion result 3 Conversion time 1 A D conversion result 1 A D conversion Note Vertical arrows indicate instruction execution by software Conversion time 2 Conversion time 3 Clear Figure 20 3 Example of A D Converter Operation Multi Mode Three Channels AN0 to AN2 Selected ...

Page 1035: ...the A D converter becomes idle The ADF bit is cleared by reading ADF while ADF 1 then writing 0 to the ADF bit When the operating mode or analog input channel selection must be changed during A D conversion to prevent incorrect operation first clear the ADST bit to 0 to halt A D conversion After making the necessary changes set the ADST bit to 1 A D conversion will start again from the first chann...

Page 1036: ...e repeated the ADF flag is kept to 1 When the ADST bit is cleared to 0 A D conversion stops The ADF bit is cleared by reading ADF while ADF 1 then writing 0 to the ADF bit If both the ADF flag and ADIE bit are set to 1 while steps 2 to 4 are repeated an ADI interrupt is requested at all times To generate an interrupt on completing conversion of the third channel clear the ADF bit to 0 after an int...

Page 1037: ...Channel 3 AN3 operating Waiting A D conversion result 1 A D conversion result 4 A D conversion result 2 A D conversion result 3 Clear 1 Clear 1 Set 1 Continuous A D conversion Notes 1 Vertical arrows indicate instruction execution by software 2 A D conversion data is invalid Conversion time 1 Conversion time 2 Conversion time 3 Conversion time 4 Conversion time 5 Figure 20 4 Example of A D Convert...

Page 1038: ... conversion is the same as when 1 is written to the ADST bit by software 20 4 5 Input Sampling and A D Conversion Time The A D converter has a built in sample and hold circuit The A D converter samples the analog input at the A D conversion start delay time tD after the ADST bit in ADCSR is set to 1 then starts conversion Figure 20 5 shows the A D conversion timing Table 20 4 indicates the A D con...

Page 1039: ...conversion start delay time Input sampling time A D conversion time Figure 20 5 A D Conversion Timing Table 20 4 A D Conversion Time Single Mode CKS1 0 CKS1 1 CKS0 0 CKS0 1 CKS0 0 Item Symbol Min Typ Max Min Typ Max Min Typ Max A D conversion start delay time tD 11 14 19 26 35 50 Input sampling time tSPL 33 65 129 A D conversion time tCONV 135 138 267 274 531 546 Note Values in the table are the n...

Page 1040: ...r Input Timing A D conversion can also be externally triggered When the TRGS 3 0 bits in ADCSR are set to B 1001 an external trigger is input to the ADTRG pin The ADST bit in ADCSR is set to 1 at the falling edge of the ADTRG pin thus starting A D conversion Other operations regardless of the operating mode are the same as when the ADST bit has been set to 1 by software Figure 20 6 shows the timin...

Page 1041: ...nse to an ADI interrupt enables continuous conversion to be achieved without imposing a load on software In single mode set the DMAC so that DMA transfer initiated by an ADI interrupt is performed only once In the case of A D conversion on multiple channels in scan mode or multi mode setting the DMA transfer count to one causes DMA transfer to finish after transferring only one channel of data To ...

Page 1042: ...000 in the figure to B 000000001 001 in the figure figure 20 7 item 1 Full scale error is the deviation between actual and ideal A D conversion characteristics when the digital output value changes from B 1111111110 110 in the figure to the maximum B 1111111111 111 in the figure figure 20 7 item 2 Quantization error is the intrinsic error of the A D converter and is expressed as 1 2 LSB figure 20 ...

Page 1043: ...Vcc and AVss PVss Do not leave the AVcc and AVss pins open when the A D converter or D A converter is not in use and in software standby mode When not in use connect AVcc to the power supply PVcc and AVss to the ground PVss 3 Setting range of AVref input voltage Set the reference voltage range of the AVref pin as 3 0 V AVref AVcc 20 7 3 Notes on Board Design In board design digital circuitry and a...

Page 1044: ...wn also includes a CR filter to suppress noise This circuit is shown as an example the circuit constants should be selected according to actual application conditions Figure 20 9 shows an equivalent circuit diagram of the analog input ports and table 20 7 lists the analog input pin specifications This LSI AVref AVcc AN0 to AN7 AVss 1 1 2 Rin 100 Ω 0 1 µF Notes Values are reference values 2 Rin Inp...

Page 1045: ...ble the A D converter s sample and hold circuit input capacitance to be charged within the sampling time if the sensor output impedance exceeds 5 kΩ charging may be insufficient and it may not be possible to guarantee A D conversion precision However for A D conversion in single mode with a large capacitance provided externally for A D conversion in single mode the input load will essentially comp...

Page 1046: ...D converter equivalent circuit Figure 20 10 Example of Analog Input Circuit 20 7 6 Influences on Absolute Precision Adding capacitance results in coupling with GND and therefore noise in GND may adversely affect absolute precision Be sure to connect AVss etc to an electrically stable GND Care is also required to insure that filter circuits do not communicate with digital signals on the mounting bo...

Page 1047: ...n time of 10 µs with 20 pF load Output voltage of 0 V to AVref D A output hold function in software standby mode Module standby mode can be set DADR0 AVcc AVref DA0 DA1 DADR1 DACR AVss Module data bus Peripheral bus 8 bit D A Control circuit Bus interface Legend DADR0 D A data register 0 DADR1 D A data register 1 DACR D A control register Figure 21 1 Block Diagram of D A Converter ...

Page 1048: ...onverter Table 21 1 Pin Configuration Pin Name Symbol I O Function Analog power supply pin AVcc Input Analog block power supply Analog ground pin AVss Input Analog block ground Analog reference voltage pin AVref Input D A conversion reference voltage Analog output pin 0 DA0 Output Channel 0 analog output Analog output pin 1 DA1 Output Channel 1 analog output ...

Page 1049: ...ata register 1 DADR1 R W H 00 H FFFE6801 8 16 D A control register DACR R W H 1F H FFFE6802 8 16 21 3 1 D A Data Registers 0 and 1 DADR0 and DADR1 DADR is an 8 bit readable writable register that stores data to which D A conversion is to be performed Whenever analog output is enabled the values in DADR are converted and output to the analog output pins DADR is initialized to H 00 by a power on res...

Page 1050: ...nel 1 DA1 is disabled 1 D A conversion of channel 1 is enabled Analog output of channel 1 DA1 is enabled 6 DAOE0 0 R W D A Output Enable 0 Controls D A conversion and analog output for channel 0 0 Analog output of channel 0 DA0 is disabled 1 D A conversion of channel 0 is enabled Analog output of channel 0 DA0 is enabled 5 DAE 0 R W D A Enable Used together with the DAOE0 and DAOE1 bits to control...

Page 1051: ...E0 Description 0 D A conversion is disabled 0 1 D A conversion of channel 0 is enabled and D A conversion of channel 1 is disabled 0 D A conversion of channel 1 is enabled and D A conversion of channel 0 is disabled 0 1 1 D A conversion of channels 0 and 1 is enabled 0 D A conversion is disabled 0 1 0 1 1 1 D A conversion of channels 0 and 1 is enabled ...

Page 1052: ...e analog output pin DA0 after the conversion time tDCONV has elapsed The conversion result continues to be output until DADR0 is written to again or the DAOE0 bit is cleared to 0 The output value is expressed by the following formula Contents of DADR 256 AVref 3 If DADR0 is written to again the conversion is immediately started The conversion result is output after the conversion time tDCONV has e...

Page 1053: ...he analog power supply current is equal to as during D A conversion If the analog power supply current needs to be reduced in software standby mode clear the DAOE0 DAOE1 and DAE bits to 0 to disable the D A outputs 21 5 3 Setting Analog Input Voltage The reliability of this LSI may be adversely affected if the following voltage ranges are exceeded 1 AVcc and AVss input voltages Input voltages AVcc...

Page 1054: ...Section 21 D A Converter DAC Rev 0 50 May 18 2006 Page 1024 of 1588 REJ09B0313 0050 ...

Page 1055: ... or write in sector units 512 16 bytes and ECC processing executed An access unit of 2048 64 bytes referred to as a page is used in some datasheets for AND type flash memory In this manual an access unit of 512 16 bytes referred to as a sector is always used Read or write in byte units Supports up to 1 Gbit of flash memory The AND type flash memory with 1 Gbit indicate the one of AG AND type 2 NAN...

Page 1056: ...r check is performed for a sector 512 byte data 16 byte control code Note that the ECC code generation in the 16 byte control code and the number of bytes to be checked differ depending on the specifications Error correction capability is up to three errors In a write operation an ECC code is generated for data and control code prior to the ECC The control code following the ECC is not considered ...

Page 1057: ...e 10 Access Time The operating frequency of the FLCTL pins can be specified by the FCKSEL bit and the QTSEL bit in the common control register FLCMNCR regardless of the operating frequency of the peripheral bus Before changing the CPG specification the FLCTL must be placed in a module stop state In NAND type flash memory the FSC and FWE pins operate with the frequency on the pins which CPG designa...

Page 1058: ... FLASH FIFO 256 bytes 32 8 8 8 8 32 32 FLCTL CPG FCKSEL 1 1 2 1 4 FCLK DMA transfer requests 2 lines Peripheral bus Peripheral bus interface Interrupts 4 lines Registers State machine Transmission reception control Control signal Note FCLK is an operating clock for interface signals with flash memory It is specified by the CPG QTSEL Peripheral clock Pφ Figure 22 1 FLCTL Block Diagram ...

Page 1059: ... FOE Output enable Output ALE OE Address Latch Enable ALE Asserted when an address is output and negated when data is input or output Output Enable OE Asserted when data is input or when a status is read FSC Serial clock Output RE SC Read Enable RE Reads data at the falling edge of RE Serial Clock SC Inputs or outputs data synchronously with the SC FWE Write enable Output WE WE Write Enable Flash ...

Page 1060: ...W H 0000 0000 H FFFF F008 32 Address register FLADR R W H 0000 0000 H FFFF F00C 32 Address register 2 FLADR2 R W H 0000 0000 H FFFF F03C 32 Data register FLDATAR R W H 0000 0000 H FFFF F010 32 Data counter register FLDTCNTR R W H 0000 0000 H FFFF F014 32 Interrupt DMA control register FLINTDMACR R W H 0000 0000 H FFFF F018 32 Ready busy timeout setting register FLBSYTMR R W H 0000 0000 H FFFF F01C...

Page 1061: ...R R W R W R W R W R W R R R R R R W R R R W SNAND QT SEL FCK SEL ECCPOS 1 0 ACM 1 0 NAND WF CE0 TYPE SEL Bit Bit Name Initial Value R W Description 31 to 19 All 0 R Reserved These bits are always read as 0 The write value should always be 0 18 SNAND 0 R W Large Capacity NAND Flash Memory Select This bit is used to specify 1 Gbit or larger NAND flash memory with the page configuration of 2048 64 by...

Page 1062: ...es it as FCLK QTSEL 1 FCKSEL 1 Setting prohibited 16 0 R Reserved This bit is always read as 0 The write value should always be 0 15 FCKSEL 0 R W Flash Clock Select Selects the dividing rate of clock FCLK in the flash memory This bit is used together with QTSEL Refer to the description of QTSEL 14 0 R Reserved This bit is always read as 0 The write value should always be 0 13 12 ECCPOS 1 0 00 R W ...

Page 1063: ...peration 0 Performs address or data input output in one FCLK cycle 1 Performs address or data input output in two FCLK cycles 8 to 4 All 0 R Reserved These bits are always read as 0 The write value should always be 0 3 CE0 0 R W Chip Enable 0 0 Disables the chip Outputs high level to the FCE pin 1 Enables the chip Outputs low level to the FCE pin 2 1 All 0 R Reserved These bits are always read as ...

Page 1064: ...W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W ADR CNT2 SCTCNT 19 16 ADR MD CDS RC DOSR SEL RW DOA DR ADRCNT 1 0 DOC MD2 DOC MD1 SCTCNT 15 0 Bit Bit Name Initial Value R W Description 31 ADRCNT2 0 R Address Issue Byte Count Specification 2 Specifies the number of bytes for the address data to be issued in address stage This bit is used...

Page 1065: ... R W Data Buffer Specification Specifies the data buffer to be read from or written to in the data stage in command access mode 0 Specifies FLDATAR as the data buffer 1 Specifies FLDTFIFO as the data buffer 24 DOSR 0 R W Status Read Check Specifies whether or not the status read is performed after the second command has been issued in command access mode 0 Performs no status read 1 Performs status...

Page 1066: ...econd command stage is executed in command access mode 0 Does not execute the second command stage 1 Executes the second command stage 16 DOCMD1 0 R W First Command Stage Execution Specification Specifies whether or not the first command stage is executed in command access mode 0 Does not execute the first command stage 1 Executes the first command stage 15 to 0 SCTCNT 15 0 H 0000 R W Sector Trans...

Page 1067: ...0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W CMD 15 8 CMD 7 0 Bit Bit Name Initial Value R W Description 31 to 16 All 0 R Reserved These bits are always read as 0 The write value should always be 0 15 to 8 CMD 15 8 H 00 R W Specify a...

Page 1068: ... 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W ADR 31 24 ADR 23 16 ADR 15 8 ADR 7 0 Bit Bit Name Initial Value R W Description 31 to 24 ADR 31 24 H 00 R W Fourth Address Data Specify 4th data to be output to flash memory as an address in command access mode 23 to 16 ADR 23 16 H 00 R ...

Page 1069: ... 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W ADR 25 16 ADR 15 0 Bit Bit Name Initial Value R W Description 31 to 26 All 0 R Reserved These bits are always read as 0 The write value should always be 0 25 to 0 ADR 25 0 H 000 0000 R W Physical Sector Address Specify a physical sector number to be accessed in sector access mode The physical sector number is converted into a...

Page 1070: ...R W Bit Initial value R W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R W R W R W R W R W R W R W R W ADR 7 0 Bit Bit Name Initial Value R W Description 31 to 8 All 0 R Reserved These bits are always read as 0 The write value should always be 0 7...

Page 1071: ... bit values are used when the CPU reads from or writes to FLECFIFO In FLECFIFO read these bits specify the number of longwords of the data that can be read from FLECFIFO In FLECFIFO write these bits specify the number of longwords of unoccupied area that can be written in FLECFIFO 23 to 16 DTFLW 7 0 H 00 R FLDTFIFO Access Count Specify the number of longwords in FLDTFIFO to be read or written Thes...

Page 1072: ...W R W R W R W R W R W R W R W R W R W R W R W R W DT 31 24 DT 23 16 DT 15 8 DT 7 0 Bit Bit Name Initial Value R W Description 31 to 24 DT 31 24 H 00 R W Fourth Data Specify the 4th data to be input or output via the NAF7 to NAF0 pins In write Specify write data In read Store read data 23 to 16 DT 23 16 H 00 R W Third Data Specify the 3rd data to be input or output via the NAF7 to NAF0 pins In writ...

Page 1073: ... 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R W R R R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R W R W R W R W R W R W R W R W R W R W ECER INTE FIFOTRG 1 0 AC1 CLR AC0 CLR DREQ1 EN DREQ0 EN EC ERB ST ERB BTO ERB TRR EQF1 TRR EQF0 STER INTE RBER INTE TE INTE TR INTE1 TR INTE0 Bit Bit Name Initial Value R W Description 31 to 25 All 0 R Reserved These bits are a...

Page 1074: ...f data or issue a DMA transfer request to the CPU when FLDTFIFO stores 16 bytes of data In flash memory programming 00 Issue an interrupt to the CPU when FLDTFIFO has empty area of 4 bytes or more do not set DMA transfer 01 Issue an interrupt or a DMA transfer request to the CPU when FLDTFIFO has empty area of 16 bytes or more 10 Issue an interrupt to the CPU when FLDTFIFO has empty area of 128 by...

Page 1075: ...fer request issued from FLECFIFO 16 DREQ0EN 0 R W FLDTFIFODMA Request Enable Enables or disables the DMA transfer request issued from FLDTFIFO 0 Disables the DMA transfer request issued from the FLDTFIFO 1 Enables the DMA transfer request issued from the FLDTFIFO 15 to 10 All 0 R Reserved These bits are always read as 0 The write value should always be 0 9 ECERB 0 R W ECC Error Indicates the resul...

Page 1076: ...imeout error occurs the bits RBTIMCNT 19 0 in FLBSYCNT are decremented to 0 This bit is a flag 1 cannot be written to this bit Only 0 can be written to clear the flag 0 Indicates that no timeout error occurs 1 Indicates that a timeout error occurs 6 TRREQF1 0 R W FLECFIFO Transfer Request Flag Indicates that a transfer request is issued from FLECFIFO This bit is a flag 1 cannot be written to this ...

Page 1077: ...les the interrupt request to the CPU by a timeout error 1 Enables the interrupt request to the CPU by a timeout error 2 TEINTE 0 R W Transfer End Interrupt Enable Enables or disables an interrupt request to the CPU when a transfer has been ended TREND bit in FLTRCR 0 Disables the transfer end interrupt request to the CPU 1 Enables the transfer end interrupt request to the CPU 1 TRINTE1 0 R W FLECF...

Page 1078: ...ing Register FLBSYTMR FLBSYTMR is a 32 bit readable writable register that specifies the timeout time when the FRB pin is busy Bit Initial value R W Bit Initial value R W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W...

Page 1079: ... an interrupt is enabled by the RBERINTE bit in FLINTDMACR Bit Initial value R W Bit Initial value R W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R STAT 7 0 RBTIMCNT 19 16 RBTIMCNT 15 0 Bit Bit Name Initial Value R W Description 31...

Page 1080: ...6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W DTFO 31 24 DTFO 23 16 DTFO 15 8 DTFO 7 0 Bit Bit Name Initial Value R W Description 31 to 24 DTFO 31 24 H 00 R W First Data Specify 1st data to be input or output via t...

Page 1081: ...is register must be specified as the destination source Note that the direction of read or write specified by the SELRW bit in FLCMDCR must match that specified in this register When transferring 16 byte DMA access FLECFIFO from the address on the 16 byte address boundary Bit Initial value R W Bit Initial value R W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1...

Page 1082: ...ead Store read data 23 to 16 ECFO 23 16 H 00 R W Second Data Specify 2nd data to be input or output via the NAF7 to NAF0 pins In write Specify write data In read Store read data 15 to 8 ECFO 15 8 H 00 R W Third Data Specify 3rd data to be input or output via the NAF7 to NAF0 pins In write Specify write data In read Store read data 7 to 0 ECFO 7 0 H 00 R W Fourth Data Specify 4th data to be input o...

Page 1083: ... bit to 0 Bit Initial value R W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R R R R R R R W R W TR END TR STRT Bit Bit Name Initial Value R W Description 7 to 2 All 0 R Reserved These bits are always read as 0 The write value should always be 0 1 TREND 0 R W Processing End Flag Bit Indicates that the processing performed in the specified access mode has been completed The write value should always be 0 0 TRST...

Page 1084: ...command issue stage program start command Status read stage AND type flash memory programming access is achieved by executing these five stages sequentially An access to flash memory is completed at the end of the final stage status read stage Command Address Data input Program start CDE WE SC H 10 H 11 SA 1 SA 2 CA 1 CA 2 H 40 OE Program First command Address Data Second command Status read Figur...

Page 1085: ...ntroller FLCTL Rev 0 50 May 18 2006 Page 1055 of 1588 REJ09B0313 0050 22 4 2 Operating Modes Two operating modes are supported Command access mode Sector access mode The ECC generation and error check are performed in sector access mode ...

Page 1086: ...leted Not required in sector access Not required in reading Not required when FLDTFIFO is used Not required in reading Not required in reading Start the transfer Wait until the transfter is completed Yes No FLTRCR All 0 Yes No TREND in FLTRCR 1 Yes No Except FLTRCR register settings completed Set FLCMNCR Set FLCMDCR Set FLCMCDR Set FLADR Set FLDTCNTR Set FLDATAR Set FLCMNCR Set FLINTDMACR Set FLBS...

Page 1087: ...igures 22 4 and 22 5 show examples of read operation for AND type flash memory In these examples the first command is specified as H 00 and address data length is specified as 2 bytes SA1 and SA2 Only SA1 and SA2 are specified while CA1 and CA2 are not specified In addition the number of read bytes is specified as 4 bytes in the data counter and H FF is specified as the second command OE WE CDE SC...

Page 1088: ...ures 22 6 and 22 7 show examples of programming operation for AND type flash memory OE WE CDE SC I O7 to I O0 R B 1 2 3 4 H 10 SA1 SA2 Figure 22 6 Programming Operation Timing for AND Type Flash Memory 1 OE WE CDE SC I O7 to I O0 R B H 40 ST Figure 22 7 Programming Operation Timing for AND Type Flash Memory 2 ...

Page 1089: ...as H 00 address data length is specified as 3 bytes and the number of read bytes is specified as 8 bytes in the data counter CLE ALE WE RE I O7 to I O0 R B H 00 A2 A1 A3 1 2 3 4 5 8 Figure 22 8 Read Operation Timing for NAND Type Flash Memory 1 Figures 22 9 and 22 10 show examples of programming operation for NAND type flash memory CLE ALE WE RE I O7 to I O0 R B H 80 A2 A1 A3 1 2 3 4 5 8 Figure 22...

Page 1090: ...ry 2048 64 Bytes Access Figure 22 11 shows an example of read operation for NAND type flash memory 2048 64 bytes In this example the first command is specified as H 00 the second command is specified as H 30 and address data length is specified as 4 bytes The number of read bytes is specified as 4 bytes in the data counter CLE ALE WE RE I O7 to I O0 R B H 00 A1 A2 A3 A4 1 2 3 4 H 30 Figure 22 11 R...

Page 1091: ...show examples of programming operation for NAND type flash memory 2048 64 bytes CLE ALE WE RE I O7 to I O0 R B H 80 A1 A2 A3 A4 1 2 3 4 H 10 Figure 22 12 Programming Operation Timing for NAND Type Flash Memory 1 CLE ALE WE RE I O7 to I O0 R B H 10 H 70 Status Figure 22 13 Programming Operation Timing for NAND Type Flash Memory 2 ...

Page 1092: ... stored in FLDTFIFO and 16 byte control code is stored in FLECFIFO the DREQ1EN and DREQ0EN bits in FLINTDMACR can be set to transfer by the DMA Figure 22 14 shows the relationship of DMA transfer between sectors in flash memory data and control code and memory on the address space FLCTL FLDT FIFO FLEC FIFO Flash memory Data 512 bytes Control code 16 bytes DMA channel 0 transfer DMA channel 1 trans...

Page 1093: ...25 18 are valid Set the invalid bit to 0 depending on the capacity of flash memory FLADR 1 0 specify the boundary address for column address in the unit of 512 16 bytes When NAND type flash memory 2048 64 bytes is used set FLADR 1 0 as follows 00 0 byte 01 512 16 bytes 10 1024 32 bytes 11 1536 48 bytes Legend CA Column address SA Sector address Legend CA Column address Row Row address page address...

Page 1094: ...12 0 0 11 11 12 13 13 40 40 300 12 300 1 13 28 Physical sector Values specified in registers by the CPU Physical sector specification register Sector transfer count specification register Sector 0 to sector 11 are transferred Sector 12 is transferred Sector 13 to sector 40 are transferred Logical sector Transfer start Transfer start Transfer start FLADR ADR17 to 0 FLCMDCR SCTCNT Figure 22 16 Secto...

Page 1095: ... the STERINTE bit in FLINTDMACR is enabled 1 Status Read of AND Type Flash Memory The status register of AND type flash memory can be read by asserting the output enable signal OE OE 0 If programming is executed in command access mode or sector access mode while the DOSR bit in FLCMDCR is set to 1 the FLCTL automatically asserts the OE signal and reads the status register of AND type flash memory ...

Page 1096: ...bit in FLCMDCR is set to 1 the FLCTL automatically inputs command H 70 to NAND type flash memory and reads the status register of NAND type flash memory When the status register of NAND type flash memory is read the I O7 to I O0 pins indicate the following information as described in table 22 4 Table 22 4 Status Read of NAND Type Flash Memory I O Status definition Description I O7 Program protecti...

Page 1097: ... enable bit Note that the status error ready busy timeout error and ECC error use the common FLSTE interrupt to the CPU Table 22 5 FLCTL Interrupt Requests Interrupt Source Interrupt Flag Enable Bit Description Priority STERB STERINTE Status error BTOERB RBERINTE Ready busy timeout error FLSTE interrupt ECERB ECERINTE ECC error FLTEND interrupt TREND TEINTE Transfer end FLTRQ0 interrupt TRREQF0 TR...

Page 1098: ...ummarizes DMA transfer enable or disable states in each access mode Table 22 6 DMA Transfer Specifications Sector Access Mode Command Access Mode FLDTFIFO DMA transfer enabled DMA transfer enabled FLECFIFO DMA transfer enabled DMA transfer disabled In little endian form these bits should not be used because a 16 byte DMA transfer causes a data replacement in longword units For details on DMAC sett...

Page 1099: ...h Speed Operation The USB host controller and USB function controller are incorporated The USB host controller and USB function controller can be switched by register settings Both high speed transfer 480 Mbps and full speed transfer 12 Mbps are supported High speed full speed USB transceiver shared by the USB host and USB function is incorporated 2 Reduced Number of External Pins and Space Saving...

Page 1100: ... of the USB Host Controller Exclusive communication with a peripheral device with one to one connection Automatic scheduling for SOF and packet transmissions Programmable intervals for isochronous and interrupt transfers 7 Features of the USB Function Controller Control transfer stage control function Device state control function Auto response function for SET_ADDRESS request NAK response interru...

Page 1101: ...able connection monitor pin This pin should be connected directly to the Vbus of the USB bus Whether the Vbus is connected or disconnected can be detected If this pin is not connected with the Vbus of the USB bus it should be supplied with 5 V It should be supplied with 5 V also when the host controller function is selected At this time Vbus is not provided to the connected device Reference resist...

Page 1102: ... pins Transceiver block digital pin power supply USBDPVcc Input Power supply for pins Transceiver block digital pin ground USBDPVss Input Ground for pins Transceiver block analog core power supply USBAVcc Input Power supply for the core Transceiver block analog core ground USBAVss Input Ground for the core Transceiver block digital core power supply USBDVcc Input Power supply for the core Power su...

Page 1103: ...R W H 00000000 H FFFC 1C10 32 D0FIFO port register D0FIFO R W H 00000000 H FFFC 1C14 32 D1FIFO port register D1FIFO R W H 00000000 H FFFC 1C18 32 CFIFO port select register CFIFOSEL R W H 0000 H FFFC 1C1E 16 CFIFO port control register CFIFOCTR R W H 0000 H FFFC 1C20 16 CFIFO port SIE register CFIFOSIE R W H 0000 H FFFC 1C22 16 D0FIFO port select register D0FIFOSEL R W H 0000 H FFFC 1C24 16 D0FIFO...

Page 1104: ...SB request index register USBINDX R H 0000 H FFFC 1C58 16 USB request length register USBLENG R H 0000 H FFFC 1C5A 16 DCP configuration register DCPCFG R W H 0000 H FFFC 1C5C 16 DCP maximum packet size register DCPMAXP R W H 0040 H FFFC 1C5E 16 DCP control register DCPCTR R W H 0040 H FFFC 1C60 16 Pipe window select register PIPESEL R W H 0000 H FFFC 1C64 16 Pipe configuration register PIPECFG R W...

Page 1105: ... DCFM DMRPD DPRPU FSRPC USBE Bit Bit Name Initial Value R W Description 15 to 8 All 0 R Reserved These bits are always read as 0 The write value should always be 0 7 HSE 0 R W High Speed Operation Enable 0 High speed operation is disabled 1 High speed operation is enabled detected by this module 6 DCFM 0 R W Controller Function Select Selects the host controller function or function controller fun...

Page 1106: ...is enabled by software 1 0 R Reserved This bit is always read as 0 The write value should always be 0 0 USBE 0 R W USB Block Operation Enable Enables a software reset for this module When the system clears this bit to 0 this module resets the registers to be initialized by a software reset to the initial values When USBE 0 is being set the system cannot write to the registers or bits to be initial...

Page 1107: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R SOFEN LNST 1 0 Bit Bit Name Initial Value R W Description 15 to 6 All 0 R Reserved These bits are always read as 0 The write value should always be 0 5 SOFEN 0 R SOF Issuance Enable Indicates whether SOF issuance by this module internal circuit is enabled or disabled after the UACT bit in DVSTCTR is written to by software in host mode ope...

Page 1108: ...USBCLK by setting the FSRPC bit in SYSCFG After a power on reset D and D line status can be confirmed prior to the USBCLK supply by setting the FSRPC bit to 1 Once USBCLK is supplied software setting is not required Note Depending on the D and D line status Table 23 3 USB Data Bus Line Status LNST 1 LNST 0 During Full Speed Operation During High Speed Operation During Chirp Operation 0 0 SE0 Squel...

Page 1109: ...e always read as 0 The write value should always be 0 8 WKUP 0 R W Wakeup Output This bit is used to control remote wakeup signal output to the USB bus The module controls the output time of a remote wakeup signal When this bit is set to 1 this module clears this bit to 0 after outputting the 10 ms K state According to the USB specification the USB bus idle state must be kept for 5 ms or longer be...

Page 1110: ... should be controlled by software This bit should be cleared to 0 after the USB bus reset time has elapsed 0 USB bus reset signal output is stopped 1 USB bus reset signal is output 5 RESUME 0 R W Resume Output Outputs a resume signal to the USB bus by setting this bit to 1 0 Resume signal output is stopped 1 Resume signal is output 4 UACT 0 R W USB Bus Enable Controls the SOF or µSOF packet transm...

Page 1111: ...ed the HSE bit is set to 1 this module executes the reset handshake protocol RHST 01 during the execution and feeds back the execution results to these bits 11 for high speed operation or 10 for full speed operation 00 Communication speed not decided 01 Reset handshake is being handled 10 Full speed operation established 11 High speed operation established Note If RHST is not established even thou...

Page 1112: ... 3 0 Bit Bit Name Initial Value R W Description 15 to 4 All 0 R Reserved These bits are always read as 0 The write value should always be 0 3 to 0 UTST 3 0 0000 R W Test Mode Table 23 4 shows test mode operation of this module These bits control the USB test signal output in high speed mode These bits are valid only during high speed operation RHST 11 in DVSTCTR should be confirmed before use UTST...

Page 1113: ...B0313 0050 Table 23 4 Test Mode Operation UTST Bit Setting Test Mode Functions of Function Controller Selected Functions of Host Controller Selected Normal operation 0000 0000 Test_J 0001 1001 Test_K 0010 1010 Test_SE0_NAK 0011 1011 Test_Packet 0100 1100 Reserved 0101 to 0111 1101 to 1111 ...

Page 1114: ...y a power on reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 R R R R R R R R R R R R RW R W R W R W FWAIT 3 0 Bit Bit Name Initial Value R W Description 15 to 4 All 0 R Reserved These bits are always read as 0 The write value should always be 0 3 to 0 FWAIT 3 0 1111 R W FIFO Port Access Wait Specification These bits specify the number of access wai...

Page 1115: ...W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W FIFOPORT 31 16 FIFOPORT 15 0 Bit Bit Name Initial Value R W Description 31 to 0 FIFOPORT 31 0 All 0 R W FIFO Port These bits are used to read receive data from the buffer memory and write transmit data to the buffer memory Notes 1 The DCP can access the buffer memory only through t...

Page 1116: ...umber should not be changed while the DMA transfer is enabled These registers are initialized by a power on reset or a software reset 1 CFIFOSEL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R W R W R R R R R W R R R W R W R W R W RCNT REW MBW 1 0 ISEL CURPIPE 2 0 Bit Bit Name Initial Value R W Description 15 RCNT 0 R W Read Count Mode 0 The DT...

Page 1117: ... bit width while data is being written to the buffer memory 9 to 6 All 0 R Reserved These bits are always read as 0 The write value should always be 0 5 ISEL 0 R W FIFO Port Access Direction When DCP is Selected 0 Reading from the buffer memory is selected 1 Writing to the buffer memory is selected This bit is valid only when DCP is selected with the CURPIPE bit This bit should be set according to...

Page 1118: ...T REW DCLRM DREQE MBW 1 0 TRENB TRCLR DEZPM CURPIPE 2 0 Bit Bit Name Initial Value R W Description 15 RCNT 0 R W Read Count Mode 0 The DTLN bit is cleared when all of the receive data has been read 1 The DTLN bit is decremented when the receive data is read 14 REW 0 R W Buffer Pointer Rewind 0 Invalid 1 The buffer pointer is rewound 13 DCLRM 0 R W Auto Buffer Memory Clear Mode Accessed after Speci...

Page 1119: ...TRENB 0 R W Transaction Counter Enable This bit is valid when the receiving direction reading from the buffer memory has been set for the pipe specified by the CURPIPE bits 0 Transaction counter function is invalid 1 Transaction counter function is valid 8 TRCLR 0 R W Transaction Counter Clear This bit is valid when the receiving direction reading from the buffer memory has been set for the pipe s...

Page 1120: ...nished the buffer in the CPU has been cleared and the FIFO port is accessible CFIFOCTR D0FIFOCTR and D1FIFOCTR are used for the corresponding FIFO ports These registers are initialized by a power on reset or a software reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W 1 R W 1 R R R R R R R R R R R R R R BVAL BCLR FRDY DTLN 11 0 Bit Bit Name Initi...

Page 1121: ...ort Ready Confirming the FIFO port state by reading this bit requires an access cycle of at least 450 ns after the pipe has been selected 0 FIFO port access is disabled 1 FIFO port access is enabled 12 0 R Reserved This bit is always read as 0 The write value should always be 0 11 to 0 DTLN 11 0 H 000 R Receive Data Length 2 The length of the receive data can be confirmed Notes 1 Only reading 0 an...

Page 1122: ... Description 15 TGL 0 R W Access Right Switch Sets the buffer memory on the SIE side to the CPU side Set the PID bits to NAK the PID bits in DCPCTR are cleared to 00 and check that the SIE does not access the buffer memory with the SBUSY bit that the SBUSY bit is cleared to 0 Then write the TGL bit toggle operation This bit is valid only for pipes for which the receiving direction reading from the...

Page 1123: ...sactions and read the number of transactions These registers are initialized by a power on reset and a software reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W TRNCNT 15 0 Bit Bit Name Initial Value R W Description 15 to 0 TRNCNT 15 0 H 0000 R W Transaction Counter These bits are valid...

Page 1124: ... DVSE CTRE BEMPE NRDYE BRDYE URST SADR SCFG SUSP WDST RDST CMPL SERR Bit Bit Name Initial Value R W Description 15 VBSE 0 R W VBUS Interrupts Enable 0 Interrupt output disabled 1 Interrupt output enabled 14 RSME 0 R W Resume Interrupts Enable 0 Interrupt output disabled 1 Interrupt output enabled 13 SOFE 0 R W Frame Number Update Interrupts Enable 0 Interrupt output disabled 1 Interrupt output ena...

Page 1125: ...d at transition to address state 1 DVST interrupt enabled at transition to address state 5 SCFG 0 R W Configuration State Transition Notifications Enable 0 DVST interrupt disabled at transition to configuration state 1 DVST interrupt enabled at transition to configuration state 4 SUSP 0 R W Suspend State Transition Notifications Enable 0 DVST interrupt disabled at transition to suspended state 1 D...

Page 1126: ...ntrol read transfer 1 CMPL 0 R W Control Transfer End Notifications Enable 0 CTST interrupt disabled at detection of the end of control transfer 1 CTST interrupt enabled at detection of the end of control transfer 0 SERR 0 R W Control Transfer Sequence Error Notifications Enable 0 CTST interrupt disabled at detection of control transfer sequence error 1 CTST interrupt enabled at detection of contr...

Page 1127: ... bit is always read as 0 The write value should always be 0 14 BCHGE 0 R W USB Bus Change Interrupt Enable 0 Interrupt output disabled 1 Interrupt output enabled 13 0 R Reserved This bit is always read as 0 The write value should always be 0 12 DTCHE 0 R W Disconnection Detection Interrupt Enable during Full Speed Operation The disconnection detection using this bit is valid only when the host con...

Page 1128: ...te value should always be 0 5 SIGNE 0 R W Setup Transaction Error Interrupt Enable 0 Interrupt output disabled 1 Interrupt output enabled 4 SACKE 0 R W Setup Transaction Normal Response Interrupt Enable 0 Interrupt output disabled 1 Interrupt output enabled 3 0 R Reserved This bit is always read as 0 The write value should always be 0 2 BRDYM 0 R W BRDY Interrupt Status Clear Timing Control for Ea...

Page 1129: ... R W Description 15 to 8 All 0 R Reserved These bits are always read as 0 The write value should always be 0 7 PIPE7BRDYE 0 R W BRDY interrupt Enable for PIPE7 0 Interrupt output disabled 1 Interrupt output enabled 6 PIPE6BRDYE 0 R W BRDY interrupt Enable for PIPE6 0 Interrupt output disabled 1 Interrupt output enabled 5 PIPE5BRDYE 0 R W BRDY interrupt Enable for PIPE5 0 Interrupt output disabled ...

Page 1130: ...ENB NRDYENB is a register that enables NRDY interrupts for each pipe This register is initialized by a power on reset or a software reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R W R W R W R W R W R W R W R W PIPE7 NRDYE PIPE6 NRDYE PIPE5 NRDYE PIPE4 NRDYE PIPE3 NRDYE PIPE2 NRDYE PIPE1 NRDYE PIPE0 NRDYE Bit Bit Name Initial Value...

Page 1131: ...abled 3 PIPE3NRDYE 0 R W NRDY Interrupt Enable for PIPE3 0 Interrupt output disabled 1 Interrupt output enabled 2 PIPE2NRDYE 0 R W NRDY Interrupt Enable for PIPE2 0 Interrupt output disabled 1 Interrupt output enabled 1 PIPE1NRDYE 0 R W NRDY Interrupt Enable for PIPE1 0 Interrupt output disabled 1 Interrupt output enabled 0 PIPE0NRDYE 0 R W NRDY Interrupt Enable for PIPE0 0 Interrupt output disabl...

Page 1132: ...PE PIPE1 BEMPE PIPE0 BEMPE Bit Bit Name Initial Value R W Description 15 to 8 All 0 R Reserved These bits are always read as 0 The write value should always be 0 7 PIPE7BEMPE 0 R W BEMP Interrupt Enable for PIPE7 0 Interrupt output disabled 1 Interrupt output enabled 6 PIPE6BEMPE 0 R W BEMP Interrupt Enable for PIPE6 0 Interrupt output disabled 1 Interrupt output enabled 5 PIPE5BEMPE 0 R W BEMP In...

Page 1133: ...PE2 0 Interrupt output disabled 1 Interrupt output enabled 1 PIPE1BEMPE 0 R W BEMP Interrupt Enable for PIPE1 0 Interrupt output disabled 1 Interrupt output enabled 0 PIPE0BEMPE 0 R W BEMP Interrupt Enable for PIPE0 0 Interrupt output disabled 1 Interrupt output enabled Note If an interrupt is enabled disabled after the interrupt status was cleared an interval of 80 ns or more is required ...

Page 1134: ...1 VBUS Interrupt Status 2 0 VBUS interrupts not generated 1 VBUS interrupts generated 14 RESM 0 R W 1 Resume Interrupt Status 2 0 Resume interrupts not generated 1 Resume interrupts generated 13 SOFR 0 R W 1 Frame Number Refresh Interrupt Status 2 0 SOF interrupts not generated 1 SOF interrupts generated 12 DVST 0 R W 1 Device State Transition Interrupt Status 2 0 Device state transition interrupt...

Page 1135: ...errupt Status This bit is cleared when all of the bits in BRDYSTS are cleared 0 BRDY interrupts not generated 1 BRDY interrupts generated 7 VBSTS 3 R VBUS Input Status The VBUS input status based on the VBSTS bit requires that chattering be eliminated using a control program 0 The VBUS pin is low level 1 The VBUS pin is high level 6 to 4 DVSQ 2 0 4 R Device State 000 Powered state 001 Default stat...

Page 1136: ...Control write no data status stage 110 Control transfer sequence error 111 Setting prohibited Notes 1 Only 0 can be written to 2 If multiple sources have occurred among the VBINT RESM SOFR DVST and CTRT bits an access cycle of at least 140 ns and 3 bus clock cycles is required in order to clear the bits in succession not simultaneously 3 This bit is initialized to 1 when the VBUS pin is high level...

Page 1137: ... 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R W R W R W R W R W R W R R R R R R R R R BCHG SOFR DTCH BEMP NRDY BRDY ATCH SIGN SACK Bit Bit Name Initial Value R W Description 15 0 R Reserved This bit is always read as 0 The write value should always be 0 14 BCHG 0 R W USB Bus Change Interrupt Status 0 BCHG interrupts not generated 1 BCHG interrupts generated 13 SOFR 0...

Page 1138: ... not generated 1 BRDY interrupts generated 7 ATCH 0 R W Connection Detection Interrupt Status The connection detection using this bit is valid only when the host controller function is selected 0 ATCH interrupts not generated 1 ATCH interrupts generated 6 0 R Reserved This bit is always read as 0 The write value should always be 0 5 SIGN 0 R W Setup Transaction Error Interrupt Status 0 SIGN interr...

Page 1139: ...t Name Initial Value R W Description 15 to 8 All 0 R Reserved These bits are always read as 0 The write value should always be 0 7 PIPE7BRDY 0 R W 1 BRDY Interrupt Status for PIPE7 2 0 Interrupts not generated 1 Interrupts generated 6 PIPE6BRDY 0 R W 1 BRDY Interrupt Status for PIPE6 2 0 Interrupts not generated 1 Interrupts generated 5 PIPE5BRDY 0 R W 1 BRDY Interrupt Status for PIPE5 2 0 Interru...

Page 1140: ...upt Status for PIPE1 2 0 Interrupts not generated 1 Interrupts generated 0 PIPE0BRDY 0 R W 1 BRDY Interrupt Status for PIPE0 2 0 Interrupts not generated 1 Interrupts generated Notes 1 Only 0 can be written to 2 If multiple sources have occurred an access cycle of at least 140 ns and 3 bus clock cycles is required in order to clear the bits in succession not simultaneously ...

Page 1141: ...t Name Initial Value R W Description 15 to 8 All 0 R Reserved These bits are always read as 0 The write value should always be 0 7 PIPE7NRDY 0 R W 1 NRDY Interrupt Status for PIPE7 2 0 Interrupts not generated 1 Interrupts generated 6 PIPE6NRDY 0 R W 1 NRDY Interrupt Status for PIPE6 2 0 Interrupts not generated 1 Interrupts generated 5 PIPE5NRDY 0 R W 1 NRDY Interrupt Status for PIPE5 2 0 Interru...

Page 1142: ...upt Status for PIPE1 2 0 Interrupts not generated 1 Interrupts generated 0 PIPE0NRDY 0 R W 1 NRDY Interrupt Status for PIPE0 2 0 Interrupts not generated 1 Interrupts generated Notes 1 Only 0 can be written to 2 If multiple sources have occurred an access cycle of at least 140 ns and 3 bus clock cycles is required in order to clear the bits in succession not simultaneously ...

Page 1143: ... BEMP PIPE4 BEMP PIPE3 BEMP PIPE2 BEMP PIPE1 BEMP PIPE0 BEMP Bit Bit Name Initial Value R W Description 15 to 8 All 0 R Reserved These bits are always read as 0 The write value should always be 0 7 PIPE7BEMP 0 R W 1 BEMP Interrupts for PIPE7 2 0 Interrupts not generated 1 Interrupts generated 6 PIPE6BEMP 0 R W 1 BEMP Interrupts for PIPE6 2 0 Interrupts not generated 1 Interrupts generated 5 PIPE5B...

Page 1144: ... 1 Interrupts generated 1 PIPE1BEMP 0 R W 1 BEMP Interrupts for PIPE1 2 0 Interrupts not generated 1 Interrupts generated 0 PIPE0BEMP 0 R W 1 BEMP Interrupts for PIPE0 2 0 Interrupts not generated 1 Interrupts generated Notes 1 Only 0 can be written to 2 If multiple sources have occurred an access cycle of at least 140 ns and 3 bus clock cycles is required in order to clear the bits in succession ...

Page 1145: ...R R R R OVRN CRCE SOFRM FRNM 10 0 Bit Bit Name Initial Value R W Description 15 OVRN 0 R W 1 Overrun Underrun 2 0 No error 1 An error occurred Indicates that a data buffer error is the source of error notification with the NRDY interrupt for the pipe in which isochronous transfer is being performed For details see tables 23 5 and 23 6 14 CRCE 0 R W 1 Receive Data Error 2 0 No error 1 An error occu...

Page 1146: ...s at the timing at which SOF packets are received If the module cannot detect an SOF packet because the packet has been corrupted or for other reasons the FRNM value is retained until a new SOF packet is received At that point the FRNM bit based on the SOF interpolation timer is not updated Notes 1 Only 0 can be written to 2 If OVRN and CRCE sources have occurred an access cycle of at least 140 ns...

Page 1147: ...generated 23 3 22 µFrame Number Register UFRMNUM UFRMNUM is a register that indicates the µframe number This register is initialized by a power on reset or a software reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R UFRNM 2 0 Bit Bit Name Initial Value R W Description 15 to 3 All 0 R Reserved These bits are always rea...

Page 1148: ...elected peripheral addresses should be set using the DEVSEL bits in PIPEMAXP This register is initialized by a power on reset a software reset or a USB bus reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R USBADDR 6 0 Bit Bit Name Initial Value R W Description 15 to 7 All 0 R Reserved These bits are always read as 0 Th...

Page 1149: ...ister is initialized by a power on reset software reset or a USB bus reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W BREQUEST 7 0 BMREQUESTTYPE 7 0 Bit Bit Name Initial Value R W Description 15 to 8 BREQUEST 7 0 H 00 R W Request These bits store the USB request bRequest value 7 to 0 BM...

Page 1150: ...unction controller function is selected these bits can only be read When the host controller function is selected these bits can be read or written to 23 3 26 USB Request Index Register USBINDX USBINDEX is a register that stores setup requests for control transfers When the function controller function is selected the value of wIndex that has been received is stored When the host controller functi...

Page 1151: ...Length to be transmitted is set This register is initialized by a power on reset a software reset and a USB bus reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W WLENGTH 15 0 Bit Bit Name Initial Value R W Description 15 to 0 WLENGTH 15 0 H 0000 R W Length These bits store the USB reques...

Page 1152: ... 0 0 0 0 0 0 R R R R R R R R W R W R R R W R R R R CNTMD SHT NAK DIR Bit Bit Name Initial Value R W Description 15 to 9 All 0 R Reserved These bits are always read as 0 The write value should always be 0 8 CNTMD 0 R W Continuous Transfer Mode 0 Non continuous transfer mode 1 Continuous transfer mode Because the DCP buffer memory is used for both control read transfers and control write transfers t...

Page 1153: ...tion When the host controller function is selected this bit sets the transfer direction of data stage and status stage in control transfers When the function controller function is selected this bit should be cleared to 0 0 Data receiving direction 1 Data transmitting direction 3 to 0 All 0 R Reserved These bits are always read as 0 The write value should always be 0 ...

Page 1154: ... Bit Name Initial Value R W Description 15 14 DEVSEL 1 0 00 R W Device Select When the host controller function is selected these bits specify the communication target device address When the function controller function is selected these bits should be set to B 00 00 Address 00 01 Address 01 10 Address 10 11 Address 11 13 to 7 All 0 R Reserved These bits are always read as 0 The write value shoul...

Page 1155: ... R W BSTS SUREQ SQCLR SQSET SQMON CCPL PID 1 0 Bit Bit Name Initial Value R W Description 15 BSTS 0 R Buffer Status 0 Buffer access is disabled 1 Buffer access is enabled The direction of buffer access writing or reading depends on the ISEL bit in CFIFOSEL 14 SUREQ 0 R W 2 SETUP Token Transmission Transmits the setup packet by setting this bit to 1 This module clears this bit when the setup transa...

Page 1156: ...the host controller function is selected this bit should be cleared to 0 1 0 PID 1 0 00 R W Response PID 00 NAK response 01 BUF response depending on the buffer state 10 STALL response 11 STALL response When the function controller function is selected these bits are cleared to B 00 immediately after the SETUP token has been received If a transfer error is detected the controller sets these bits t...

Page 1157: ...sponding bits for not only the selected pipe but all of the pipes are initialized This register is initialized by a power on reset or a software reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R W R W R W PIPESEL 2 0 Bit Bit Name Initial Value R W Description 15 to 3 All 0 R Reserved These bits are always read as 0 The wri...

Page 1158: ... and TYPE0 bits are initialized by a USB bus reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R R R R W R W R W R W R R R W R W R W R W R W TYPE 1 0 BFRE DBLB CNTMD SHT NAK DIR EPNUM 3 0 Bit Bit Name Initial Value R W Description 15 14 TYPE 1 0 00 R W Transfer Type PIPE1 and PIPE2 00 Pipe use disabled 01 Bulk transfer 10 Setting prohibited 1...

Page 1159: ...buffer 1 Double buffer This bit is valid when PIPE1 to PIPE5 are selected The procedure to change this bit for a PIPE is shown below Single buffer to double buffer DBLB 0 to DBLB 1 1 Set the PID bit to NAK for the corresponding pipe 2 Set the ACLRM bit in PIPEnCTR to 1 3 Wait for 100 ns using software 4 Clear the ACLRM bit to 0 5 Change the DBLB bit to 1 6 Set the response PID bit to BUF Double bu...

Page 1160: ...ected TYPE 11 This bit should not be set to 1 for PIPE6 and PIPE7 0 Non continuous transfer mode 1 Continuous transfer mode 7 SHTNAK 0 R W Pipe Disabled at End of Transfer 0 Pipe continued at the end of transfer 1 Pipe disabled at the end of transfer 6 5 All 0 R Reserved These bits are always read as 0 The write value should always be 0 4 DIR 0 R W Transfer Direction 0 Receiving OUT transfer 1 Sen...

Page 1161: ...R W R W R W R W R W R R R R W R W R W R W R W R W R W BUFSIZE 4 0 BUFNMB 6 0 Bit Bit Name Initial Value R W Description 15 0 R Reserved This bit is always read as 0 The write value should always be 0 14 to 10 BUFSIZE 4 0 H 00 R W Buffer Size Specify the buffer size for the corresponding pipe from 0 64 bytes to H 1F 2 kbytes The valid value for the BUFSIZE bit depends on the pipe selected by the PI...

Page 1162: ...set for the user system when PIPE1 to PIPE5 are selected BUFNMB0 to BUFNMB3 are used exclusively for the DCP BUFNMB4 and BUFNMB5 are allocated to PIPE6 and PIPE7 PIPE1 to PIPE5 A value from H 06 to H 4F should be set When PIPE7 is not used a value from H 05 to H 4F can be set When PIPE6 and PIPE7 are not used a value from H 04 to H 4F can be set PIPE6 Writing to this bit is invalid These bits are ...

Page 1163: ...0 R W Device Select When the host controller function is selected these bits specify the peripheral device address When the function controller function is selected this bit should be set to B 00 00 Address 00 01 Address 01 10 Address 10 11 Address 11 13 to 11 All 0 R Reserved These bits are always read as 0 The write value should always be 0 10 to 0 MXPS 10 0 R W Maximum Packet Size These bits sp...

Page 1164: ...to 13 All 0 R Reserved These bits are always read as 0 The write value should always be 0 12 IFIS 0 R W Isochronous IN Buffer Flush 0 The buffer is not flushed 1 The buffer is flushed This bit is valid only when isochronous transfer is selected Before using this bit the following settings are required When isochronous IN transfer is started 1 Set the IFIS bit to 1 2 Set the PID1 and PID0 bits in P...

Page 1165: ...y when the function controller function and isochronous transfer are selected In other words these bits can be set when PIPE1 and PIPE2 are selected OUT direction When this module does not receive the OUT token from the host until the time indicated by these bits it detects an interval error on the NRDY interrupt and generates the NRDY interrupt IN direction When this module does not receive the I...

Page 1166: ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R W R W R W 1 R W 1 R R R R R R W R W BSTS INBUFM AT REPM ACLRM SQCLR SQSET SQMON PID 1 0 Bit Bit Name Initial Value R W Description 15 BSTS 0 R Buffer Status 0 Buffer access is disabled 1 Buffer access is enabled The direction of buffer access writing or reading depends on setting of the DIR bit in PIPECFG For details see section 23 4 Operation 14 INBUFM 0 R...

Page 1167: ...ys be 0 1 0 PID 1 0 00 R W Response PID 4 00 NAK response 01 BUF response depending on the buffer state 10 STALL response 11 STALL response When the host controller function is selected and PID is not set to BUF no token is issued If a transfer error is detected the controller sets the PID bits to end the transfer Notes 1 Reading of 0 and writing of 1 are valid 2 If the SQCLR and SQSET bits in thi...

Page 1168: ...on is selected 2 Controller Function Selection This module can select the host controller function or function controller function using the DCFM bit in SYSCFG Changing the DCFM bit should be done in the initial settings immediately after a power on reset 3 Enabling High Speed Operation This module can select a USB communication speed communication bit rate of either high speed or full speed using...

Page 1169: ...e resistor after connection with the host controller or peripheral device by means of reset handshake suspended state and resume detection If a disconnection from the host controller or peripheral device is detected this module should be initialized by a software reset When the function controller function is selected and the DPRPU bit in SYSCFG is cleared to 0 during communication with the host c...

Page 1170: ...ates the Interrupt Related Status VBINT VBUS interrupt When a change in the state of the VBUS input pin has been detected low to high or high to low Host function VBSTS RESM Resume interrupt When a change in the state of the USB bus has been detected in the suspended state J state to K state or J state to SE0 Function SOFR Frame number update interrupt When the host controller function is selected...

Page 1171: ...d Set configuration request received Function DVSQ CTRT Control transfer stage transition interrupt When a stage transition is detected in control transfer Setup stage completed Control write transfer status stage transition Control read transfer status stage transition Control transfer completed A control transfer sequence error occurred Function CTSQ BEMP Buffer empty interrupt When transmission...

Page 1172: ...een received and there is no area in which data can be stored in the buffer memory so reception of data is not possible When a CRC error or a bit stuffing error occurred during isochronous transfer Host function NRDYSTS PIPENRDY BRDY Buffer ready interrupt When the buffer is ready reading or writing is enabled Host function NRDYSYS PIPENRDY BCHG Bus change interrupt When a change of USB bus state ...

Page 1173: ...ol read data stage CMPL Completion of control transfer Control transfer setup reception SERR Control transfer error VBSE INTENB0 INTSTS0 RSME SOFE DVSE CTRE BEMPE NRDYE BRDYE VBINT RESM SOFR DVST BCHGE INTENB1 INTSTS1 DTCHE SIGNE SACKE BCHG DTCH SIGN SACK CTRT BEMP NRDY BRDY b7 b1 b0 b7 b1 b0 BEMP interrupt status register NRDY interrupt enable register b7 b1 b0 b7 b1 b0 NRDY interrupt status regi...

Page 1174: ...he PIPEBRDYE bit in BRDYENB that corresponds to the pipe to 1 and the BRDYE bit in INTENB0 to 1 Figure 23 3 shows the timing at which the BRDY interrupt is generated The conditions for clearing the BRDY bit in INTSTS0 by this module depend on the setting of the BRDYM bit in INTENB1 Table 23 10 shows the conditions When the function controller function is selected under condition 1 noted below a ze...

Page 1175: ...cket 2 Buffer is full by reception 3 Transaction counter ends when buffer is not full 1 1 2 3 or 4 below 1 One of a to c conditions occurs when both buffers are waiting for reception a Short packet reception including a zero length packet b One buffer of two is full by reception c Transaction counter ends when buffer is not full 2 Reading of one buffer is complete when both buffers are waiting for...

Page 1176: ...ta of the packet is complete 3 After the transaction counter ends reading data of the last packet is complete Write Transmit DCP Not generated 1 to 7 0 0 1 2 3 or 4 below 1 Software changes the direction of transfer from receiving to transmitting 2 Transmission of data to the host is completed when there are data waiting to be transmitted 3 Software sets the ACLRM bit in PIPEnCTR to 1 when there a...

Page 1177: ...ransmission of data from one buffer is complete when there are data waiting to be transmitted in both buffers 4 Software sets the ACLRM bit to 1 when there are data waiting to be transmitted in both buffers 5 Software sets the SCLR bit to 1 when there are data waiting to be transmitted in both buffers 1 Don t care Not generated Note In non continuous transfer CNTMD 0 buffer full means that the max...

Page 1178: ...ated because writing to the buffer is enabled 1 Zero length packet reception or data packet reception when BFRE 0 short packet reception transaction counter completion buffer full 2 Data packet reception when BFRE 1 short packet reception transaction counter completion 3 Packet transmission USB bus USB bus USB bus BRDY interrupt BRDY interrupt BRDY interrupt Figure 23 3 Timing at which a BRDY Inte...

Page 1179: ...n underrun error has occurred during isochronous transfer However a SIGN interrupt will be generated when no ACK response has been returned from the peripheral side in setup transaction b When the function controller function is selected The NRDY interrupt is generated under the following conditions 1 For data transmission If an IN token has been received data underrun when the PID bit in PIPEnCTR...

Page 1180: ...function is selected IN token packet NAK handshake NAK handshake NAK handshake OUT token packet Data packet PING packet 1 Data transmission 2 Data reception OUT token reception 3 Data reception PING token reception USB bus NRDY interrupt USB bus NRDY interrupt CRC error etc USB bus NRDY interrupt Figure 23 4 Timing at which NRDY Interrupt is Generated when Function Controller Function is Selected ...

Page 1181: ... on one side is empty and transmitting of data from the buffer on the other side has been completed A BEMP interrupt is generated if data consisting of less than eight bytes is being written to the buffer on one side and transmitting of data on the other side of the buffer has been completed 2 When the receiving direction reading from the buffer memory has been set If the size of the data packet t...

Page 1182: ...ed by means of the resume interrupt The device state transition interrupts can be enabled or disabled individually using INTENB0 The device state that made a transition can be confirmed using the DVSQ bit in INTSTS0 To make a transition to the default state the device state transition interrupt is generated after the reset handshake protocol has been completed Device state can be controlled only w...

Page 1183: ...Address execution Address 0 when URST 1 DVST is set to 1 Suspended state detection when SUSP 1 DVST is set to 1 SetConfiguration execution configuration value 0 when SCFG 1 DVST is set to 1 SetConfiguration execution configuration value 0 when SADR 1 DVST is set to 1 Resume RESM is set to 1 Resume RESM is set to 1 Resume RESM is set to 1 Resume RESM is set to 1 USB bus reset detection when URST 1 ...

Page 1184: ...uring control write transfers At the OUT token of the data stage an IN token is received when there have been no ACK response at all A packet is received at the data stage for which the first data packet is DATAPID DATA0 At the status stage an OUT or PING token is received 3 During no data control transfers At the status stage an OUT or PING token is received At the control write transfer stage if...

Page 1185: ...fer sequence error 4 Error detection and IN token reception are valid at all stages in the box ACK trans mission ACK transmission ACK transmission Figure 23 7 Control Transfer Stage Transitions 6 Frame Update Interrupt Figure 23 8 shows an example of the SOFR interrupt output timing of this module When the frame number is updated or a damaged SOF packet is detected the SOFR interrupt is generated ...

Page 1186: ...o SOFR interrupt until the module enters the µSOF locked state Also the SOF interpolation function is not activated The µSOF lock state is the state in which µSOF packets with different frame numbers are received twice continuously without error occurrence The conditions under which the µSOF lock monitoring begins and stops are as follows 1 Conditions under which µSOF lock monitoring begins USBE 1...

Page 1187: ...not the peripheral device is connected when the host controller function has been selected and can also be used to detect a remote wakeup The BCHG interrupt is generated regardless of whether the host controller function or function controller function has been selected 10 DTCH Interrupt The DTCH interrupt is generated if disconnection of the device is detected during full speed operation when the...

Page 1188: ...odule has eight pipes that are used for data transfer Settings should be entered for each of the pipes in conjunction with the specifications of the system Table 23 11 Pipe Setting Items Register Name Bit Name Setting Contents Remarks TYPE Specifies the transfer type See section 23 4 3 1 Transfer Types BFRE Selects the BRDY interrupt mode PIPE1 to PIPE5 Can be set DBLB Selects a single buffer or d...

Page 1189: ...be set can be specified in areas H 0 to H 3 PIPE6 to PIPE7 Cannot be set areas fixed at H 4 and H 5 DCPMAXP PIPEMAXP MXPS Maximum packet size See section 23 4 3 3 Maximum Packet Size Setting IFIS Buffer flush PIPE1 and PIPE2 Can be set only when isochronous transfer has been selected PIPE3 to PIPE7 Cannot be set PIPEPERI IITV Interval counter PIPE1 and PIPE2 Can be set only when isochronous transf...

Page 1190: ...at the combination of the DIR bit and EPNUM bit is unique 3 Maximum Packet Size Setting The MXPS bit in DCPMAXP and PIPEMAXP is used to specify the maximum packet size for each pipe DCP and PIPE1 to PIPE5 can be set to any of the maximum pipe sizes defined by the USB specification For PIPE6 and PIPE7 64 bytes are the upper limit of the maximum packet size The maximum packet size should be set befo...

Page 1191: ...when the function controller function is selected The response PID is used to specify the response to transactions from the host A NAK setting The NAK response is always returned in response to the generated transaction B BUF setting Responses are made to transactions based on the status of the buffer memory C STALL setting The STALL response is always returned in response to the generated transac...

Page 1192: ...et and NAK is always returned in response to transactions When the SETUP token is received normally DCP only If the transaction counter ended or a short packet is received when the SHTNAK bit in PIPECFG has been set to 1 for bulk transfer B BUF setting There is no BUF writing by this module C STALL setting In the following cases PID STALL is set and STALL is always returned in response to transact...

Page 1193: ...d in a status stage Therefore software settings are not required However when the host controller function has been selected and control transfer is used the sequence bit should be set by software at the stage transition For the Clearfeature request transmission or reception the data PID sequence bit should be set by software regardless of whether the host controller function or function controlle...

Page 1194: ...g pipe operation response PID BUF In normal mode reception of OUT data is enabled and an ACK is returned in response to a PING token if the buffer is ready to receive data b Null Auto Response Mode With the pipes for bulk IN transfer zero length packets are continuously transmitted when the ATREPM bit is set to 1 To make a transition from normal mode to null auto response mode null auto response m...

Page 1195: ... SIE side The buffer memory sets independent areas for each pipe In the memory areas 64 bytes comprise one block and the memory areas are set using the first block number of the number of blocks specified using the BUFNMB and BUFSIZE bits in PIPEBUF Moreover three FIFO ports are used for access to the buffer memory reading and writing data A pipe is assigned to the FIFO port by specifying the pipe...

Page 1196: ...how the buffer status The buffer memory status can be confirmed using the BSTS bit in DCPCTR and the INBUFM bit in PIPEnCTR The access direction for the buffer memory can be specified using either the DIR bit in PIPEnCFG or the ISEL bit in CFIFOSEL when DCP is selected The INBUFM bit is valid for PIPE0 to PIPE5 in the sending direction For an IN pipe uses double buffer software can refer the BSTS ...

Page 1197: ... is allowed However because reading is not possible when a zero length packet is received the buffer must be cleared 1 sending direction 0 The transmission has not been finished Writing to the CPU is inhibited 1 sending direction 1 The transmission has been finished Writing to the CPU is allowed Table 23 13 Buffer Status Indicated by the INBUFM Bit IDIR INBUFM Buffer Memory State 0 receiving direc...

Page 1198: ...packets are destroyed Clearing method Cleared by writing 1 Cleared by writing 1 1 Mode valid 0 Mode invalid 1 Mode valid 0 Mode invalid c Buffer Areas Table 23 15 shows the FIFO buffer memory map of this controller The buffer memory has special fixed areas to which pipes are assigned in advance and user areas that can be set by the user The buffer for the DCP is a special fixed area that is used b...

Page 1199: ...received the ACK response is returned to the host controller This function can be set only in the buffer memory reading direction Also if the ACLRM bit is set to 1 and then to 0 the buffer memory of the pipe can be cleared regardless of the access direction An access cycle of at least 100 ns is required between ACLRM 1 and ACLRM 0 e Buffer Memory Specifications Single Double Setting Either a singl...

Page 1200: ...to packets of the maximum packet size and sent If the data being sent is less than the buffer size short packet or the integer multiple of the maximum packet size is less than the buffer size BVAL 1 must be set after the data being sent has been written In the continuous reception mode interrupts are not issued during reception of packets up to the buffer size until the transaction counter has end...

Page 1201: ...eceived DTLN 0 so the BCLR bit in the register must be used to release the buffer The length of the data being received can be confirmed using the DTLN bit in C DnFIFOCTR Table 23 16 FIFO Port Function Settings Register Name Bit Name Function Note REW Buffer memory rewind re read rewrite DCLRM Automatically clears data received for a specified pipe after the data has been read For DnFIFO only DREQ...

Page 1202: ... the current pipe once again The REW bit in C DnFIFOSEL is used for this If a pipe is selected when the REW bit is set to 1 and at the same time the CURPIPE bit in C DnFIFOSEL is set the pointer used for reading from and writing to the buffer memory is reset and reading or writing can be carried out from the first byte Also if a pipe is selected with 0 set for the REW bit data can be read and writ...

Page 1203: ...ansactions has been completed in the data packet receiving direction this module is able to recognize that the transfer has ended The transaction counter is a function that operates when the pipe selected by means of the D0FIFO D1FIFO port has been set in the direction of reading data from the buffer memory The transaction counter has TRNCNT that specifies the number of transactions and a current ...

Page 1204: ...t exceed a transfer speed of 48 MB s This module can limit access cycle through the access wait set FWAIT bit so that the peripheral clock frequency is not limited The FWAIT bit can be set to each FIFO port and can be efficiently set according to the CPU speed the transfer source access cycle and so on Conditions Access direction writing to FIFO Peripheral clock frequency 66 MHz MBW bit setting va...

Page 1205: ...send one zero length packet after all of the data has been sent under the condition below by setting 1 for the DEZPM bit in DnFIFOSEL This function can be set only if the buffer memory writing direction has been set a pipe in the sending direction has been set for the CURPIPE bits If the number of data bytes written to the buffer memory is a multiple of the integer for the maximum packet size when...

Page 1206: ...Doesn t need to be cleared Needs to be cleared Doesn t need to be cleared Doesn t need to be cleared e BRDY Interrupt Timing Selection Function By setting the BFRE bit setting in PIPECFG it is possible to keep the BRDY interrupt from being generated when a data packet consisting of the maximum packet size is received When using DMA transfers this function can be used to generate an interrupt only ...

Page 1207: ...ata from the buffer memory has been completed Note This function is valid only in the reading direction of reading from the buffer memory In the writing direction the BFRE bit should be fixed at 0 4 Timing at which the FIFO Port can be Accessed a Timing at which the FIFO Port can be Accessed when Switching Pipes Figure 23 12 shows a diagram of the timing up to the point where the FRDY and DTLN bit...

Page 1208: ...en using a pipe with a double buffer the other buffer can be accessed after reading from or writing to one buffer has been completed When using a double buffer access to the FIFO port should be carried out after waiting 300 ns and 6 clock cycles at a peripheral clock after the access made just prior to toggling The same timing applies when a short packet is being sent based on the BVAL 1 setting u...

Page 1209: ...generated according to the response received from the peripheral side SIGN1 or SACK bits in INTSTS1 by means of which the result of the setup transactions can be confirmed A data packet of DATA0 USB request is transmitted as the data packet for the setup transactions regardless of the setting of the SQMON bit in DCPCTR b Data Stage Data transfers are done using the DCP buffer memory The access dir...

Page 1210: ...high speed operation the PING packet is sent Control for the PING packet is done in the same manner as the bulk transfers 2 Control Transfers when the Function Controller Function is Selected a Setup Stage This module always sends an ACK response in response to a setup packet that is normal with respect to this module The operation of this module operates in the setup stage is noted below 1 When a...

Page 1211: ...is larger than the size of the DCP buffer memory the data transfer should be carried out using the BRDY interrupt for control write transfers and the BEMP interrupt for control read transfers With control write transfers during high speed operation the NYET handshake response is carried out based on the state of the buffer memory For information on the NYET handshake see section 23 4 6 2 NYET Hand...

Page 1212: ...ous transfer mode setting can be selected The maximum size that can be set for the buffer memory is 2 kbytes The buffer memory state is controlled by this module with a response sent automatically for a PING packet NYET handshake If MXPS 0 has been set the interrupt specifications are different from those of the other pipes For details see section 23 4 3 3 Maximum Packet Size Setting 1 PING Packet...

Page 1213: ...for PID Bit in DCPCTR Buffer Memory State Token Response Note NAK STALL SETUP ACK IN OUT PING NAK STALL BUF SETUP ACK RCV BRDY1 OUT PING ACK If an OUT token is received a data packet is received RCV BRDY2 OUT NYET Notifies whether a data packet can be received RCV BRDY2 OUT Short ACK Notifies whether a data packet can be received RCV BRDY2 PING ACK Notifies that a data packet can be received RCV N...

Page 1214: ...r under the following conditions Power on reset The IITV bits are initialized Software reset The IITV bits are initialized Buffer memory initialization using the ACLRM bit The IITV bits are not initialized but the count value is Setting the ACLRM bit to 0 starts counting from the value set in the IITV bits Note that the interval counter is not initialized in the following case USB bus reset USB su...

Page 1215: ...errors If the PID of the packet being received is illegal 2 CRC errors and bit stuffing errors If an error occurs in the CRC of the packet being received or the bit stuffing is illegal 3 Maximum packet size exceeded The maximum packet size exceeded the set value 4 Overrun and underrun errors When host controller function is selected When using isochronous IN transfers reception the IN token was re...

Page 1216: ...unction is selected and the function controller function is selected ignored as a corrupted packet 3 Overrun and underrun errors An NRDY interrupt is generated to set the OVRN bit in both cases when host controller function is selected and function controller function is selected When the host controller function is selected no tokens are transmitted When the function controller function is select...

Page 1217: ... the PID bits to STALL in both cases when the host controller function is selected and the function controller function is selected 2 DATA PID Because High Bandwidth transfers are not supported the DATA PID added with the USB 2 0 standard is supported as shown below 1 IN direction DATA0 Sent as data packet PID DATA1 Not sent DATA2 Not sent mDATA Not sent 2 OUT direction when using full speed opera...

Page 1218: ...rval frame during an isochronous IN transfer OUT Notifies that a token not being received When a token cannot be normally received in the interval frame during an isochronous OUT transfer The interval count is carried out when an SOF is received or for interpolated SOFs so the isochronism can be maintained even if an SOF is damaged The frame interval that can be set is the 2 IITV frame or 2 IITV µ...

Page 1219: ...e in function controller function after data has been written to the buffer memory a data packet can be sent with the next frame in which an SOF packet is detected This function is called the isochronous transfer transmission data setup function and it makes it possible to designate the frame from which transmission began If a double buffer is used for the buffer memory transmission will be enable...

Page 1220: ...sfer enabled SOF packet Buffer A Buffer B Figure23 14 Example of Data Setup Function Operation 5 Isochronous Transfer Transmission Buffer Flush when the Function Controller Function is Selected If an SOF packet or a µSOF packet is received without receiving an IN token in the interval frame during isochronous data transmission this module operates as if an IN token had been corrupted and clears th...

Page 1221: ...interval error There are five types of interval errors as shown below The interval error is generated at the timing indicated by 1 in the figure and the IN buffer flush function is activated If an interval error occurs during an IN transfers the buffer flush function is activated and if it occurs during an OUT transfer an NRDY interrupt is generated The OVRN bit should be used to distinguish betwe...

Page 1222: ...e SOF interpolation operation begins when USBE 1 SCKE 1 and an SOF packet is received The interpolation function is initialized under the following conditions Power on reset Software reset USB bus reset Suspended state detected Also the SOF interpolation operates under the following specifications 125 µs 1 ms conforms to the results of the reset handshake protocol The interpolation function is not...

Page 1223: ...e micro frame number SOFR interrupt timing and µSOF lock Isochronous transfer interval count If an SOF packet is missing when full speed operation is being used the FRNM bit in FRMNUM0 is not refreshed If a µSOF packet is missing during high speed operation the UFRNM bit in FRMNUM1 is refreshed However if a µSOF packet for which the µFRNM 000 is missing the FRNM bit is not refreshed In this case t...

Page 1224: ...xists 1 Interrupt transfer OUT BUF Valid Send data exists 1 IN BUF Valid 2 1 Isochronous transfer OUT BUF Valid 3 1 Notes 1 Symbols in the table indicate that the condition is one that is unrelated to the generating of tokens Valid indicates that for interrupt transfers and isochronous transfers the condition is generated only in transfer frames that are based on the interval counter Invalid indic...

Page 1225: ...sfer data stages and status stages A pipe is searched in the order of DCP Pipe 1 Pipe 2 Pipe 3 Pipe 4 Pipe 5 and then if the pipe is one for which a bulk or control transfer data stage or a control transfer status stage transaction can be generated the transaction is generated If a transfer is generated processing moves to the next pipe transaction regardless of whether the response from the perip...

Page 1226: ...Section 23 USB 2 0 Host Function Module USB Rev 0 50 May 18 2006 Page 1196 of 1588 REJ09B0313 0050 ...

Page 1227: ...f the 24 bits are valid R 5 G 6 B 5 STN DSTN panels are prone to flicker and shadowing The controller applies 65536 color control by 24 bit space modulation FRC with 8 bit RGB values for reduced flicker Dedicated display memory is unnecessary using part of the synchronous DRAM area 3 as the VRAM to store display data of the LCDC The display is stable because of the large 2 4 kbyte line buffer Supp...

Page 1228: ...iagram of LCDC Clock generator Pallet RAM LCDC Power control Register LCD_CLK Bck Pck Bus interface Bus interface BSC External memory VRAM Line buffer 2 4 kbytes 4 bytes 256 entries LCD_CL1 LCD_CL2 LCD_FLM LCD_DATA 15 to 0 LCD_DON LCD_VCPWC LCD_VEPWC LCD_M_DISP Peripheral bus DOTCLK Figure 24 1 LCDC Block Diagram ...

Page 1229: ...STN DSTN horizontal sync signal HSYNC TFT LCD_CL2 Output Shift clock 2 STN DSTN dot clock DOTCLK TFT LCD_M_DISP Output LCD current alternating signal DISP signal LCD_FLM Output First line marker vertical sync signal VSYNC TFT LCD_VCPWC Output LCD module power control VCC LCD_VEPWC Output LCD module power control VEE LCD_CLK Input LCD clock source input Note Check the LCD module specifications care...

Page 1230: ...dress register for lower display panel LDSARL R W H 0C000000 H FFFFFC0C 32 LCDC fetch data line address offset register for display panel LDLAOR R W H 0280 H FFFFFC10 16 LCDC palette control register LDPALCR R W H 0000 H FFFFFC12 16 Palette data register 00 to FF LDPR00 to LDPRFF R W H FFFFF800 to H FFFFFBFC 32 LCDC horizontal character number register LDHCNR R W H 4F52 H FFFFFC14 16 LCDC horizont...

Page 1231: ...ion clock source The selected clock source can be divided using an internal divider into a clock of 1 1 to 1 32 and be used as the LCDC operating clock DOTCLK The clock output from the LCDC is used to generate the synchronous clock output LCD_CL2 for the LCD panel from the operating clock selected in this register For a TFT panel LCD_CL2 DOTCLK and for an STN or DSTN panel LCD_CL2 a clock with a f...

Page 1232: ...ts are always read as 0 The write value should always be 0 5 to 0 DCDR 5 0 000001 R W Clock Division Ratio Set the input clock division ratio For details on the setting see table 24 3 Table 24 3 I O Clock Frequency and Clock Division Ratio I O Clock Frequency MHz DCDR 5 0 Clock Division Ratio 50 000 60 000 66 000 000001 1 1 50 000 60 000 66 000 000010 1 2 25 000 30 000 33 000 000011 1 3 16 667 20 ...

Page 1233: ...M vertical sync signal first line marker for the LCD module 0 LCD_FLM pulse is high active 1 LCD_FLM pulse is low active 14 CL1POL 0 R W CL1 Horizontal Sync Signal Polarity Select Selects the polarity of the LCD_CL1 horizontal sync signal for the LCD module 0 LCD_CL1 pulse is high active 1 LCD_CL1 pulse is low active 13 DISPPOL 0 R W DISP Display Enable Polarity Select Selects the polarity of the ...

Page 1234: ...Signal Control Sets whether or not to enable CL1 output during the vertical retrace period 0 CL1 is output during vertical retrace period 1 CL1 is not output during vertical retrace period 8 CL2CNT 1 R W CL2 Dot Clock of LCD Module Control Sets whether or not to enable CL2 output during the vertical and horizontal retrace period 0 CL2 is output during vertical and horizontal retrace period 1 CL2 i...

Page 1235: ...or data specifications for an STN or DSTN panel see the specifications of the LCD panel used The output data bus width should be set according to the mechanical interface specifications of the LCD panel If an STN or DSTN panel is selected display control is performed using a 24 bit space modulation FRC consisting of the 8 bit R G and B included in the LCDC regardless of the color and gradation set...

Page 1236: ... PABD DSPCOLOR 6 0 Bit Bit Name Initial Value R W Description 15 to 9 All 0 R Reserved These bits are always read as 0 The write value should always be 0 8 PABD 0 R W Byte Data Pixel Alignment Sets the pixel data alignment type in one byte of data The contents of aligned data per pixel are the same regardless of this bit s setting For example data H 05 should be expressed as B 0101 which is the no...

Page 1237: ...ually selected by the display data and displayed The number of colors that can be selected in rotation mode is restricted by the display resolution For details see table 24 5 0000000 Monochrome 2 grayscales 1 bpp via palette 0000001 Monochrome 4 grayscales 2 bpp via palette 0000010 Monochrome 16 grayscales 4 bpp via palette 0000100 Monochrome 64 grayscales 6 bpp via palette 0001010 Color 16 colors...

Page 1238: ...write value should always be 0 13 ROT 0 R W Rotation Module Select Selects whether or not to rotate the display by hardware Note that the following restrictions are applied to rotation An STN or TFT panel must be used A DSTN panel is not allowed The maximum horizontal internal scan direction of the LCD panel width of the LCD panel is 320 Set a binary exponential that exceeds the display size in LD...

Page 1239: ...ion is carried out whatever the AU setting is 00 4 burst 01 8 burst 10 16 burst 11 32 burst Notes 1 Above burst lengths are used for 32 bit bus For 16 bit bus the burst lengths are twice the lengths of 32 bit bus 2 When displaying a rotated image the burst length is limited depending on the number of column address bits and bus width of connected SDRAM For details see tables 24 4 and 24 5 7 to 0 A...

Page 1240: ...SAU4 All 0 R W Start Address for Upper Display Data Fetch The start address for data fetch of the display data must be set within the synchronous DRAM area of area 3 3 to 0 All 0 R Reserved These bits are always read as 0 The write value should always be 0 Notes 1 The minimum alignment unit of LDSARU is 512 bytes when the hardware rotation function is not used Write 0 to the lower nine bits When u...

Page 1241: ...R W R R R R SAL25 SAL24 SAL23 SAL22 SAL21 SAL20 SAL19 SAL18 SAL17 SAL16 SAL15 SAL14 SAL13 SAL12 SAL11 SAL10 SAL9 SAL8 SAL7 SAL6 SAL5 SAL4 Bit Bit Name Initial Value R W Description 31 to 28 All 0 R Reserved These bits are always read as 0 The write value should always be 0 27 26 All 1 R Reserved These bits are always read as 1 The write value should always be 1 25 to 4 SAL25 to SAL4 All 0 R W Star...

Page 1242: ...LAO4 LAO3 LAO2 LAO1 LAO0 Bit Bit Name Initial Value R W Description 15 to 10 LAO15 to LAO10 All 0 R W 9 LAO9 1 R W 8 LAO8 0 R W 7 LAO7 1 R W 6 to 0 LAO6 to LAO0 All 0 R W Line Address Offset The minimum alignment unit of LDLAOR is 16 bytes Because the LCDC handles these values as 16 byte data the values written to the lower four bits of the register are always treated as 0 The lower four bits of t...

Page 1243: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R W PALS PALEN Bit Bit Name Initial Value R W Description 15 to 5 All 0 R Reserved These bits always read as 0 The write value should always be 0 4 PALS 0 R Palette State Indicates the access right state of the palette 0 Display mode LCDC uses the palette 1 Color palette setting mode The host CPU uses the palette 3 to 1 All 0 R Reserved The...

Page 1244: ... 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W R R R R R R R R R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W PALDnn 23 PALDnn 22 PALDnn 21 PALDnn 20 PALDnn 19 PALDnn 18 PALDnn 17 PALDnn 16 PALDnn 15 PALDnn 14 PALDnn 13 PALDnn 12 PALDnn 11 PALDnn 10 PALDnn 9 PALDnn 8 PALDn...

Page 1245: ...with a width of 640 pixels HDCN 640 8 1 79 H 4F 7 6 5 4 3 2 1 0 HTCN7 HTCN6 HTCN5 HTCN4 HTCN3 HTCN2 HTCN1 HTCN0 0 1 0 1 0 0 1 0 R W R W R W R W R W R W R W R W Horizontal Total Character Number Set the number of total horizontal characters unit character 8 dots Specify to the value of the number of total characters 1 However the minimum horizontal retrace period is three characters 24 dots Example...

Page 1246: ...al sync signals CL1 and Hsync unit character 8 dots Specify to the value of the number of horizontal sync signal width 1 Example For a horizontal sync signal width of 8 dots HSYNW 8 dots 8 dots character 1 0 H 0 11 to 8 All 0 R Reserved These bits are always read as 0 The write value should always be 0 7 6 5 4 3 2 1 0 HSYNP7 HSYNP6 HSYNP5 HSYNP4 HSYNP3 HSYNP2 HSYNP1 HSYNP0 0 1 0 1 0 0 0 0 R W R W ...

Page 1247: ...Bit Initial value R W 0 0 0 0 0 0 0 1 1 1 0 1 1 1 1 1 R R R R R R W R W R W R W R W R W R W R W R W R W R W VDLN10 VDLN9 VDLN8 VDLN7 VDLN6 VDLN5 VDLN4 VDLN3 VDLN2 VDLN1 VDLN0 Bit Bit Name Initial Value R W Description 15 to 11 All 0 R Reserved These bits are always read as 0 The write value should always be 0 10 9 8 7 6 5 4 3 2 1 0 VDLN10 VDLN9 VDLN8 VDLN7 VDLN6 VDLN5 VDLN4 VDLN3 VDLN2 VDLN1 VDLN0...

Page 1248: ...VTLN0 Bit Bit Name Initial Value R W Description 15 to 11 All 0 R Reserved These bits are always read as 0 The write value should always be 0 10 9 8 7 6 5 4 3 2 1 0 VTLN10 VTLN9 VTLN8 VTLN7 VTLN6 VTLN5 VTLN4 VTLN3 VTLN2 VTLN1 VTLN0 0 0 1 1 1 0 1 1 1 1 1 R W R W R W R W R W R W R W R W R W R W R W Vertical Total Line Number Set the total number of vertical display lines unit line Specify to the val...

Page 1249: ...ue of the vertical sync signal width 1 Example For a vertical sync signal width of 1 line VSYNW 1 1 0 H 0 11 0 R Reserved This bit is always read as 0 The write value should always be 0 10 9 8 7 6 5 4 3 2 1 0 VSYNP10 VSYNP9 VSYNP8 VSYNP7 VSYNP6 VSYNP5 VSYNP4 VSYNP3 VSYNP2 VSYNP1 VSYNP0 0 0 1 1 1 0 1 1 1 1 1 R W R W R W R W R W R W R W R W R W R W R W Vertical Sync Signal Output Position Set the ou...

Page 1250: ...R W R W R W ACLN4 ACLN3 ACLN2 ACLN1 ACLN0 Bit Bit Name Initial Value R W Description 15 to 5 All 0 R Reserved These bits are always read as 0 The write value should always be 0 4 3 2 1 0 ACLN4 ACLN3 ACLN2 ACLN1 ACLN0 0 1 1 0 0 R W R W R W R W R W AC Line Number Set the number of lines where the LCD current alternating signal of the LCD module is toggled unit line Specify to the value of the number...

Page 1251: ...iption 15 MINTEN 0 R W Memory Access Interrupt Enable Enables or disables an interrupt generation at the start point of each vertical retrace line period for VRAM access by LCDC 0 Disables an interrupt generation at the start point of each vertical retrace line period for VRAM access 1 Enables an interrupt generation at the start point of each vertical retrace line period for VRAM access 14 FINTEN...

Page 1252: ...tine this bit should be cleared by writing 0 0 LCDC did not generate a memory access interrupt or has been informed that the generated memory access interrupt has completed 1 LCDC has generated a memory access end interrupt and not yet been informed that the generated memory access interrupt has completed 10 FINTS 0 R W Flame End Interrupt State Indicates the flame end interrupt handling state Thi...

Page 1253: ...ed 1 LCDC has generated a Vsync start interrupt and has not yet been informed that the generated Vsync start interrupt has completed 8 VEINTS 0 R W Vsync End Interrupt State Indicates the LCDC s Vsync end interrupt handling state This bit is set to 1 at the time a Vsync end interrupt is generated During the Vsync end interrupt handling routine this bit should be cleared by writing 0 0 LCDC did not...

Page 1254: ...Period Set the period from LCD_VEPWC assertion to LCD_DON assertion in the power on sequence of the LCD module in frame units Specify to the value of the period 1 This period is the c period in figures 24 4 to 24 7 Power Supply Control Sequence and States of the LCD Module For details on setting this register see table 24 6 Available Power Supply Control Sequence Periods at Typical Frame Rates The...

Page 1255: ...VEPWC pin 0 Disabled LCD_VEPWC pin is masked and fixed low 1 Enabled LCD_VEPWC pin output is asserted and negated according to the power on or power off sequence 4 DONE 1 R W LCD_DON Pin Enable Sets whether or not to enable a power supply control sequence using the LCD_DON pin 0 Disabled LCD_DON pin is masked and fixed low 1 Enabled LCD_DON pin output is asserted and negated according to the power...

Page 1256: ... 1 1 1 R W R W R W R W LCDC Power On Sequence Period Set the period from LCD_VCPWC assertion to starting output of the display data LCD_DATA and timing signals LCD_FLM LCD_CL1 LCD_CL2 and LCD_M_DISP in the power on sequence of the LCD module in frame units Specify to the value of the period 1 This period is the a period in figures 24 4 to 24 7 Power Supply Control Sequence and States of the LCD Mo...

Page 1257: ... in frame units Specify to the value of the period 1 This period is the e period in figures 24 4 to 24 7 Power Supply Control Sequence and States of the LCD Module 3 2 1 0 OFFF3 OFFF2 OFFF1 OFFF0 1 1 1 1 R W R W R W R W LCDC Power Off Sequence Period Set the period from stopping output of the display data LCD_DATA and timing signals LCD_FLM LCD_CL1 LCD_CL2 and LCD_M_DISP to LCD_VCPWC negation to i...

Page 1258: ...B 00 Do not make any action to the DON bit until the sequence ends 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R W R R R R W DON2 DON Bit Bit Name Initial Value R W Description 15 to 5 All 0 R Reserved These bits are always read as 0 The write value should always be 0 4 DON2 0 R W Display On 2 Specifies the start of the LCDC dis...

Page 1259: ...generated and indicates its processing state This interrupt is generated at the time when image data which is set by the line number register LDUINTLNR in LCDC is read from VRAM This LCDC issues the interrupts LCDCI user specified interrupt by this register memory access interrupt by the LCDC interrupt control register LDINTR and OR of Vsync interrupt output This register and LCDC interrupt contro...

Page 1260: ...ser specified interrupt and has not yet been notified that the generated user specified interrupt has completed Note Interrupt processing flow 1 Interrupt signal is input 2 LDINTR is read 3 If MINTS FINTS VSINTS or VEINTS is 1 a generated interrupt is memory access interrupt flame end interrupt Vsync rising edge interrupt or Vsync falling edge interrupt Processing for each interrupt is performed 4...

Page 1261: ...UINTLN8 0 R W 7 UINTLN7 0 R W 6 UINTLN6 1 R W 5 UINTLN5 0 R W 4 UINTLN4 0 R W 3 UINTLN3 1 R W 2 UINTLN2 1 R W 1 UINTLN1 1 R W 0 UINTLN0 1 R W User Specified Interrupt Generation Line Number Specifies the line in which the user specified interrupt is generated line units Set the number of lines in which interrupts are generated 1 Example Generate the user specified interrupt in the 80th line UINTLN...

Page 1262: ...12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R W R W R W R W R W R W R W R W LIRN7 LIRN6 LIRN5 LIRN4 LIRN3 LIRN2 LIRN1 LIRN0 Bit Bit Name Initial Value R W Description 15 to 8 All 0 R Reserved These bits are always read as 0 The write value should always be 0 7 to 0 LIRN7 to LIRN0 All 0 R W VRAM Read Bus Cycle Interval Specifies the number of t...

Page 1263: ...on and a 2 4 kbyte line buffer so although a complete breakdown of the display is unlikely there may be some problems with the display depending on the combination A recommended size at the frame rate of 60 Hz is 320 240 dots in 16 bpp or 640 480 dots in 8 bpp As a rough standard the bus occupation ratio shown below should not exceed 40 Bus occupation ratio Overhead coefficient x Total number of d...

Page 1264: ...NP V Addressable Video Bottom Border Front porch VSYNW Vsync Time Hsync Time Figure 24 2 Valid Display and the Retrace Period 24 4 2 Limits on the Resolution of Rotated Displays Burst Length and Connected Memory SDRAM This LCDC is capable of displaying a landscape format image on a LCD module by rotating a portrait format image for display by 90 degrees Only the numbers of colors for each resoluti...

Page 1265: ...ore than 8 bursts 9 bits Not more than 16 bursts 4 bpp packed 10 bits 8 bits 4 bursts 9 bits Not more than 8 bursts 4 bpp unpacked 10 bits Not more than 16 bursts 8 bits 4 bursts 9 bits Not more than 8 bursts Monochrome 6 bpp 10 bits Not more than 16 bursts 8 bits 4 bursts 9 bits Not more than 8 bursts 8 bpp 10 bits Not more than 16 bursts 8 bits Unusable 9 bits 4 bursts Color 16 bpp 10 bits Not m...

Page 1266: ...8 bits Not more than 16 bursts 9 bits 4 bpp packed 10 bits 8 bits Not more than 8 bursts 9 bits Not more than 16 bursts 4 bpp unpacked 10 bits 8 bits Not more than 8 bursts 9 bits Not more than 16 bursts 6 bpp 10 bits Color 8 bits Not more than 16 bursts 9 bits 4 bpp packed 10 bits 8 bits Not more than 8 bursts 9 bits Not more than 16 bursts 4 bpp unpacked 10 bits 8 bits Not more than 8 bursts 9 b...

Page 1267: ...ome 1 bpp 8 bits 9 bits 10 bits 2 bpp 8 bits 9 bits 10 bits 8 bits 9 bits 4 bpp packed 10 bits 8 bits Not more than 16 bursts 9 bits 4 bpp unpacked 10 bits 6 bpp 8 bits Not more than 16 bursts 9 bits 10 bits Color 4 bpp 8 bits packed 9 bits 10 bits 4 bpp 8 bits Not more than 16 bursts unpacked 9 bits 10 bits 8 bpp 8 bits Not more than 16 bursts 9 bits 10 bits Note Specify the data so that the data...

Page 1268: ...DSMR 240 320 320 240 8 bits Not more than 4 bursts 9 bits Not more than 8 bursts 4 bpp packed 10 bits Not more than 16 bursts 8 bits Unusable 9 bits 4 bursts Monochrome 4 bpp unpacked 10 bits Not more than 8 bursts 8 bits Unusable 9 bits 4 bursts 6 bpp 10 bits Not more than 8 bursts 8 bits Unusable 9 bits 4 bursts 8 bpp 10 bits Not more than 8 bursts 8 bits Unusable 9 bits Unusable Color 16 bpp 10...

Page 1269: ...ot more than 8 bursts 9 bits Not more than 16 bursts 10 bits 8 bits 4 bursts 4 bpp unpacked 9 bits Not more than 8 bursts 10 bits Not more than 16 bursts 8 bits 4 bursts 9 bits Not more than 8 bursts 6 bpp 10 bits Not more than 16 bursts Color 8 bits Not more than 8 bursts 9 bits Not more than 16 bursts 4 bpp packed 10 bits 8 bits 4 bursts 9 bits Not more than 8 bursts 4 bpp unpacked 10 bits Not m...

Page 1270: ... more than 16 bursts 9 bits 4 bpp packed 10 bits 8 bits Not more than 8 bursts 9 bits Not more than 16 bursts 4 bpp unpacked 10 bits 6 bpp 8 bits Not more than 8 bursts 9 bits Not more than 16 bursts 10 bits Color 4 bpp 8 bits Not more than 16 bursts packed 9 bits 10 bits 4 bpp 8 bits Not more than 8 bursts unpacked 9 bits Not more than 16 bursts 10 bits 8 bpp 8 bits Not more than 8 bursts 9 bits ...

Page 1271: ... B3 B4 B5 B6 B7 G0 G1 G2 G3 G4 G5 G6 G7 R0 R1 R2 R3 R4 R5 R6 R7 M0 M1 M2 M3 M4 M5 M6 M7 Figure 24 3 Color Palette Data Format PALDnn color and gradation data should be set as above For a color display PALDnn 23 16 PALDnn 15 8 and PALDnn 7 0 respectively hold the R G and B data Although the bits PALDnn 18 16 PALDnn 9 8 and PALDnn 2 0 exist no memory is associated with these bits PALDnn 18 16 PALDnn...

Page 1272: ... Address 00 01 02 03 LAO 00 LAO 01 LAO 02 LAO 03 Bit Byte0 Byte1 MSB LSB P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 7 6 5 4 3 2 1 0 Display Memory 3 Packed 4bpp Pixel Alignment in Byte is Big Endian Windows CE Recommended Format Address 00 01 02 03 LAO 00 LAO 01 LAO 02 LAO 03 Bit Byte0 Byte1 Byte2 MSB LSB P00 P01 P02 P03 P10 P11 P12 P13 P04 P05 P14 P15 7 6 5 4 3 2 1 0 Display ...

Page 1273: ...1 P02 P12 7 6 5 4 3 2 1 0 Display Memory 8 Unpacked 5bpp Windows CE Recommended Format Address 00 01 02 03 LAO 00 LAO 01 LAO 02 LAO 03 Bit Byte0 Byte1 Byte2 MSB LSB P00 P01 P10 P11 P02 P12 7 6 5 4 3 2 1 0 Display Memory Top Left Pixel P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 Display Pn Pn 1 0 Put 2 bit data LAO Line Address Offset Unused bits should be 0 Top Left Pixel P00 P...

Page 1274: ...LAO 04 LAO 06 Bit Word0 Word2 Word4 MSB LSB P00R P01R P10R P11R P02R P12R P00G P01G P10G P11G P02G P12G P00B P01B P10B P11B P02B P12B 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Display Memory Top Left Pixel P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 Display Pn Pn 5 0 Put 6 bit data LAO Line Address Offset Unused bits should be 0 Top Left Pixel P00 P01 P02 P03 P04 P05 P06 P07 P10 P1...

Page 1275: ...the clock used This LCDC has a Vsync interrupt function so that it is possible to issue an interrupt at the beginning of each vertical retrace line period to be exact at the beginning of the line after the last line of the display This function is set up by using the LDINTR 24 4 6 Power Management Registers An LCD module normally requires a specific sequence for processing to do with the cutoff of...

Page 1276: ...out LCD_DON pin Register control sequence Figure 24 4 Power Supply Control Sequence and States of the LCD Module 00b 00b 11b a 0 frame b 0 frame c 1 frame d 1 frame f 0 frame e 0 frame VCPE OFF VEPE OFF DONE ON Start power supply Start power cutoff Arbitrary Undefined Undefined LCD module active LCD module stopped LCD module stopped Internal signal Internal signal 2 Power Supply Control for LCD Pa...

Page 1277: ...le stopped e 1 frame f 1 frame a 1 frame 00b 11b 00b 11b Figure 24 6 Power Supply Control Sequence and States of the LCD Module 00b 00b 11b a 0 frame b 0 frame c 0 frame d 0 frame e 0 frame f 0 frame VCPE OFF 4 Power Supply Control for LCD panels other than TFT VEPE OFF DONE OFF Internal signal Internal signal Internal signal Start power supply Start power cutoff Arbitrary Undefined Undefined in D...

Page 1278: ...00 ms 11 1 60 200 00 ms H C 12 1 120 108 33 ms 12 1 60 216 67 ms H D 13 1 120 116 67 ms 13 1 60 233 33 ms H E 14 1 120 125 00 ms 14 1 60 250 00 ms ONA ONB ONC OFFD OFFE and OFFF are used to set the power supply control sequence periods in units of frames from 0 to 15 1 is subtracted from each register H 0 to H E settings select from 1 to15 frames The setting H F selects 0 frames Actual sequence pe...

Page 1279: ...r setting DON 0 Register access is enabled Fixed resolution the format of the data for display is determined by the number of colors and timing signals are not output to the LCD module Table 24 8 LCD Module Power Supply States STN DSTN module State Power Supply for Logic Display Data Timing Signal Power Supply for High Voltage Systems DON Signal Control Pin LCD_VCPWC LCD_CL2 LCD_CL1 LCD_FLM LCD_M_...

Page 1280: ...ply control sequence processing is in use by the LCDC or the supply of power is cut off while the LCDC is in its display on mode normal operation is not guaranteed In the worst case the connected LCD module may be damaged 24 4 7 Operation for Hardware Rotation Operation in hardware rotation mode is described below Hardware rotation mode can be thought of as using a landscape format LCD panel inste...

Page 1281: ...he image Picture image LDSARU start point LDSARU LDLAOR 1 Scanning starts from LDSARU Scanning is done from small address to large address of X coordination LDSARU LDLAOR LDVDLNR 1 end point Picture image Picture image LCD panel Start point End point 1 Normal mode Figure 24 8 Operation for Hardware Rotation Normal Mode For example the registers have been set up for the display of image data in lan...

Page 1282: ...degrees The settings in relation to the LCD panel should match the settings for the LCD panel before rotation Rotation is possible regardless of the drawing processing carried out by the graphics driver software However the sizes in the image data and address offset values which are managed by the graphics driver software must be altered Picture image LDSARU start point LDSARU LDLAOR HDCN 8 2 1 en...

Page 1283: ... B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 LCD_DATA4 to 15 Low Figure 24 10 Clock and LCD Data Signal Example STN Monochrome 4 Bit Data Bus Module DOTCLK 2 STN monochrome 8 bit data bus module LCD_CL2 LCD_DATA0 LCD_DATA1 LCD_DATA2 LCD_DATA3 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 LCD_DATA8 to 15 Low LCD_DATA4 LCD_DATA5 LCD_DATA6 LCD_DATA7 B12 B13 B14 B15 Figure 24 11 Clock and LCD Data Signal Example S...

Page 1284: ... R15 G15 B15 R12 G12 B12 R13 G13 B13 R14 G14 Figure 24 12 Clock and LCD Data Signal Example STN Color 4 Bit Data Bus Module DOTCLK 4 STN color 8 bit data bus module LCD_CL2 LCD_DATA0 LCD_DATA1 LCD_DATA2 LCD_DATA3 R0 G0 B0 R1 G1 R2 G2 LCD_DATA8 to 15 Low LCD_DATA4 LCD_DATA5 LCD_DATA6 LCD_DATA7 B1 B2 R3 G3 R4 G4 B3 R5 B4 G5 B5 R6 G6 R7 G7 B6 B7 R8 G8 B8 R9 G9 R10 G10 B9 B10 R11 G11 R12 G12 B11 R13 B...

Page 1285: ..._DATA2 LCD_DATA3 R0 G0 B0 R1 G1 R2 G2 LCD_DATA12 to 15 Low LCD_DATA4 LCD_DATA5 LCD_DATA6 LCD_DATA7 B1 B2 R3 G3 R4 G4 B3 R5 B4 G5 B5 R6 G6 R7 G7 B6 B7 R8 G8 B8 R9 G9 R10 G10 B9 B10 R11 G11 R12 G12 B11 R13 B12 G13 B13 R14 G14 R15 G15 B14 B15 LCD_DATA8 LCD_DATA9 LCD_DATA10 LCD_DATA11 Figure 24 14 Clock and LCD Data Signal Example STN Color 12 Bit Data Bus Module ...

Page 1286: ...ATA3 R0 G0 B0 R1 G1 R2 G2 LCD_DATA4 LCD_DATA5 LCD_DATA6 LCD_DATA7 B1 B2 R3 G3 R4 G4 B3 R5 B4 G5 B5 R6 G6 R7 G7 B6 B7 R8 G8 B8 R9 G9 R10 G10 B9 B10 R11 G11 R12 G12 B11 R13 B12 G13 B13 R14 G14 R15 G15 B14 B15 LCD_DATA8 LCD_DATA9 LCD_DATA10 LCD_DATA11 LCD_DATA12 LCD_DATA13 LCD_DATA14 LCD_DATA15 Figure 24 15 Clock and LCD Data Signal Example STN Color 16 Bit Data Bus Module ...

Page 1287: ...CD_DATA7 LB4 LB5 LB6 LB7 Figure 24 16 Clock and LCD Data Signal Example DSTN Monochrome 8 Bit Data Bus Module DOTCLK 8 DSTN monochrome 16 bit data bus module LCD_CL2 LCD_DATA0 LCD_DATA1 LCD_DATA2 LCD_DATA3 LCD_DATA4 LCD_DATA5 LCD_DATA6 LCD_DATA7 UB0 UB1 UB2 UB4 UB5 UB3 UB7 UB6 LB0 LB1 LB2 LB3 LB5 LB6 LB4 LB7 LCD_DATA8 LCD_DATA9 LCD_DATA10 LCD_DATA11 LCD_DATA12 LCD_DATA13 LCD_DATA14 LCD_DATA15 Figu...

Page 1288: ... LR5 LB4 LG5 LB5 LR6 LG6 LR7 LG7 LB6 LB7 Figure 24 18 Clock and LCD Data Signal Example DSTN Color 8 Bit Data Bus Module DOTCLK 10 DSTN color 12 bit data bbus module LCD_CL2 LCD_DATA8 LCD_DATA9 LCD_DATA10 LCD_DATA11 UR0 UG0 UB0 UR1 UR2 UG2 UB2 UR3 UR4 UG4 UB4 UR5 UR6 UG6 UB6 UR7 LCD_DATA12 to 15 Low LCD_DATA4 LCD_DATA5 LCD_DATA6 LCD_DATA7 UG1 UB1 LR0 LG0 UG3 UB3 LR2 LG2 UG5 UB5 LR4 LG4 UG7 UB7 LR6...

Page 1289: ...B0 UR1 UG1 UR2 UG2 LCD_DATA4 LCD_DATA5 LCD_DATA6 LCD_DATA7 UB1 UB2 UR3 UG3 UR4 UG4 UB3 UR5 UB4 UG5 UB5 UR6 UG6 UR7 UG7 UB6 UB7 LCD_DATA8 LCD_DATA9 LCD_DATA10 LCD_DATA11 LCD_DATA12 LCD_DATA13 LCD_DATA14 LCD_DATA15 LR0 LG0 LB0 LR1 LG1 LR2 LG2 LB1 LB2 LR3 LG3 LR4 LG4 LB3 LR5 LB4 LG5 LB5 LR6 LG6 LR7 LG7 LB6 LB7 Figure 24 20 Clock and LCD Data Signal Example DSTN Color 16 Bit Data Bus Module ...

Page 1290: ...ATA6 B05 LCD_DATA7 LCD_DATA8 LCD_DATA9 LCD_DATA10 LCD_DATA11 LCD_DATA12 LCD_DATA13 LCD_DATA14 LCD_DATA15 G00 G01 G02 G03 G04 G05 R01 R02 R03 R04 R05 B11 B12 B13 B14 B15 G10 G11 G12 G13 G14 G15 R11 R12 R13 R14 R15 B21 B22 B23 B24 B25 G20 G21 G22 G23 G24 G25 R21 R22 R23 R24 R25 B31 B32 B33 B34 B35 G30 G31 G32 G33 G34 G35 R31 R32 R33 R34 R35 Figure 24 21 Clock and LCD Data Signal Example TFT Color 16...

Page 1291: ...on position LCD_CL1 Valid Valid Valid Valid Valid LCD_DATA One horizontal time LCD_FLM 1st line data 2nd line data One frame time 480 CL1 1st line data LCD_CL2 2nd line data Next frame time 480 CL1 No vertical retrace One vertical retrace LCD_CL1 LCD_DATA Valid Valid One horizontal time LCD_FLM 1st line data 2nd line data One frame time 481 CL1 1st line data LCD_CL2 2nd line data Next frame time 4...

Page 1292: ... frame time 480 CL1 1st line data LCD_CL2 2nd line data 480th line data Next frame time 480 CL1 No vertical retrace Horizontal wave B639 3 B639 4 B639 5 B639 6 B639 7 G639 2 G639 3 G639 4 G639 5 G639 6 G639 7 R639 3 R639 4 R639 5 R639 6 R639 7 LCD_DATA8 LCD_DATA9 LCD_DATA10 LCD_DATA11 LCD_DATA12 LCD_DATA13 LCD_DATA14 LCD_DATA15 B0 3 B0 4 B0 5 B0 6 B0 7 G0 2 G0 3 G0 4 G0 5 G0 6 G0 7 R0 3 R0 4 R0 5 ...

Page 1293: ...3 Procedure for Halting Access to Display Data Storage VRAM 1 Confirm that the LPS1 and LPS0 bits in LDPMMR are currently set to 1 2 Clear the DON bit in LDCNTR to 0 display off mode 3 Confirm that the LPS1 and LPS0 bits in LDPMMR have changed to 0 4 Wait for the display time for a single frame to elapse This halting procedure is required before selecting self refreshing for the display data stora...

Page 1294: ...Section 24 LCD Controller LCDC Rev 0 50 May 18 2006 Page 1264 of 1588 REJ09B0313 0050 ...

Page 1295: ...DAC PA6 input port AN6 input ADC DA0 output DAC PA5 input port AN5 input ADC PA4 input port AN4 input ADC PA3 input port AN3 input ADC PA2 input port AN2 input ADC PA1 input port AN1 input ADC A PA0 input port AN0 input ADC Table 25 2 Multiplexed Pins Port B Setting of Mode Bits PBnMD 1 0 00 01 10 11 Setting Register Function 1 Related Module Function 2 Related Module Function 3 Related Module Fun...

Page 1296: ...2 input port SCL1 I O IIC3 PINT2 input INTC IRQ2 input INTC PB1 input port SDA0 I O IIC3 PINT1 input INTC IRQ1 input INTC PBCRL1 PB0 input port SCL0 I O IIC3 PINT0 input INTC IRQ0 input INTC Table 25 3 Multiplexed Pins Port C Setting of Mode Bits PCnMD 1 0 00 01 10 11 Setting Register Function 1 Related Module Function 2 Related Module Function 3 Related Module PC14 I O port WAIT input BSC PC13 I ...

Page 1297: ...ated Module Function 3 Related Module Function 4 Related Module Function 5 Related Module Function 6 Related Module PD15 I O port D31 I O data PINT7 input INTC ADTRG input ADC TIOC4D I O MTU2 PD14 I O port D30 I O data PINT6 input INTC TIOC4C I O MTU2 PD13 I O port D29 I O data PINT5 input INTC TEND1 output DMAC TIOC4B I O MTU2 PDCRL4 PD12 I O port D28 I O data PINT4 input INTC DACK1 output DMAC T...

Page 1298: ...ta IRQ4 input INTC SSCK1 I O SSU TCLKA input MTU2 TIOC1A I O MTU2 PD3 I O port D19 I O data IRQ3 input INTC SCS0 I O SSU DACK3 output DMAC TIOC0D I O MTU2 PD2 I O port D18 I O data IRQ2 input INTC SSO0 I O SSU DREQ3 input DMAC TIOC0C I O MTU2 PD1 I O port D17 I O data IRQ1 input INTC SSI0 I O SSU DACK2 output DMAC TIOC0B I O MTU2 PDCRL1 PD0 O port D16 I O data IRQ0 input INTC SSCK0 I O SSU DREQ2 i...

Page 1299: ...ut BSC IRQ5 input INTC SCK3 I O SCIF PECRL3 PE8 I O port CE2A output BSC IRQ4 input INTC SCK2 I O SCIF PE7 I O port FRAME output BSC IRQ3 input INTC TxD2 output SCIF DACK1 output DMAC PE6 I O port A25 output address IRQ2 input INTC RxD2 input SCIF DREQ1 input DMAC PE5 I O port A24 output address IRQ1 input INTC TxD1 output SCIF DACK0 output DMAC PECRL2 PE4 I O port A23 output address IRQ0 input IN...

Page 1300: ... O SSI PFCRH3 PF24 I O port SSISCK2 I O SSI PF23 I O port SSIDATA1 I O SSI LCD_VEPWC output LCDC PF22 I O port SSIWS1 I O SSI LCD_VCPWC output LCDC PF21 I O port SSISCK1 I O SSI LCD_CLK input LCDC PFCRH2 PF20 I O port SSIDATA0 I O SSI LCD_FLM output LCDC PF19 I O port SSIWS0 I O SSI LCD_M_DISP output LCDC PF18 I O port SSISCK0 I O SSI LCD_CL2 output LCDC PF17 I O port FCE output FLCTL LCD_CL1 outp...

Page 1301: ... O SSU PF5 I O port FCDE output FLCTL LCD_DATA5 output LCDC SSI1 I O SSU PFCRL2 PF4 I O port FWE output FLCTL LCD_DATA4 output LCDC SSCK1 I O SSU PF3 I O port TCLKD input MTU2 LCD_DATA3 output LCDC SCS0 I O SSU PF2 I O port TCLKC input MTU2 LCD_DATA2 output LCDC SSO0 I O SSU PF1 I O port TCLKB input MTU2 LCD_DATA1 output LCDC SSI0 I O SSU PFCRL1 PF0 I O port TCLKA input MTU2 LCD_DATA0 output LCDC ...

Page 1302: ...t C control register L3 PCCRL3 R W H 0000 H FFFE3912 8 16 Port C control register L2 PCCRL2 R W H 0000 H FFFE3914 8 16 32 Port C control register L1 PCCRL1 R W H 0000 H 0010 2 H FFFE3916 8 16 Port D I O register L PDIORL R W H 0000 H FFFE3986 8 16 Port D control register L4 PDCRL4 R W H 0000 H 1111 2 H FFFE3990 8 16 32 Port D control register L3 PDCRL3 R W H 0000 H 1111 2 H FFFE3992 8 16 Port D co...

Page 1303: ...otes 1 In 8 bit access the register can be read but cannot be written to 2 The initial value depends on the operating mode of the LSI 25 2 1 Port B I O Register L PBIORL PBIORL is a 16 bit readable writable register that is used to set the pins on port B as inputs or outputs The PB11IOR to PB8IOR bits correspond to the PB11 CTx1 to PB8 CRx0 CRx0 CRx1 pins respectively PBIORL is enabled when the po...

Page 1304: ...8 Writing by 8 bit access is disabled Note Bit Initial value R W Bit Bit Name Initial Value R W Description 15 to 2 All 0 R Reserved These bits are always read as 0 1 0 PB12MD 1 0 01 R W PB12 Mode Select the function of the PB12 WDTOVF IRQOUT REFOUT UBCTRG pin 00 PB12 output port 01 WDTOVF output WDT 10 IRQOUT REFOUT output INTC BSC 11 UBCTRG output UBC 2 Port B Control Register L3 PBCRL3 15 14 13...

Page 1305: ...tion of the PB10 CRx1 pin 0 PB10 I O port 1 CRx1 input RCAN TL1 7 6 All 0 R Reserved These bits are always read as 0 The write value should always be 0 5 4 PB9MD 1 0 00 R W PB9 Mode Select the function of the PB9 CTx0 CTx0 CTx1 pin 00 PB9 I O port 01 CTx0 output RCAN TL1 10 CTx0 CTx1 output RCAN TL1 11 Setting prohibited 3 2 All 0 R Reserved These bits are always read as 0 The write value should a...

Page 1306: ...13 12 PB7MD 1 0 00 R W PB7 Mode Select the function of the PB7 SDA3 PINT7 IRQ7 pin 00 PB7 input port 01 SDA3 I O IIC3 10 PINT7 input INTC 11 IRQ7 input INTC 11 10 All 0 R Reserved These bits are always read as 0 The write value should always be 0 9 8 PB6MD 1 0 00 R W PB6 Mode Select the function of the PB6 SCL3 PINT6 IRQ6 pin 00 PB6 input port 01 SCL3 I O IIC3 10 PINT6 input INTC 11 IRQ6 input INT...

Page 1307: ...B Control Register L1 PBCRL1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R W R W R R R W R W R R R W R W R R R W R W Bit Initial value R W PB1MD 1 0 PB2MD 1 0 PB3MD 1 0 PB0MD 1 0 Bit Bit Name Initial Value R W Description 15 14 All 0 R Reserved These bits are always read as 0 The write value should always be 0 13 12 PB3MD 1 0 00 R W PB3 Mode Select the function of the...

Page 1308: ...NTC 7 6 All 0 R Reserved These bits are always read as 0 The write value should always be 0 5 4 PB1MD 1 0 00 R W PB1 Mode Select the function of the PB1 SDA0 PINT1 IRQ1 pin 00 PB1 input port 01 SDA0 I O IIC3 10 PINT1 input INTC 11 IRQ1 input INTC 3 2 All 0 R Reserved These bits are always read as 0 The write value should always be 0 1 0 PB0MD 1 0 00 R W PB0 Mode Select the function of the PB0 SCL0...

Page 1309: ...lways be 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W PC1 IOR PC2 IOR PC3 IOR PC4 IOR PC5 IOR PC6 IOR PC7 IOR PC8 IOR PC9 IOR PC10 IOR PC11 IOR PC12 IOR PC13 IOR PC14 IOR PC0 IOR 25 2 4 Port C Control Register L1 to L4 PCCRL1 to PCCRL4 PCCRL1 to PCCRL4 are 16 bit readable writable registe...

Page 1310: ...always be 0 0 PC12MD 0 R W PC12 Mode Selects the function of the PC12 CKE pin 0 PC12 I O port 1 CKE output BSC 2 Port C Control Register L3 PCCRL3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R W R W R R R W R W R R R R W R R R R W PC11MD 1 0 PC10MD 1 0 PC9 MD0 PC8 MD0 Bit Initial value R W Bit Bit Name Initial Value R W Description 15 14 All 0 R Reserved These bits ar...

Page 1311: ...of the PC10 RASU BACK pin 00 PC10 I O port 01 RASU output BSC 10 BACK output BSC 11 Setting prohibited 7 to 5 All 0 R Reserved These bits are always read as 0 The write value should always be 0 4 PC9MD0 0 R W PC9 Mode Selects the function of the PC9 CASL pin 0 PC9 I O port 1 CASL output BSC 3 to 1 All 0 R Reserved These bits are always read as 0 The write value should always be 0 0 PC8MD0 0 R W PC...

Page 1312: ...PC7MD0 0 R W PC7 Mode Selects the function of the PC7 WE3 DQMUU AH ICIOWR pin 0 PC7 I O port 1 WE3 DQMUU AH ICIOWR output BSC 11 to 9 All 0 R Reserved These bits are always read as 0 The write value should always be 0 8 PC6MD0 0 R W PC6 Mode Selects the function of the PC6 WE2 DQMUL ICIORD pin 0 PC6 I O port 1 WE2 DQMUL ICIORD output BSC 7 to 5 All 0 R Reserved These bits are always read as 0 The ...

Page 1313: ...0 Depends on the operating mode of the LSI Note PC3 MD0 PC2 MD0 PC1 MD0 Bit Initial value R W Bit Bit Name Initial Value R W Description 15 to 13 All 0 R Reserved These bits are always read as 0 The write value should always be 0 12 PC3MD0 0 R W PC3 Mode Selects the function of the PC3 CS3 pin 0 PC3 I O port 1 CS3 output BSC 11 to 9 All 0 R Reserved These bits are always read as 0 The write value ...

Page 1314: ... PC1 I O port initial value 1 A1 output address Area 0 32 bit mode 0 Setting prohibited 1 A1 output address initial value 3 2 All 0 R Reserved These bits are always read as 0 The write value should always be 0 1 0 PC0MD 1 0 00 R W PC0 Mode Select the function of the PC0 A0 CS7 pin 00 PC0 I O port 01 A0 output address 10 CS7 output BSC 11 Setting prohibited Note The initial value depends on the ope...

Page 1315: ...s as an input 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W PD1 IOR PC2 IOR PD3 IOR PD4 IOR PD5 IOR PD6 IOR PD7 IOR PD8 IOR PD9 IOR PD10 IOR PD11 IOR PD12 IOR PD13 IOR PD14 IOR PD15 IOR PD0 IOR 25 2 6 Port D Control Registers L1 to L4 PDCRL1 to PDCRL4 PDCRL1 to PDCRL4 are 16 bit readable w...

Page 1316: ...etting prohibited 001 D31 I O data initial value 010 Setting prohibited 011 Setting prohibited 100 Setting prohibited 101 Setting prohibited 110 Setting prohibited 111 Setting prohibited Area 0 16 bit mode 000 PD15 I O port initial value 001 D31 I O data 010 PINT7 input INTC 011 Setting prohibited 100 ADTRG input ADC 101 TIOC4D I O MTU2 110 Setting prohibited 111 Setting prohibited 11 0 R Reserved...

Page 1317: ...g prohibited 001 D30 I O data initial value 010 Setting prohibited 011 Setting prohibited 100 Setting prohibited 101 Setting prohibited 110 Setting prohibited 111 Setting prohibited Area 0 16 bit mode 000 PD14 I O port initial value 001 D30 I O data 010 PINT6 input INTC 011 Setting prohibited 100 Setting prohibited 101 TIOC4C I O MTU2 110 Setting prohibited 111 Setting prohibited 7 0 R Reserved Th...

Page 1318: ...ting prohibited 001 D29 I O data initial value 010 Setting prohibited 011 Setting prohibited 100 Setting prohibited 101 Setting prohibited 110 Setting prohibited 111 Setting prohibited Area 0 16 bit mode 000 PD13 I O port 001 D29 I O data initial value 010 PINT5 input INTC 011 Setting prohibited 100 TEND1 output DMAC 101 TIOC4B I O MTU2 110 Setting prohibited 111 Setting prohibited 3 0 R Reserved ...

Page 1319: ... 000 Setting prohibited 001 D28 I O data initial value 010 Setting prohibited 011 Setting prohibited 100 Setting prohibited 101 Setting prohibited 110 Setting prohibited 111 Setting prohibited Area 0 16 bit mode 000 PD12 I O port 001 D28 I O data initial value 010 PINT4 input INTC 011 Setting prohibited 100 DACK1 output DMAC 101 TIOC4A I O MTU2 110 Setting prohibited 111 Setting prohibited Note Th...

Page 1320: ...s always read as 0 The write value should always be 0 14 to 12 PD11MD 2 0 000 001 R W PD11 Mode Select the function of the PD11 D27 PINT3 DREQ1 TIOC3D pin Area 0 32 bit mode 000 Setting prohibited 001 D27 I O data initial value 010 Setting prohibited 011 Setting prohibited 100 Setting prohibited 101 Setting prohibited 110 Setting prohibited 111 Setting prohibited Area 0 16 bit mode 000 PD11 I O po...

Page 1321: ...tting prohibited 001 D26 I O data initial value 010 Setting prohibited 011 Setting prohibited 100 Setting prohibited 101 Setting prohibited 110 Setting prohibited 111 Setting prohibited Area 0 16 bit mode 000 PD10 I O port initial value 001 D26 I O data 010 PINT2 input INTC 011 Setting prohibited 100 TEND0 output DMAC 101 TIOC3C I O MTU2 110 Setting prohibited 111 Setting prohibited 7 0 R Reserved...

Page 1322: ...ing prohibited 001 D25 I O data initial value 010 Setting prohibited 011 Setting prohibited 100 Setting prohibited 101 Setting prohibited 110 Setting prohibited 111 Setting prohibited Area 0 16 bit mode 000 PD9 I O port 001 D25 I O data initial value 010 PINT1 input INTC 011 Setting prohibited 100 DACK0 output DMAC 101 TIOC3B I O MTU2 110 Setting prohibited 111 Setting prohibited 3 0 R Reserved Th...

Page 1323: ...000 Setting prohibited 001 D24 I O data initial value 010 Setting prohibited 011 Setting prohibited 100 Setting prohibited 101 Setting prohibited 110 Setting prohibited 111 Setting prohibited Area 0 16 bit mode 000 PD8 I O port 001 D24 I O data initial value 010 PINT0 input INTC 011 Setting prohibited 100 DREQ0 input DMAC 101 TIOC3A I O MTU2 110 Setting prohibited 111 Setting prohibited Note The i...

Page 1324: ...t is always read as 0 The write value should always be 0 14 to 12 PD7MD 2 0 000 001 R W PD7 Mode Select the function of the PD7 D23 IRQ7 SCS1 TCLKD TIOC2B pin Area 0 32 bit mode 000 Setting prohibited 001 D23 I O data initial value 010 Setting prohibited 011 Setting prohibited 100 Setting prohibited 101 Setting prohibited 110 Setting prohibited 111 Setting prohibited Area 0 16 bit mode 000 PD7 I O...

Page 1325: ...00 Setting prohibited 001 D22 I O data initial value 010 Setting prohibited 011 Setting prohibited 100 Setting prohibited 101 Setting prohibited 110 Setting prohibited 111 Setting prohibited Area 0 16 bit mode 000 PD6 I O port initial value 001 D22 I O data 010 IRQ6 input INTC 011 SSO1 I O SSU 100 TCLKC input MTU2 101 TIOC2A I O MTU2 110 Setting prohibited 111 Setting prohibited 7 0 R Reserved Thi...

Page 1326: ...0 Setting prohibited 001 D21 I O data initial value 010 Setting prohibited 011 Setting prohibited 100 Setting prohibited 101 Setting prohibited 110 Setting prohibited 111 Setting prohibited Area 0 16 bit mode 000 PD5 I O port initial value 001 D21 I O data 010 IRQ5 input INTC 011 SSI1 I O SSU 100 TCLKB input MTU2 101 TIOC1B I O MTU2 110 Setting prohibited 111 Setting prohibited 3 0 R Reserved This...

Page 1327: ... mode 000 Setting prohibited 001 D20 I O data initial value 010 Setting prohibited 011 Setting prohibited 100 Setting prohibited 101 Setting prohibited 110 Setting prohibited 111 Setting prohibited Area 0 16 bit mode 000 PD4 I O port initial value 001 D20 I O data 010 IRQ4 input INTC 011 SSCK1 I O SSU 100 TCLKA input MTU2 101 TIOC1A I O MTU2 110 Setting prohibited 111 Setting prohibited Note The i...

Page 1328: ... is always read as 0 The write value should always be 0 14 to 12 PD3MD 2 0 000 001 R W PD3 Mode Select the function of the PD3 D19 IRQ3 SCS0 DACK3 TIOC0D pin Area 0 32 bit mode 000 Setting prohibited 001 D19 I O data initial value 010 Setting prohibited 011 Setting prohibited 100 Setting prohibited 101 Setting prohibited 110 Setting prohibited 111 Setting prohibited Area 0 16 bit mode 000 PD3 I O ...

Page 1329: ...00 Setting prohibited 001 D18 I O data initial value 010 Setting prohibited 011 Setting prohibited 100 Setting prohibited 101 Setting prohibited 110 Setting prohibited 111 Setting prohibited Area 0 16 bit mode 000 PD2 I O port initial value 001 D18 I O data 010 IRQ2 input INTC 011 SSO0 I O SSU 100 DREQ3 input DMAC 101 TIOC0C I O MTU2 110 Setting prohibited 111 Setting prohibited 7 0 R Reserved Thi...

Page 1330: ...0 Setting prohibited 001 D17 I O data initial value 010 Setting prohibited 011 Setting prohibited 100 Setting prohibited 101 Setting prohibited 110 Setting prohibited 111 Setting prohibited Area 0 16 bit mode 000 PD1 I O port initial value 001 D17 I O data 010 IRQ1 input INTC 011 SSI0 I O SSU 100 DACK2 output DMAC 101 TIOC0B I O MTU2 110 Setting prohibited 111 Setting prohibited 3 0 R Reserved Thi...

Page 1331: ... mode 000 Setting prohibited 001 D16 I O data initial value 010 Setting prohibited 011 Setting prohibited 100 Setting prohibited 101 Setting prohibited 110 Setting prohibited 111 Setting prohibited Area 0 16 bit mode 000 PD0 I O port initial value 001 D16 I O data 010 IRQ0 input INTC 011 SSCK0 I O SSU 100 DREQ2 input DMAC 101 TIOC0A I O MTU2 110 Setting prohibited 111 Setting prohibited Note The i...

Page 1332: ... W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W PE1 IOR PE2 IOR PE3 IOR PE4 IOR PE5 IOR PE6 IOR PE7 IOR PE8 IOR PE9 IOR PE10 IOR PD11 IOR PE12 IOR PE13 IOR PE14 IOR PE15 IOR PE0 IOR 25 2 8 Port E Control Registers L1 to L4 PECRL1 to PECRL4 PECRL1 to PECRL4 are 16 bit readable writable registers that are used to select the functions of the multiplexed pins on port E 1 P...

Page 1333: ...utput BSC 10 Setting prohibited 11 CTS3 I O SCIF 7 6 All 0 R Reserved These bits are always read as 0 The write value should always be 0 5 4 PE13MD 1 0 00 R W PE13 Mode Select the function of the PE13 TxD3 pin 00 PE13 I O port 01 Setting prohibited 10 Setting prohibited 11 TxD3 output SCIF 3 2 All 0 R Reserved These bits are always read as 0 The write value should always be 0 1 0 PE12MD 1 0 00 R W...

Page 1334: ...ld always be 0 14 to 12 PE11MD 2 0 000 R W PE11 Mode Select the function of the PE11 CS6 CE1B IRQ7 TEND1 pin 000 PE11 I O port 001 CS6 CE1B output BSC 010 IRQ7 input INTC 011 Setting prohibited 100 TEND1 output DMAC 101 Setting prohibited 110 Setting prohibited 111 Setting prohibited 11 0 R Reserved This bit is always read as 0 The write value should always be 0 10 to 8 PE10MD 2 0 000 R W PE10 Mod...

Page 1335: ...ld always be 0 5 4 PE9MD 1 0 00 R W PE9 Mode Select the function of the PE9 CS5 CE1A IRQ5 SCK3 pin 00 PE9 I O port 01 CS5 CE1A output BSC 10 IRQ5 input INTC 11 SCK3 I O SCIF 3 2 All 0 R Reserved These bits are always read as 0 The write value should always be 0 1 0 PE8MD 1 0 00 R W PE8 Mode Select the function of the PE8 CE2A IRQ4 SCK2 pin 00 PE8 I O port 01 CE2A output BSC 10 IRQ4 input INTC 11 S...

Page 1336: ... should always be 0 14 to 12 PE7MD 2 0 000 R W PE7 Mode Select the function of the PE7 FRAME IRQ3 TxD2 DACK1 pin 000 PE7 I O port 001 FRAME output BSC 010 IRQ3 input INTC 011 TxD2 output SCIF 100 DACK1 output DMAC 101 Setting prohibited 110 Setting prohibited 111 Setting prohibited 11 0 R Reserved This bit is always read as 0 The write value should always be 0 10 to 8 PE6MD 2 0 000 R W PE6 Mode Se...

Page 1337: ...00 PE5 I O port 001 A24 output address 010 IRQ1 input INTC 011 TxD1 output SCIF 100 DACK0 output DMAC 101 Setting prohibited 110 Setting prohibited 111 Setting prohibited 3 0 R Reserved This bit is always read as 0 The write value should always be 0 2 to 0 PE4MD 2 0 000 R W PE4 Mode Select the function of the PE4 A23 IRQ0 RxD1 DREQ0 pin 000 PE4 I O port 001 A23 output address 010 IRQ0 input INTC 0...

Page 1338: ...0 13 12 PE3MD 1 0 00 R W PE3 Mode Select the function of the PE3 A22 SCK1 pin 00 PE3 I O port 01 A22 output address 10 Setting prohibited 11 SCK1 I O SCIF 11 10 All 0 R Reserved These bits are always read as 0 The write value should always be 0 9 8 PE2MD 1 0 00 R W PE2 Mode Select the function of the PE2 A21 SCK0 pin 00 PE2 I O port 01 A21 output address 10 Setting prohibited 11 SCK0 I O SCIF 7 6 ...

Page 1339: ...ts The PF30IOR to PF0IOR bits correspond to the PF30 AUDIO_CLK to PF0 TCLKA LCD_DATA0 SSCK0 pins respectively PFIORH and PFIORL are enabled when the port F pins are functioning as general purpose inputs outputs PF30 to PF0 In other states they are disabled If a bit in PFIORH PFIORL is set to 1 the corresponding pin on port F functions as an output If it is cleared to 0 the corresponding pin functi...

Page 1340: ... 16 bit readable writable registers that are used to select the functions of the multiplexed pins on port F 1 Port F Control Register H4 PFCRH4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R W R R R R W R R R R W PF30 MD0 PF29 MD0 PF28 MD0 Bit Initial value R W Bit Bit Name Initial Value R W Description 15 to 9 All 0 R Reserved These bits are always read as 0...

Page 1341: ... 0 0 R R R R W R R R R W R R R R W R R R R W PF26 MD0 PF27 MD0 PF25 MD0 PF24 MD0 Bit Initial value R W Bit Bit Name Initial Value R W Description 15 to 13 All 0 R Reserved These bits are always read as 0 The write value should always be 0 12 PF27MD0 0 R W PF27 Mode Selects the function of the PF27 SSISCK3 pin 0 PF27 I O port 1 SSISCK3 I O SSI 11 to 9 All 0 R Reserved These bits are always read as ...

Page 1342: ...K2 I O SSI 3 Port F Control Register H2 PFCRH2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R W R W R R R W R W R R R W R W R R R W R W PF20MD 1 0 PF21MD 1 0 PF22MD 1 0 PF23MD 1 0 Bit Initial value R W Bit Bit Name Initial Value R W Description 15 14 All 0 R Reserved These bits are always read as 0 The write value should always be 0 13 12 PF23MD 1 0 00 R W PF23 Mode Se...

Page 1343: ... 6 All 0 R Reserved These bits are always read as 0 The write value should always be 0 5 4 PF21MD 1 0 00 R W PF21 Mode Select the function of the PF21 SSISCK1 LCD_CLK pin 00 PF21 I O port 01 SSISCK1 I O SSI 10 LCD_CLK input LCDC 11 Setting prohibited 3 2 All 0 R Reserved These bits are always read as 0 The write value should always be 0 1 0 PF20MD 1 0 00 R W PF20 Mode Select the function of the PF...

Page 1344: ... These bits are always read as 0 The write value should always be 0 13 12 PF19MD 1 0 00 R W PF19 Mode Select the function of the PF19 SSIWS0 LCD_M_DISP pin 00 PF19 I O port 01 SSIWS0 I O SSI 10 LCD_M_DISP output LCDC 11 Setting prohibited 11 10 All 0 R Reserved These bits are always read as 0 The write value should always be 0 9 8 PF18MD 1 0 00 R W PF18 Mode Select the function of the PF18 SSISCK0...

Page 1345: ...ct the function of the PF17 FCE LCD_CL1 pin 00 PF17 I O port 01 FCE output FLCTL 10 LCD_CL1 output LCDC 11 Setting prohibited 3 2 All 0 R Reserved These bits are always read as 0 The write value should always be 0 1 0 PF16MD 1 0 00 R W PF16 Mode Select the function of the PF16 FRB LCD_DON pin 00 PF16 I O port 01 FRB input FLCTL 10 LCD_DON output LCDC 11 Setting prohibited ...

Page 1346: ... These bits are always read as 0 The write value should always be 0 13 12 PF15MD 1 0 00 R W PF15 Mode Select the function of the PF15 NAF7 LCD_DATA15 pin 00 PF15 I O port 01 NAF7 I O FLCTL 10 LCD_DATA15 output LCDC 11 Setting prohibited 11 10 All 0 R Reserved These bits are always read as 0 The write value should always be 0 9 8 PF14MD 1 0 00 R W PF14 Mode Select the function of the PF14 NAF6 LCD_...

Page 1347: ...e function of the PF13 NAF5 LCD_DATA13 pin 00 PF13 I O port 01 NAF5 I O FLCTL 10 LCD_DATA13 output LCDC 11 Setting prohibited 3 2 All 0 R Reserved These bits are always read as 0 The write value should always be 0 1 0 PF12MD 1 0 00 R W PF12 Mode Select the function of the PF12 NAF4 LCD_DATA12 pin 00 PF12 I O port 01 NAF4 I O FLCTL 10 LCD_DATA12 output LCDC 11 Setting prohibited ...

Page 1348: ...These bits are always read as 0 The write value should always be 0 13 12 PF11MD 1 0 00 R W PF11 Mode Select the function of the PF11 NAF3 LCD_DATA11 pin 00 PF11 I O port 01 NAF3 I O FLCTL 10 LCD_DATA11 output LCDC 11 Setting prohibited 11 10 All 0 R Reserved These bits are always read as 0 The write value should always be 0 9 8 PF10MD 1 0 00 R W PF10 Mode Select the function of the PF10 NAF2 LCD_D...

Page 1349: ...t the function of the PF9 NAF1 LCD_DATA9 pin 00 PF9 I O port 01 NAF1 I O FLCTL 10 LCD_DATA9 output LCDC 11 Setting prohibited 3 2 All 0 R Reserved These bits are always read as 0 The write value should always be 0 1 0 PF8MD 1 0 00 R W PF8 Mode Select the function of the PF8 NAF0 LCD_DATA8 pin 00 PF8 I O port 01 NAF0 I O FLCTL 10 LCD_DATA8 output LCDC 11 Setting prohibited ...

Page 1350: ...rved These bits are always read as 0 The write value should always be 0 13 12 PF7MD 1 0 00 R W PF7 Mode Select the function of the PF7 FSC LCD_DATA7 SCS1 pin 00 PF7 I O port 01 FSC output FLCTL 10 LCD_DATA7 output LCDC 11 SCS1 I O SSU 11 10 All 0 R Reserved These bits are always read as 0 The write value should always be 0 9 8 PF6MD 1 0 00 R W PF6 Mode Select the function of the PF6 FOE LCD_DATA6 ...

Page 1351: ...the function of the PF5 FCDE LCD_DATA5 SSI1 pin 00 PF5 I O port 01 FCDE output FLCTL 10 LCD_DATA5 output LCDC 11 SSI1 I O SSU 3 2 All 0 R Reserved These bits are always read as 0 The write value should always be 0 1 0 PF4MD 1 0 00 R W PF4 Mode Select the function of the PF4 FWE LCD_DATA4 SSCK1 pin 00 PF4 I O port 01 FWE output FLCTL 10 LCD_DATA4 output LCDC 11 SSCK1 I O SSU ...

Page 1352: ...ed These bits are always read as 0 The write value should always be 0 13 12 PF3MD 1 0 00 R W PF3 Mode Select the function of the PF3 TCLKD LCD_DATA3 SCS0 pin 00 PF3 I O port 01 TCLKD input MTU2 10 LCD_DATA3 output LCDC 11 SCS0 I O SSU 11 10 All 0 R Reserved These bits are always read as 0 The write value should always be 0 9 8 PF2MD 1 0 00 R W PF2 Mode Select the function of the PF2 TCLKC LCD_DATA...

Page 1353: ...he function of the PF1 TCLKB LCD_DATA1 SSI0 pin 00 PF1 I O port 01 TCLKB input MTU2 10 LCD_DATA1 output LCDC 11 SSI0 I O SSU 3 2 All 0 R Reserved These bits are always read as 0 The write value should always be 0 1 0 PF0MD 1 0 00 R W PF0 Mode Select the function of the PF0 TCLKA LCD_DATA0 SSCK0 pin 00 PF0 I O port 01 TCLKA input MTU2 10 LCD_DATA0 output LCDC 11 SSCK0 I O SSU ...

Page 1354: ...tion 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R W R W PB12IRQ 1 0 Bit Initial value R W Bit Bit Name Initial Value R W Description 15 to 2 All 0 R Reserved These bits are always read as 0 The write value should always be 0 1 0 PB12IRQ 1 0 00 R W PB12IRQOUT Mode Select the function of the IRQOUT REFOUT pin when bits 1 and 0 PB12MD 1 0 in PBCR...

Page 1355: ...read as 0 The write value should always be 0 14 to 12 SSI3CKS 2 0 000 R W SSI ch3 Clock Select Select the source of the oversampling clock that is used in channel 3 of the SSI For settings see table 25 8 11 0 R Reserved This bit is always read as 0 The write value should always be 0 10 to 8 SSI2CKS 2 0 000 R W SSI ch2 Clock Select Select the source of the oversampling clock that is used in channel...

Page 1356: ...he Source of Oversampling Clock by Setting the SSInCKS Bits Clock Operation Mode Settings of SSInCKS 2 0 1 0 or 1 2 3 000 AUDIO_X1 input 001 AUDIO_X1 input 4 010 AUDIO_CLK input 2 011 AUDIO_CLK input 2 4 100 EXTAL input CKIO input Setting prohibited 101 EXTAL input 4 CKIO input 4 Setting prohibited 110 EXTAL input 2 CKIO input 2 Setting prohibited 111 EXTAL input 8 CKIO input 8 Setting prohibited ...

Page 1357: ...nction is automatically changed by the settings of the A D control status register in A D converter and D A control register in D A converter See section 20 A D Converter ADC and section 21 D A Converter DAC Table 25 9 Switching Pin Function of Port A Pin Function A D converter D A converter PA0 AN0 to PA5 AN5 PA6 AN6 DA0 and PA7 AN7 DA1 Stop Stop PA0 to PA5 PA6 and PA7 Stop Operation PA0 to PA5 D...

Page 1358: ...sage Notes The multiplexed pins listed in tables 25 1 to 25 6 except pins PA0 to PA7 and PB0 to PB7 include weak keepers in their I O buffers to prevent the pins from floating into intermediate voltage levels However note that the voltage retained in the high impedance state may fluctuate due to noise ...

Page 1359: ...I O 16 ports Port E I O 16 ports Port F I O 31 ports 2 The following pins in this LSI have weak keeper circuits that prevent the pins from floating into intermediate voltage levels Port B PB8 to PB12 Port C PC0 and PC14 Port D PD0 to PD15 Port E PE0 to PE15 Port F PF0 to PF30 The I O pins include weak keeper circuits that fix the input level high or low when the I O pins are not driven from outsid...

Page 1360: ... 2 Port A Data Register L PADRL PADRL is a 16 bit read only register that stores port A data The PA7DR to PA0DR bits correspond to the PA7 AN7 DA1 to PA0 AN0 pins respectively The general input function of the PA7 to PA0 pins is enabled only when the A D and D A converters are halted Writing to these bits is ignored and therefore does not affect the pin state If these bits are read the pin state n...

Page 1361: ... Pin state R 5 PA5DR Pin state R 4 PA4DR Pin state R 3 PA3DR Pin state R 2 PA2DR Pin state R 1 PA1DR Pin state R 0 PA0DR Pin state R See table 26 2 Table 26 2 Port A Data Registers L PADRL Read Write Operation Bits 7 to 0 of PADRL Pin Function Read Operation Write Operation General input Pin state Ignored Does not affect the pin state ANn input DAn output Disabled Ignored Does not affect the pin s...

Page 1362: ...B6 input SCL3 I O PINT6 input IRQ6 input PB5 input SDA2 I O PINT5 input IRQ5 input PB4 input SCL2 I O PINT4 input IRQ4 input PB3 input SDA1 I O PINT3 input IRQ3 input PB2 input SCL1 I O PINT2 input IRQ2 input PB1 input SDA0 I O PINT1 input IRQ1 input PB0 input SCL0 I O PINT0 input IRQ0 input Figure 26 2 Port B 26 3 1 Register Descriptions Table 26 3 lists the port B registers Table 26 3 Register C...

Page 1363: ...turned directly If a value is written to PBDRL although that value is written into PBDRL it does not affect the pin state Table 26 4 summarizes PBDRL read write operations 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 R R R R W R W R W R W R W R R R R R R R R PB12 DR PB11 DR PB10 DR PB9 DR PB8 DR PB7 DR PB6 DR PB5 DR PB4 DR PB3 DR PB2 DR PB1 DR PB0 DR Note Depends on ...

Page 1364: ...PBDRL but it has no effect on pin state Bits 11 to 8 of PBDRL PBIORL Pin Function Read Operation Write Operation General input Pin state Can write to PBDRL but it has no effect on pin state 0 Other than general input Pin state Can write to PBDRL but it has no effect on pin state General output PBDRL value Value written is output from pin 1 Other than general output PBDRL value Can write to PBDRL b...

Page 1365: ... 1 0 Bit Initial value R W 0 0 0 0 R R R R R R R R R R R R R R R R PB11 PR PB10 PR PB9 PR PB8 PR PB7 PR PB6 PR PB5 PR PB4 PR PB3 PR PB2 PR PB1 PR PB0 PR Bit Bit Name Initial Value R W Description 15 to 12 All 0 R Reserved These bits are always read as 0 and cannot be modified 11 PB11PR Pin state R 10 PB10PR Pin state R 9 PB9PR Pin state R 8 PB8PR Pin state R 7 PB7PR Pin state R 6 PB6PR Pin state R...

Page 1366: ...8 I O RASL output PC7 I O WE3 DQMUU AH ICIOWR output PC6 I O WE2 DQMUL ICIORD output PC5 I O WE1 DQMLU WE output PC4 I O WE0 DQMLL output PC3 I O CS3 output PC2 I O CS2 output PC1 I O A1 output PC0 I O A0 output CS7 output Figure 26 3 Port C 26 4 1 Register Descriptions Table 26 5 lists the port C registers Table 26 5 Register Configuration Register Name Abbreviation R W Initial Value Address Acce...

Page 1367: ...y If a value is written to PCDRL although that value is written into PCDRL it does not affect the pin state Table 26 6 summarizes PCDRL read write operations 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W PC14 DR PC13 DR PC12 DR PC11 DR PC10 DR PC9 DR PC8 DR PC7 DR PC6 DR PC5 DR PC4 DR PC3 DR...

Page 1368: ...RL Pin Function Read Operation Write Operation 0 General input Pin state Can write to PCDRL but it has no effect on pin state Other than general input Pin state Can write to PCDRL but it has no effect on pin state 1 General output PCDRL value Value written is output from pin Other than general output PCDRL value Can write to PCDRL but it has no effect on pin state ...

Page 1369: ... R R R R R R R R R R PC14 PR PC13 PR PC12 PR PC11 PR PC10 PR PC9 PR PC8 PR PC7 PR PC6 PR PC5 PR PC4 PR PC3 PR PC2 PR PC1 PR PC0 PR Bit Bit Name Initial Value R W Description 15 0 R Reserved This bit is always read as 0 and cannot be modified 14 PC14PR Pin state R 13 PC13PR Pin state R 12 PC12PR Pin state R 11 PC11PR Pin state R 10 PC10PR Pin state R 9 PC9PR Pin state R 8 PC8PR Pin state R 7 PC7PR ...

Page 1370: ... O PD7 I O D23 I O IRQ7 input SCS1 I O TCLKD input TIOC2B I O PD6 I O D22 I O IRQ6 input SSO1 I O TCLKC input TIOC2A I O PD5 I O D21 I O IRQ5 input SSI1 I O TCLKB input TIOC1B I O PD4 I O D20 I O IRQ4 input SSCK1 I O TCLKA input TIOC1A I O PD3 I O D19 I O IRQ3 input SCS0 I O DACK3 output TIOC0D I O PD2 I O D18 I O IRQ2 input SSO0 I O DREQ3 input TIOC0C I O PD1 I O D17 I O IRQ1 input SSI0 I O DACK2...

Page 1371: ...tate not the register value is returned directly If a value is written to PDDRL although that value is written into PDDRL it does not affect the pin state Table 26 8 summarizes PDDRL read write operation 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W PD15 DR PD14 DR PD13 DR PD12 DR PD11 DR ...

Page 1372: ...RL Pin Function Read Operation Write Operation 0 General input Pin state Can write to PDDRL but it has no effect on pin state Other than general input Pin state Can write to PDDRL but it has no effect on pin state 1 General output PDDRL value Value written is output from pin Other than general output PDDRL value Can write to PDDRL but it has no effect on pin state ...

Page 1373: ... 1 0 Bit Initial value R W R R R R R R R R R R R R R R R R PD15 PR PD14 PR PD13 PR PD12 PR PD11 PR PD10 PR PD9 PR PD8 PR PD7 PR PD6 PR PD5 PR PD4 PR PD3 PR PD2 PR PD1 PR PD0 PR Bit Bit Name Initial Value R W Description 15 PD15PR Pin state R 14 PD14PR Pin state R 13 PD13PR Pin state R 12 PD12PR Pin state R 11 PD11PR Pin state R 10 PD10PR Pin state R 9 PD9PR Pin state R 8 PD8PR Pin state R 7 PD7PR ...

Page 1374: ...E7 I O FRAME output IRQ3 input TxD2 output DACK1 output PE6 I O A25 output IRQ2 input RxD2 input DREQ1 input PE5 I O A24 output IRQ1 input TxD1 output DACK0 output PE4 I O A23 output IRQ0 input RxD1 input DREQ0 input PE3 I O A22 output SCK1 I O PE2 I O A21 output SCK0 I O PE1 I O CS4 output MRES input TxD0 output PE0 I O BS output RxD0 input ADTRG input Figure 26 5 Port E 26 6 1 Register Descripti...

Page 1375: ...register value is returned directly If a value is written to PEDRL although that value is written into PEDRL it does not affect the pin state Table 26 10 summarizes PEDRL read write operation 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W PE15 DR PE14 DR PE13 DR PE12 DR PE11 DR PE10 DR PE9 ...

Page 1376: ...RL Pin Function Read Operation Write Operation 0 General input Pin state Can write to PEDRL but it has no effect on pin state Other than general input Pin state Can write to PEDRL but it has no effect on pin state 1 General output PEDRL value Value written is output from pin Other than general output PEDRL value Can write to PEDRL but it has no effect on pin state ...

Page 1377: ...e external pin R R R R R R R R R R R R R R R R PE15 PR PE14 PR PE13 PR PE12 PR PE11 PR PE10 PR PE9 PR PE8 PR PE7 PR PE6 PR PE5 PR PE4 PR PE3 PR PE2 PR PE1 PR PE0 PR Bit Bit Name Initial Value R W Description 15 PE15PR Pin state R 14 PE14PR Pin state R 13 PE13PR Pin state R 12 PE12PR Pin state R 11 PE11PR Pin state R 10 PE10PR Pin state R 9 PE9PR Pin state R 8 PE8PR Pin state R 7 PE7PR Pin state R ...

Page 1378: ...put PF17 I O FCE output LCD_CL1 output PF16 I O FRB input LCD_DON output PF15 I O NAF7 I O LCD_DATA15 output PF14 I O NAF6 I O LCD_DATA14 output PF13 I O NAF5 I O LCD_DATA13 output PF12 I O NAF4 I O LCD_DATA12 output PF11 I O NAF3 I O LCD_DATA11 output PF10 I O NAF2 I O LCD_DATA10 output PF9 I O NAF1 I O LCD_DATA9 output PF8 I O NAF0 I O LCD_DATA8 output PF7 I O FSC output LCD_DATA7 output SCS1 I ...

Page 1379: ...RH PFDRL PFDRH and PFDRL are 16 bit readable writable registers that store port F data The PF30DR to PF0DR bits correspond to the PF30 AUDIO_CLK to PF0 TCLKA LCD_DATA0 SSCK0 pins respectively When a pin function is general output if a value is written to PEDRH or PEDRL that value is output directly from the pin and if PEDRH or PEDRL is read the register value is returned directly regardless of the...

Page 1380: ...F28 DR PF27 DR PF26 DR PF25 DR PF24 DR PF23 DR PF22 DR PF21 DR PF20 DR PF19 DR PF18 DR PF17 DR PF16 DR Bit Bit Name Initial Value R W Description 15 0 R Reserved This bit is always read as undefined The write value should always be 0 14 PF30DR 0 R W 13 PF29DR 0 R W 12 PF28DR 0 R W 11 PF27DR 0 R W 10 PF26DR 0 R W 9 PF25DR 0 R W 8 PF24DR 0 R W 7 PF23DR 0 R W 6 PF22DR 0 R W 5 PF21DR 0 R W 4 PF20DR 0 ...

Page 1381: ...W R W R W R W R W R W R W PF15 DR PF14 DR PF13 DR PF12 DR PF11 DR PF10 DR PF9 DR PF8 DR PF7 DR PF6 DR PF5 DR PF4 DR PF3 DR PF2 DR PF1 DR PF0 DR Bit Bit Name Initial Value R W Description 15 PF15DR 0 R W 14 PF14DR 0 R W 13 PF13DR 0 R W 12 PF12DR 0 R W 11 PF11DR 0 R W 10 PF10DR 0 R W 9 PF9DR 0 R W 8 PF8DR 0 R W 7 PF7DR 0 R W 6 PF6DR 0 R W 5 PF5DR 0 R W 4 PF4DR 0 R W 3 PF3DR 0 R W 2 PF2DR 0 R W 1 PF1...

Page 1382: ...FIORH PFIORL Pin Function Read Operation Write Operation 0 General input Pin state Can write to PFDRH PFDRL but it has no effect on pin state Other than general input Pin state Can write to PFDRH PFDRL but it has no effect on pin state 1 General output PFDRH PFDRL value Value written is output from pin Other than general output PFDRH PFDRL value Can write to PFDRH PFDRL but it has no effect on pin...

Page 1383: ...al value R W 0 R R R R R R R R R R R R R R R R PF30 PR PF29 PR PF28 PR PF27 PR PF26 PR PF25 PR PF24 PR PF23 PR PF22 PR PF21 PR PF20 PR PF19 PR PF18 PR PF17 PR PF16 PR Bit Bit Name Initial Value R W Description 15 0 R Reserved This bit is always read as 0 The write value should always be 0 14 PF30PR Pin state R 13 PF29PR Pin state R 12 PF28PR Pin state R 11 PF27PR Pin state R 10 PF26PR Pin state R ...

Page 1384: ...PR PF6 PR PF5 PR PF4 PR PF3 PR PF2 PR PF1 PR PF0 PR Bit Bit Name Initial Value R W Description 15 PF15PR Pin state R 14 PF14PR Pin state R 13 PF13PR Pin state R 12 PF12PR Pin state R 11 PF11PR Pin state R 10 PF10PR Pin state R 9 PF9PR Pin state R 8 PF8PR Pin state R 7 PF7PR Pin state R 6 PF6PR Pin state R 5 PF5PR Pin state R 4 PF4PR Pin state R 3 PF3PR Pin state R 2 PF2PR Pin state R 1 PF1PR Pin s...

Page 1385: ...ing pin functions the pin state cannot be read by accessing data registers or port registers A25 to A21 A1 and A0 address bus D31 to D16 data bus BS CS7 CS4 to CS1 CS5 CE1A CS6 CE1B CE2A and CE2B RD WR WE3 DQMUU AH ICIOWR WE2 DQMUL ICIORD WE1 DQMLU WE and WE0 DQMLL RASU RASL CASU and CASL CKE FRAME WAIT BREQ BACK IOIS16 MRES ...

Page 1386: ...Section 26 I O Ports Rev 0 50 May 18 2006 Page 1356 of 1588 REJ09B0313 0050 ...

Page 1387: ...e enable bits Retention or non retention of data by the on chip RAM for data retention in deep standby mode is selectable on a per page basis 27 1 Features Memory map The on chip RAM is located in the address spaces shown in tables 27 1 and 27 2 Table 27 1 Address Spaces of On Chip High Speed RAM Page Address Page 0 H FFF80000 to H FFF83FFF Page 1 H FFF84000 to H FFF87FFF Page 2 H FFF88000 to H FF...

Page 1388: ...bus M bus Note that the F bus is connected only to the read ports The F bus and M bus are used for access by the CPU and the ID bus is used for access by the DMAC Each page of the on chip RAM for data retention has one read and write port and is connected to the peripheral bus Priority When the same page of the on chip high speed RAM is accessed from different buses simultaneously the access is pr...

Page 1389: ...ble For example no conflict will arise if different pages are accessed by each bus 27 2 2 RAME and RAMWE Bits Before disabling memory operation or write access to the on chip high speed RAM through the RAME or RAMWE bit be sure to read from any address and then write to the same address in each page otherwise the last written data in each page may not be actually written to the RAM For page 0 MOV ...

Page 1390: ...he addresses within 16 bytes of the last address in the on chip RAM for data retention i e at addresses H FFFFBFF0 to H FFFFBFFF If an instruction is placed at any of these prohibited locations an overrun may cause the CPU to fetch from the address space H FFFFC000 and subsequent addresses for the on chip peripheral modules and this will lead to an address error ...

Page 1391: ...wer down modes functions of CPU clocks on chip memory or part of on chip peripheral modules are halted or the power supply is turned off through which low power consumption is achieved These modes are canceled by a reset or interrupt 28 1 Features 28 1 1 Power Down Modes This LSI has the following power down modes and function 1 Sleep mode 2 Software standby mode 3 Deep standby mode 4 Module stand...

Page 1392: ... Canceling Procedure Sleep mode Execute SLEEP instruction with STBY bit in STBCR cleared to 0 Runs Halts Held Runs Runs Runs Runs 2 Runs Auto refreshing Interrupt Manual reset Power on reset DMA address error Software standby mode Execute SLEEP instruction with STBY bit in STBCR set to 1 and DEEP bit to 0 Halts Halts Held Halts contents are held Halts contents are held Halts Runs 2 Runs Self refre...

Page 1393: ...or set to high impedance For details see appendix A Pin States 2 RTC operates when the START bit in the RCR2 register is set to 1 For details see section 14 Realtime Clock RTC 3 Setting the bits RAMKP3 to RAMKP0 in the RAMKP register to 1 enables to retain the data in the corresponding area on the on chip RAM during the transition to deep standby 4 Deep standby mode can be canceled by an interrupt...

Page 1394: ...7E H FFFE0408 8 Standby control register 4 STBCR4 R W H FF H FFFE040C 8 Standby control register 5 STBCR5 R W H FF H FFFE0410 8 Standby control register 6 STBCR6 R W H FF H FFFE0414 8 System control register 1 SYSCR1 R W H FF H FFFE0402 8 System control register 2 SYSCR2 R W H FF H FFFE0404 8 System control register 3 SYSCR3 R W H 00 H FFFE0418 8 Deep standby control register DSCTR R W H 00 H FFFF...

Page 1395: ...0 0 0 0 0 R W R W R R R R R R Bit Initial value R W STBY DEEP Bit Bit Name Initial Value R W Description 7 6 STBY DEEP 0 0 R W R W Software Standby Deep Standby Specifies transition to software standby mode or deep standby mode 0x Executing SLEEP instruction puts chip into sleep mode 10 Executing SLEEP instruction puts chip into software standby mode 11 Executing SLEEP instruction puts chip into d...

Page 1396: ...R W R W R W R R R R Bit Initial value R W MSTP 10 MSTP 9 MSTP 8 MSTP 7 Bit Bit Name Initial Value R W Description 7 MSTP10 0 R W Module Stop 10 When the MSTP10 bit is set to 1 the supply of the clock to the H UDI is halted 0 H UDI runs 1 Clock supply to H UDI halted 6 MSTP9 0 R W Module Stop 9 When the MSTP9 bit is set to 1 the supply of the clock to the UBC is halted 0 UBC runs 1 Clock supply to ...

Page 1397: ... restarted by clearing the MSTP7 bit to 0 To restart the supply of the clock to the FPU after it was halted reset the LSI by a power on reset 0 FPU runs 1 Clock supply to FPU is halted 3 to 0 All 0 R Reserved These bits are always read as 0 The write value should always be 0 28 2 3 Standby Control Register 3 STBCR3 STBCR3 is an 8 bit readable writable register that controls the operation of module...

Page 1398: ... standby mode 1 The pin is set to high impedance in software standby mode 6 1 R Reserved This bit is always read as 1 The write value should always be 1 5 MSTP35 1 R W Module Stop 35 When the MSTP35 bit is set to 1 the supply of the clock to the MTU2 is halted 0 MTU2 runs 1 Clock supply to MTU2 is halted 4 3 All 1 R Reserved These bits are always read as 1 The write value should always be 1 2 MSTP...

Page 1399: ...r see section 28 4 Usage Notes 7 6 5 4 3 2 1 0 1 1 1 1 1 1 R W R W R W R W R W R W 1 R W 1 R Bit Initial value R W MSTP 46 MSTP 47 MSTP 45 MSTP 44 MSTP 41 MSTP 40 MSTP 42 Bit Bit Name Initial Value R W Description 7 MSTP47 1 R W Module Stop 47 When the MSTP47 bit is set to 1 the supply of the clock to the SCIF0 is halted 0 SCIF0 runs 1 Clock supply to SCIF0 is halted 6 MSTP46 1 R W Module Stop 46 ...

Page 1400: ...always read as 1 The write value should always be 1 2 MSTP42 1 R W Module Stop 42 When the MSTP42 bit is set to 1 the supply of the clock to the CMT is halted 0 CMT runs 1 Clock supply to CMT is halted 1 MSTP41 1 R W Module Stop 41 When the MSTP41 bit is set to 1 the supply of the clock to the LCDC is halted 0 LCDC runs 1 Clock supply to LCDC is halted 0 MSTP40 1 R W Module Stop 40 When the MSTP40...

Page 1401: ...Bit Name Initial Value R W Description 7 MSTP57 1 R W Module Stop 57 When the MSTP57 bit is set to 1 the supply of the clock to the IIC3 0 is halted 0 IIC3 0 runs 1 Clock supply to IIC3 0 is halted 6 MSTP56 1 R W Module Stop 56 When the MSTP56 bit is set to 1 the supply of the clock to the IIC3 1 is halted 0 IIC3 1 runs 1 Clock supply to IIC3 1 is halted 5 MSTP55 1 R W Module Stop 55 When the MSTP...

Page 1402: ...0 is halted 2 MSTP52 1 R W Module Stop 52 When the MSTP52 bit is set to 1 the supply of the clock to the RCAN1 is halted 0 RCAN1 runs 1 Clock supply to RCAN1 is halted 1 MSTP51 1 R W Module Stop 51 When the MSTP51 bit is set to 1 the supply of the clock to the SSU0 is halted 0 SSU0 runs 1 Clock supply to SSU0 is halted 0 MSTP50 1 R W Module Stop 50 When the MSTP50 bit is set to 1 the supply of the...

Page 1403: ...it Name Initial Value R W Description 7 MSTP67 1 R W Module Stop 67 When the MSTP67 bit is set to 1 the supply of the clock to the SSI0 is halted 0 SSI0 runs 1 Clock supply to SSI0 is halted 6 MSTP66 1 R W Module Stop 66 When the MSTP66 bit is set to 1 the supply of the clock to the SSI1 is halted 0 SSI1 runs 1 Clock supply to SSI1 is halted 5 MSTP65 1 R W Module Stop 65 When the MSTP65 bit is set...

Page 1404: ... Bit Bit Name Initial Value R W Description 3 to 1 All 1 R Reserved These bits are always read as 1 The write value should always be 1 0 MSTP60 1 R W Module Stop 60 When the MSTP60 bit is set to 1 the supply of the clock to the USB is halted 0 USB runs 1 Clock supply to USB is halted ...

Page 1405: ...ecute an instruction to read from or write to the same arbitrary address in each page before setting the RAME bit If such an instruction is not executed the data last written to each page may not be written to the on chip RAM high speed Furthermore an instruction to access the on chip RAM high speed should not be located immediately after the instruction to write to SYSCR1 If an on chip RAM high s...

Page 1406: ...speed enabled 2 RAME2 1 R W RAM Enable 2 corresponding area of on chip RAM high speed page 2 0 Access to on chip RAM high speed disabled 1 Access to on chip RAM high speed enabled 1 RAME1 1 R W RAM Enable 1 corresponding area of on chip RAM high speed page 1 0 Access to on chip RAM high speed disabled 1 Access to on chip RAM high speed enabled 0 RAME0 1 R W RAM Enable 0 corresponding area of on ch...

Page 1407: ...n chip RAM high speed Furthermore an instruction to access the on chip RAM high speed should not be located immediately after the instruction to write to SYSCR2 If an on chip RAM high speed access instruction is set normal access is not guaranteed When setting the RAME bit to 1 to enable write to the on chip RAM high speed an instruction to read SYSCR2 should be located immediately after the instr...

Page 1408: ...te to on chip RAM high speed disabled 1 Write to on chip RAM high speed enabled Note For addresses in each page see section 27 On Chip RAM 28 2 9 System Control Register 3 SYSCR3 SYSCR3 is an 8 bit readable writable register that performs the software reset control for the SSI0 to SSI3 Only byte access is valid Note When writing to this register see section 28 4 Usage Notes 7 6 5 4 3 2 1 0 0 0 0 0...

Page 1409: ...t Controls the SSI2 reset by software 0 Cancels the SSI2 reset 1 Puts the SSI2 in the reset state 1 SSI1SRST 0 R W SSI1 Software Reset Controls the SSI1 reset by software 0 Cancels the SSI1 reset 1 Puts the SSI1 in the reset state 0 SSI0SRST 0 R W SSI0 Software Reset Controls the SSI0 reset by software 0 Cancels the SSI0 reset 1 Puts the SSI0 in the reset state ...

Page 1410: ...age Notes 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R R R R R W R W R W R W Bit Initial value R W RRAM KP3 RRAM KP2 RRAM KP0 RRAM KP1 Bit Bit Name Initial Value R W Description 7 to 4 All 0 R Reserved These bits are always read as 0 The write value should always be 0 3 RRAMKP3 0 R W RRAM Storage Area 3 corresponding area of on chip RAM for data retention page 3 0 The contents of the corresponding on chip RA...

Page 1411: ...etained in deep standby mode 1 The contents of the corresponding on chip RAM for data retention area are retained in deep standby mode 0 RRAMKP0 0 R W RRAM Storage Area 0 corresponding area of on chip RAM for data retention page 0 0 The contents of the corresponding on chip RAM for data retention area are not retained in deep standby mode 1 The contents of the corresponding on chip RAM for data re...

Page 1412: ...ame Initial Value R W Description 7 CS0KEEPE 0 R W Retention of External Bus Control Pin State 0 The state of the external bus control pins is not retained when returning from deep standby mode 1 The state of the external bus control pins is retained when returning from deep standby mode 6 RAMBOOT 0 R W Selection of Method to Return from Deep Standby Mode If deep standby mode is canceled by the MR...

Page 1413: ...bits are always read as 0 The write value should always be 0 8 MRES 0 R W Return from Deep Standby Mode by Manual Reset 0 The system does not return from deep standby mode by manual reset 1 The system returns from deep standby mode by manual reset 7 IRQ7 0 R W Return from Deep Standby Mode by IRQ7 0 The system does not return from deep standby mode by the IRQ7 interrupt 1 The system returns from d...

Page 1414: ...pt 1 The system returns from deep standby mode by the IRQ3 interrupt 2 IRQ2 0 R W Return from Deep Standby Mode by IRQ2 0 The system does not return from deep standby mode by the IRQ2 interrupt 1 The system returns from deep standby mode by the IRQ2 interrupt 1 IRQ1 0 R W Return from Deep Standby Mode by IRQ1 0 The system does not return from deep standby mode by the IRQ1 interrupt 1 The system re...

Page 1415: ...ust be cleared immediately before transition to deep standby mode Note When writing to this register see section 28 4 Usage Notes 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R W R W R W R W R W R W R W R W R W R W Note Only 0 can be written after reading 1 to clear the flag IO KEEP MRESF NMIF IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Bit Initial value ...

Page 1416: ...errupt on IRQ6 pin 5 IRQ5F 0 R W IRQ5 Flag 0 No interrupt on IRQ5 pin 1 Interrupt on IRQ5 pin 4 IRQ4F 0 R W IRQ4 Flag 0 No interrupt on IRQ4 pin 1 Interrupt on IRQ4 pin 3 IRQ3F 0 R W IRQ3 Flag 0 No interrupt on IRQ3 pin 1 Interrupt on IRQ3 pin 2 IRQ2F 0 R W IRQ2 Flag 0 No interrupt on IRQ2 pin 1 Interrupt on IRQ2 pin 1 IRQ1F 0 R W IRQ1 Flag 0 No interrupt on IRQ1 pin 1 Interrupt on IRQ1 pin 0 IRQ0...

Page 1417: ...an interrupt NMI IRQ and on chip peripheral module a DMA address error or a reset manual reset or power on reset Canceling by an interrupt When an NMI IRQ or on chip peripheral module interrupt occurs sleep mode is canceled and interrupt exception handling is executed When the priority level of the generated interrupt is equal to or lower than the interrupt mask level that is set in the status reg...

Page 1418: ... on chip peripheral module registers in software standby mode see section 30 3 Register States in Each Operating Mode The CPU takes one cycle to finish writing to STBCR and then executes processing for the next instruction However it takes one or more cycles to actually write Therefore execute a SLEEP instruction after reading STBCR to have the values written to STBCR by the CPU to be definitely r...

Page 1419: ...celing software standby mode by the NMI interrupt or IRQ interrupt set the CKS 2 0 bits so that the WDT overflow period will be equal to or longer than the oscillation settling time The clock output phase of the CKIO pin may be unstable immediately after detecting an interrupt and until software standby mode is canceled When software standby mode is canceled by the falling edge of the NMI pin the ...

Page 1420: ...ICR0 is set to 0 falling edge detection the NMI interrupt is accepted When the NMIE bit is set to 1 rising edge detection by the NMI exception service routine the STBY and DEEP bits in STBCR are set to 1 and 0 respectively and a SLEEP instruction is executed software standby mode is entered Thereafter software standby mode is canceled when the NMI pin is changed from low to high level CK NMI pin N...

Page 1421: ... mode is as follows Figure 28 2 also shows its flowchart 1 Set the RRAMKP3 to RRAMKP0 bits in DSCTR for the corresponding on chip RAM for data retention area that must be retained Transfer the programs to be retained to the specified areas of the on chip RAM for data retention 2 When returning from deep standby mode by an interrupt set the corresponding bit in DSSSR to select the interrupt to canc...

Page 1422: ... RRAMKP bit in DSCTR as needed Transfer data that needs to be retained to the corresponding area Set the corresponding bit in DSSSR as needed Set the registers of the INTC as needed Perform read write to the same arbitrary address in each retention page of the on chip RAM for data retention Set the STBY and DEEP bits in STBCR to 1 Figure 28 2 Flowchart of Transition to Deep Standby Mode ...

Page 1423: ...oscillation settling time The RES pin is held low during oscillation settling time Detect RES Power on reset exception handling Read PC from H 00000000 Read SP from H 00000004 Power on reset exception handling Read PC from H 00000000 Read SP from H 00000004 Power on reset exception handling Read PC from H FFFF8000 Read SP from H FFFF8004 To the initialization routine Check the flags in DSFR Reconf...

Page 1424: ...executed The clock output phase of the CKIO pin may be unstable immediately after detecting an interrupt and until deep standby mode is canceled When deep standby mode is canceled by the falling edge of the NMI pin the NMI pin should be high when the CPU enters deep standby mode when the clock pulse stops and should be low when the CPU returns from deep standby mode when the clock is initiated aft...

Page 1425: ...rol pins are not retained For other pins the retention of their states is cancelled when the IOKEEP bit is cleared 0 1 On chip RAM for data retention The states of the external bus control pins are not retained After cancellation of deep standby mode the retention of the external bus control pin states is cancelled For other pins the retention of their states is cancelled when the IOKEEP bit is cl...

Page 1426: ...etention after cancellation of deep standby mode both the external bus control pins and other pins continues to retain the pin states until writing 0 to the IOKEEP bit in DSFR after reading 1 from the same bit Reconfiguration of peripheral functions is required to return to the previous state of deep standby mode Peripheral functions include all functions such as CPG INTC BSC I O ports PFC and per...

Page 1427: ...able a module before placing it in the module standby mode In addition do not access the module s registers while it is in the module standby state For details on the states of registers see section 30 3 Register States in Each Operating Mode 2 Canceling Module Standby Function The module standby function can be canceled by clearing each MSTP bit to 0 or by a power on reset only possible for RTC H...

Page 1428: ...ting to the register related to power down modes the CPU after executing a write instruction executes the next instruction without waiting for the write operation to complete Therefore to reflect the change specified by writing to the register while the next instruction is executed insert a dummy read of the same register between the register write instruction and the next instruction ...

Page 1429: ...s The user debugging interface H UDI has reset and interrupt request functions The H UDI in this LSI is used for emulator connection Refer to the emulator manual for the method of connecting the emulator Figure 29 1 shows a block diagram of the H UDI SDBPR SDIR SDIR TCK TDO TDI TMS TRST SDBPR MUX Shift register TAP control circuit Decoder Local bus Legend Bypass register Instruction register Figur...

Page 1430: ... the H UDI function See section 29 4 2 Reset Configuration for more information H UDI serial data input pin TDI Input Data transfer to the H UDI is executed by changing this signal in synchronization with TCK H UDI serial data output pin TDO Output Data read from the H UDI is executed by reading this pin in synchronization with TCK The initial value of the data output timing is the TCK falling edg...

Page 1431: ... is a 16 bit read only register It is initialized by TRST assertion or in the TAP test logic reset state and can be written to by the H UDI irrespective of the CPU mode Operation is not guaranteed if a reserved command is set in this register The initial value is H EFFD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Note The initial value of the TI 7 0 bits is a reserved value When setting a command the TI...

Page 1432: ...on 1 0 R Reserved This bit is always read as 0 0 1 R Reserved This bit is always read as 1 Table 29 3 H UDI Commands Bits 15 to 8 TI7 TI6 TI5 TI4 TI3 TI2 TI1 TI0 Description 0 1 1 0 H UDI reset negate 0 1 1 1 H UDI reset assert 1 0 0 1 1 1 0 0 TDO change timing switch 1 0 1 1 H UDI interrupt 1 1 1 1 BYPASS mode Other than above Reserved ...

Page 1433: ...IR Shift IR Exit1 IR Pause IR Exit2 IR Update IR Select IR 0 0 1 0 0 0 1 0 1 1 1 0 Figure 29 2 TAP Controller State Transitions Note The transition condition is the TMS value at the rising edge of TCK The TDI value is sampled at the rising edge of TCK shifting occurs at the falling edge of TCK For details on change timing of the TDO value see section 29 4 3 TDO Output Timing The TDO is at high imp...

Page 1434: ... 3 TDO Output Timing The initial value of the TDO change timing is to perform data output from the TDO pin on the TCK falling edge However setting a TDO change timing switch command in SDIR via the H UDI pin and passing the Update IR state synchronizes the TDO change timing to the TCK rising edge Hereafter to synchronize the change timing of TD0 to the falling edge of TCK the TRST pin must be simu...

Page 1435: ...e same as time for keeping the RES pin low to apply a power on reset H UDI reset assert H UDI reset negate SDIR Chip internal reset CPU state Fetch the initial values of PC and SR from the exception handling vector table Figure 29 4 H UDI Reset 29 4 5 H UDI Interrupt The H UDI interrupt function generates an interrupt by setting a command from the H UDI in SDIR An H UDI interrupt is a general exce...

Page 1436: ...erations is once set 2 In software standby mode and H UDI module standby state all of the functions in the H UDI cannot be used To retain the TAP status before and after standby mode keep TCK high before entering standby mode 3 Regardless of whether the H UDI is used make sure to keep the TRST pin low at power on to initialize the H UDI 4 Make sure to put 20 tcyc or more between the signal change ...

Page 1437: ...on of the register in the corresponding section The register states described are for the basic operating modes If there is a specific reset for an on chip peripheral module refer to the section on that on chip peripheral module 4 Notes when Writing to the On Chip Peripheral Modules To access an on chip module register two or more peripheral module clock Pφ cycles are required Care must be taken i...

Page 1438: ...t priority register 02 IPR02 16 H FFFE081A 16 32 Interrupt priority register 05 IPR05 16 H FFFE0820 16 32 Interrupt priority register 06 IPR06 16 H FFFE0C00 16 32 Interrupt priority register 07 IPR07 16 H FFFE0C02 16 32 Interrupt priority register 08 IPR08 16 H FFFE0C04 16 32 Interrupt priority register 09 IPR09 16 H FFFE0C06 16 32 Interrupt priority register 10 IPR10 16 H FFFE0C08 16 32 Interrupt...

Page 1439: ...us control register CS2BCR 32 H FFFC000C 32 CS3 space bus control register CS3BCR 32 H FFFC0010 32 CS4 space bus control register CS4BCR 32 H FFFC0014 32 CS5 space bus control register CS5BCR 32 H FFFC0018 32 CS6 space bus control register CS6BCR 32 H FFFC001C 32 CS7 space bus control register CS7BCR 32 H FFFC0020 32 CS0 space wait control register CS0WCR 32 H FFFC0028 32 CS1 space wait control re...

Page 1440: ...reload transfer count register_0 CHCR0 32 H FFFE100C 8 16 32 DMA source address register_1 SAR1 32 H FFFE1010 16 32 DMA destination address register_1 DAR1 32 H FFFE1014 16 32 DMA transfer count register_1 DMATCR1 32 H FFFE1018 16 32 DMA channel control register_1 CHCR1 32 H FFFE101C 8 16 32 DMA reload source address register_1 RSAR1 32 H FFFE1110 16 32 DMA reload destination address register_1 RD...

Page 1441: ...source address register_4 SAR4 32 H FFFE1040 16 32 DMA destination address register_4 DAR4 32 H FFFE1044 16 32 DMA transfer count register_4 DMATCR4 32 H FFFE1048 16 32 DMA channel control register_4 CHCR4 32 H FFFE104C 8 16 32 DMA reload source address register_4 RSAR4 32 H FFFE1140 16 32 DMA reload destination address register_4 RDAR4 32 H FFFE1144 16 32 DMA reload transfer count register_4 RDMA...

Page 1442: ... DMA transfer count register_7 DMATCR7 32 H FFFE1078 16 32 DMA channel control register_7 CHCR7 32 H FFFE107C 8 16 32 DMA reload source address register_7 RSAR7 32 H FFFE1170 16 32 DMA reload destination address register_7 RDAR7 32 H FFFE1174 16 32 DMA reload transfer count register_7 RDMATCR7 32 H FFFE1178 16 32 DMA operation register DMAOR 16 H FFFE1200 8 16 DMA extension resource selector 0 DMA...

Page 1443: ...imer mode register_1 TMDR_1 8 H FFFE4381 8 Timer I O control register_1 TIOR_1 8 H FFFE4382 8 Timer interrupt enable register_1 TIER_1 8 H FFFE4384 8 Timer status register_1 TSR_1 8 H FFFE4385 8 Timer counter_1 TCNT_1 16 H FFFE4386 16 Timer general register A_1 TGRA_1 16 H FFFE4388 16 Timer general register B_1 TGRB_1 16 H FFFE438A 16 Timer input capture control register TICCR 8 H FFFE4390 8 Timer...

Page 1444: ... register H_4 TIORH_4 8 H FFFE4206 8 Timer I O control register L_4 TIORL_4 8 H FFFE4207 8 Timer interrupt enable register_4 TIER_4 8 H FFFE4209 8 Timer status register_4 TSR_4 8 H FFFE422D 8 Timer counter_4 TCNT_4 16 H FFFE4212 16 Timer general register A_4 TGRA_4 16 H FFFE421C 16 Timer general register B_4 TGRB_4 16 H FFFE421E 16 Timer general register C_4 TGRC_4 16 H FFFE4228 16 Timer general r...

Page 1445: ... Timer cycle buffer register TCBR 16 H FFFE4222 16 Timer interrupt skipping set register TITCR 8 H FFFE4230 8 Timer interrupt skipping counter TITCNT 8 H FFFE4231 8 Timer buffer transfer set register TBTER 8 H FFFE4232 8 Timer dead time enable register TDER 8 H FFFE4234 8 Timer synchronous clear register TSYCR 8 H FFFE4250 8 Timer waveform control register TWCR 8 H FFFE4260 8 MTU2 Timer output lev...

Page 1446: ... 8 H FFFF2010 8 Minute alarm register RMINAR 8 H FFFF2012 8 Hour alarm register RHRAR 8 H FFFF2014 8 Day of week alarm register RWKAR 8 H FFFF2016 8 Date alarm register RDAYAR 8 H FFFF2018 8 Month alarm register RMONAR 8 H FFFF201A 8 Year alarm register RYRAR 16 H FFFF2020 16 RTC control register 1 RCR1 8 H FFFF201C 8 RTC control register 2 RCR2 8 H FFFF201E 8 RTC RTC control register 3 RCR3 8 H F...

Page 1447: ...erial extension mode register_1 SCEMR_1 16 H FFFE8828 16 Serial mode register_2 SCSMR_2 16 H FFFE9000 16 Bit rate register_2 SCBRR_2 8 H FFFE9004 8 Serial control register_2 SCSCR_2 16 H FFFE9008 16 Transmit FIFO data register_2 SCFTDR_2 8 H FFFE900C 8 Serial status register_2 SCFSR_2 16 H FFFE9010 16 Receive FIFO data register_2 SCFRDR_2 8 H FFFE9014 8 FIFO control register_2 SCFCR_2 16 H FFFE901...

Page 1448: ...egister 2_0 SSTDR2_0 8 H FFFE7008 8 16 SS transmit data register 3_0 SSTDR3_0 8 H FFFE7009 8 SS receive data register 0_0 SSRDR0_0 8 H FFFE700A 8 16 SS receive data register 1_0 SSRDR1_0 8 H FFFE700B 8 SS receive data register 2_0 SSRDR2_0 8 H FFFE700C 8 16 SS receive data register 3_0 SSRDR3_0 8 H FFFE700D 8 SS control register H_1 SSCRH_1 8 H FFFE7800 8 16 SS control register L_1 SSCRL_1 8 H FFF...

Page 1449: ... FFFEE401 8 I2 C bus mode register ICMR_1 8 H FFFEE402 8 I2 C bus interrupt enable register ICIER_1 8 H FFFEE403 8 I2 C bus status register ICSR_1 8 H FFFEE404 8 Slave address register SAR_1 8 H FFFEE405 8 I2 C bus transmit data register ICDRT_1 8 H FFFEE406 8 I2 C bus receive data register ICDRR_1 8 H FFFEE407 8 NF2CYC register NF2CYC_1 8 H FFFEE408 8 I2 C bus control register 1 ICCR1_2 8 H FFFEE...

Page 1450: ... data register 1 SSITDR_1 32 H FFFFC808 32 Receive data register 1 SSIRDR_1 32 H FFFFC80C 32 Control register 2 SSICR_2 32 H FFFFD000 32 Status register 2 SSISR_2 32 H FFFFD004 32 Transmit data register 2 SSITDR_2 32 H FFFFD008 32 Receive data register 2 SSIRDR_2 32 H FFFFD00C 32 Control register 3 SSICR_3 32 H FFFFD800 32 Status register 3 SSISR_3 32 H FFFFD804 32 Transmit data register 3 SSITDR_...

Page 1451: ...2 16 Remote Frame Receive Pending Register 1_0 RFPR1_0 16 H FFFF0048 16 Remote Frame Receive Pending Register 0_0 RFPR0_0 16 H FFFF004A 16 Mailbox Interrupt Mask Register 1_0 MBIMR1_0 16 H FFFF0050 16 Mailbox Interrupt Mask Register 0_0 MBIMR0_0 16 H FFFF0052 16 Unread Message Status Register 1_0 UMSR1_0 16 H FFFF0058 16 Unread Message Status Register 0_0 UMSR0_0 16 H FFFF005A 16 Timer Trigger Con...

Page 1452: ...Mailbox n Data 01_0 n 0 to 31 MBn_DATA_01_0 n 0 to 31 16 H FFFF0108 n 32 8 16 32 Mailbox n Data 23_0 n 0 to 31 MBn_DATA_23_0 n 0 to 31 16 H FFFF010A n 32 8 16 Mailbox n Data 45_0 n 0 to 31 MBn_DATA_45_0 n 0 to 31 16 H FFFF010C n 32 8 16 32 Mailbox n Data 67_0 n 0 to 31 MBn_DATA_67_0 n 0 to 31 16 H FFFF010E n 32 8 16 Mailbox n Control 1_0 n 0 to 31 MBn_CONTROL1_0 n 0 to 31 16 H FFFF0110 n 32 8 16 M...

Page 1453: ...3A 16 Data Frame Receive Pending Register 1_1 RXPR1_1 16 H FFFF0840 16 Data Frame Receive Pending Register 0_1 RXPR0_1 16 H FFFF0842 16 Remote Frame Receive Pending Register 1_1 RFPR1_1 16 H FFFF0848 16 Remote Frame Receive Pending Register 0_1 RFPR0_1 16 H FFFF084A 16 Mailbox Interrupt Mask Register 1_1 MBIMR1_1 16 H FFFF0850 16 Mailbox Interrupt Mask Register 0_1 MBIMR0_1 16 H FFFF0852 16 Unread...

Page 1454: ...16 Mailbox n Local Acceptance Filter Mask 0_1 n 0 to 31 MBn_LAFM0_1 n 0 to 31 16 H FFFF0904 n 32 16 32 Mailbox n Local Acceptance Filter Mask 1_1 n 0 to 31 MBn_LAFM1_1 n 0 to 31 16 H FFFF0906 n 32 16 Mailbox n Data 11_1 n 0 to 31 MBn_DATA_11_1 n 0 to 31 16 H FFFF0908 n 32 8 16 32 Mailbox n Data 23_1 n 0 to 31 MBn_DATA_23_1 n 0 to 31 16 H FFFF090A n 32 8 16 Mailbox n Data 45_1 n 0 to 31 MBn_DATA_45...

Page 1455: ...2 8 16 Common control register FLCMNCR 32 H FFFFF000 32 Command control register FLCMDCR 32 H FFFFF004 32 Command code register FLCMCDR 32 H FFFFF008 32 Address register FLADR 32 H FFFFF00C 32 Address register 2 FLADR2 32 H FFFFF03C 32 Data register FLDATAR 32 H FFFFF010 32 Data counter register FLDTCNTR 32 H FFFFF014 32 Interrupt DMA control register FLINTDMACR 32 H FFFFF018 32 Ready busy timeout...

Page 1456: ...er register D0FIFOTRN 16 H FFFC1C28 16 32 D1FIFO port select register D1FIFOSEL 16 H FFFC1C2A 16 32 D1FIFO port control register D1FIFOCTR 16 H FFFC1C2C 16 32 D1 transaction counter register D1FIFOTRN 16 H FFFC1C2E 16 32 Interrupt enable register 0 INTENB0 16 H FFFC1C30 16 32 Interrupt enable register 1 INTENB1 16 H FFFC1C32 16 32 BRDY interrupt enable register BRDYENB 16 H FFFC1C36 16 32 NRDY int...

Page 1457: ...16 32 Pipe 1 control register PIPE1CTR 16 H FFFC1C70 16 32 Pipe 2 control register PIPE2CTR 16 H FFFC1C72 16 32 Pipe 3 control register PIPE3CTR 16 H FFFC1C74 16 32 Pipe 4 control register PIPE4CTR 16 H FFFC1C76 16 32 Pipe 5 control register PIPE5CTR 16 H FFFC1C78 16 32 Pipe 6 control register PIPE6CTR 16 H FFFC1C7A 16 32 USB Pipe 7 control register PIPE7CTR 16 H FFFC1C7C 16 32 LCDC input clock re...

Page 1458: ... FFFFFC24 16 LCDC power supply sequence period register LDPSPR 16 H FFFFFC26 16 LCDC control register LDCNTR 16 H FFFFFC28 16 LCDC user specified interrupt control register LDUNITR 16 H FFFFFC34 16 LCDC user specified interrupt line number register LDUNITLNR 16 H FFFFFC36 16 LCDC LCDC memory access interval number register LDLIRNR 16 H FFFFFC40 16 Port B I O register L PBIORL 16 H FFFE3886 8 16 Po...

Page 1459: ...RH 16 H FFFE3A84 8 16 32 Port F I O register L PFIORL 16 H FFFE3A86 8 16 Port F control register H4 PFCRH4 16 H FFFE3A88 8 16 32 Port F control register H3 PFCRH3 16 H FFFE3A8A 8 16 Port F control register H2 PFCRH2 16 H FFFE3A8C 8 16 32 Port F control register H1 PFCRH1 16 H FFFE3A8E 8 16 Port F control register L4 PFCRL4 16 H FFFE3A90 8 16 32 Port F control register L3 PFCRL3 16 H FFFE3A92 8 16 ...

Page 1460: ...Standby control register 4 STBCR4 8 H FFFE040C 8 Standby control register 5 STBCR5 8 H FFFE0410 8 Standby control register 6 STBCR6 8 H FFFE0414 8 System control register 1 SYSCR1 8 H FFFE0402 8 System control register 2 SYSCR2 8 H FFFE0404 8 System control register 3 SYSCR3 8 H FFFE0418 8 Deep standby control register DSCTR 8 H FFFF2800 8 Deep standby control register 2 DSCTR2 8 H FFFF2802 8 Deep...

Page 1461: ...1 PFC 0 NMIL NMIE ICR0 IRQ71S IRQ70S IRQ61S IRQ60S IRQ51S IRQ50S IRQ41S IRQ40S ICR1 IRQ31S IRQ30S IRQ21S IRQ20S IRQ11S IRQ10S IRQ01S IRQ00S ICR2 PINT7S PINT6S PINT5S PINT4S PINT3S PINT2S PINT1S PINT0S IRQRR IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F PINTER PINT7E PINT6E PINT5E PINT4E PINT3E PINT2E PINT1E PINT0E PIRR PINT7R PINT6R PINT5R PINT4R PINT3R PINT2R PINT1R PINT0R E15 E14 E13 E12 E11 E...

Page 1462: ...R11 IPR12 IPR13 IPR14 IPR15 IPR16 INTC IPR17 BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16 BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8 BAR_0 BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0 BAM31 BAM30 BAM29 BAM28 BAM27 BAM26 BAM25 BAM24 BAM23 BAM22 BAM21 BAM20 BAM19 BAM18 BAM17 BAM16 BAM15 BAM14 BAM13 BAM12 BAM11 BAM10 BAM9 BAM8 BAMR_0 BAM7 BAM6 BAM5 BAM4 BAM3 BAM2 BAM1 BAM0 UBID DBE C...

Page 1463: ...A27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16 BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8 BAR_1 BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0 BAM31 BAM30 BAM29 BAM28 BAM27 BAM26 BAM25 BAM24 BAM23 BAM22 BAM21 BAM20 BAM19 BAM18 BAM17 BAM16 BAM15 BAM14 BAM13 BAM12 BAM11 BAM10 BAM9 BAM8 BAMR_1 BAM7 BAM6 BAM5 BAM4 BAM3 BAM2 BAM1 BAM0 UBID DBE CP 1 CP 0 BBR_1 CD 1 CD 0 ID 1 ID 0 RW 1 RW 0 SZ 1 SZ 0 BD31 BD30 B...

Page 1464: ...WRWD 0 IWRWS 2 IWRWS 1 IWRWS 0 IWRRD 2 IWRRD 1 IWRRD 0 IWRRS 2 IWRRS 1 IWRRS 0 TYPE 2 TYPE 1 TYPE 0 ENDIAN BSZ 1 BSZ 0 CS0BCR IWW 2 IWW 1 IWW 0 IWRWD 2 IWRWD 1 IWRWD 0 IWRWS 2 IWRWS 1 IWRWS 0 IWRRD 2 IWRRD 1 IWRRD 0 IWRRS 2 IWRRS 1 IWRRS 0 TYPE 2 TYPE 1 TYPE 0 ENDIAN BSZ 1 BSZ 0 CS1BCR IWW 2 IWW 1 IWW 0 IWRWD 2 IWRWD 1 IWRWD 0 IWRWS 2 IWRWS 1 IWRWS 0 IWRRD 2 IWRRD 1 IWRRD 0 IWRRS 2 IWRRS 1 IWRRS 0...

Page 1465: ...0 IWRWD 2 IWRWD 1 IWRWD 0 IWRWS 2 IWRWS 1 IWRWS 0 IWRRD 2 IWRRD 1 IWRRD 0 IWRRS 2 IWRRS 1 IWRRS 0 TYPE 2 TYPE 1 TYPE 0 ENDIAN BSZ 1 BSZ 0 CS5BCR IWW 2 IWW 1 IWW 0 IWRWD 2 IWRWD 1 IWRWD 0 IWRWS 2 IWRWS 1 IWRWS 0 IWRRD 2 IWRRD 1 IWRRD 0 IWRRS 2 IWRRS 1 IWRRS 0 TYPE 2 TYPE 1 TYPE 0 ENDIAN BSZ 1 BSZ 0 CS6BCR IWW 2 IWW 1 IWW 0 IWRWD 2 IWRWD 1 IWRWD 0 IWRWS 2 IWRWS 1 IWRWS 0 IWRRD 2 IWRRD 1 IWRRD 0 IWRR...

Page 1466: ... 25 17 9 1 Bit 24 16 8 0 BAS WW 2 WW 1 WW 0 SW 1 SW 0 WR 3 WR 2 WR 1 CS1WCR 4 WR 0 WM HW 1 HW 0 BAS WR 3 WR 2 WR 1 CS2WCR 1 WR 0 WM A2CL1 CS2WCR 2 A2CL0 BAS WR 3 WR 2 WR 1 CS3WCR 1 WR 0 WM WTRP 1 WTRP 0 WTRCD 1 WTRCD 0 A3CL1 CS3WCR 5 A3CL0 TRWL 1 TRWL 0 WTRC 1 WTRC 0 BAS WW 2 WW 1 WW 0 SW 1 SW 0 WR 3 WR 2 WR 1 CS4WCR 1 WR 0 WM HW 1 HW 0 BST 1 BST 0 BW 1 BW 0 SW 1 SW 0 W 3 W 2 W 1 BSC CS4WCR 2 W 0 ...

Page 1467: ...1 WR 0 WM HW 1 HW 0 SA 1 SA 0 TED 3 TED 2 TED 1 TED 0 PCW 1 PCW 0 PCW 1 CS5WCR 6 PCW 0 WM TEH 3 TEH 2 TEH 1 TEH 0 BAS SW 1 SW 0 WR 3 WR 2 WR 1 CS6WCR 1 WR 0 WM HW 1 HW 0 MPXAW 1 MPXAW 0 MPXMD BW 1 BW 0 W 3 W 2 W 1 CS6WCR 7 W 0 WM SA 1 SA 0 TED 3 TED 2 TED 1 TED 0 PCW 1 PCW 0 PCW 1 CS6WCR 6 PCW 0 WM TEH 3 TEH 2 TEH 1 TEH 0 BAS WW 2 WW 1 WW 0 SW 1 SW 0 WR 3 WR 2 WR 1 CS7WCR 4 WR 0 WM HW 1 HW 0 A2ROW...

Page 1468: ...n Bit 31 23 15 7 Bit 30 22 14 6 Bit 29 21 13 5 Bit 28 20 12 4 Bit 27 19 11 3 Bit 26 18 10 2 Bit 25 17 9 1 Bit 24 16 8 0 RTCSR CMF CMIE CKS 2 CKS 1 CKS 0 RRC 2 RRC 1 RRC 0 RTCNT RTCOR ACSWR ACOSW 3 ACOSW 2 ACOSW 1 ACOSW 0 BSC ACKEYR ACKEY 7 ACKEY 6 ACKEY 5 ACKEY 4 ACKEY 3 ACKEY 2 ACKEY 1 ACKEY 0 SAR0 DAR0 DMAC DMATCR0 ...

Page 1469: ...egister Abbreviation Bit 31 23 15 7 Bit 30 22 14 6 Bit 29 21 13 5 Bit 28 20 12 4 Bit 27 19 11 3 Bit 26 18 10 2 Bit 25 17 9 1 Bit 24 16 8 0 TC RLDSAR RLDDAR DO TL TEMASK HE HIE AM AL DM 1 DM 0 SM 1 SM 0 RS 3 RS 2 RS 1 RS 0 CHCR0 DL DS TB TS 1 TS 0 IE TE DE RSAR0 RDAR0 RDMATCR0 SAR1 DAR1 DMAC DMATCR1 ...

Page 1470: ...egister Abbreviation Bit 31 23 15 7 Bit 30 22 14 6 Bit 29 21 13 5 Bit 28 20 12 4 Bit 27 19 11 3 Bit 26 18 10 2 Bit 25 17 9 1 Bit 24 16 8 0 TC RLDSAR RLDDAR DO TL TEMASK HE HIE AM AL DM 1 DM 0 SM 1 SM 0 RS 3 RS 2 RS 1 RS 0 CHCR1 DL DS TB TS 1 TS 0 IE TE DE RSAR1 RDAR1 RDMATCR1 SAR2 DAR2 DMAC DMATCR2 ...

Page 1471: ...Register Abbreviation Bit 31 23 15 7 Bit 30 22 14 6 Bit 29 21 13 5 Bit 28 20 12 4 Bit 27 19 11 3 Bit 26 18 10 2 Bit 25 17 9 1 Bit 24 16 8 0 TC RLDSAR RLDDAR DO TEMASK HE HIE AM AL DM 1 DM 0 SM 1 SM 0 RS 3 RS 2 RS 1 RS 0 CHCR2 DL DS TB TS 1 TS 0 IE TE DE RSAR2 RDAR2 RDMATCR2 SAR3 DAR3 DMAC DMATCR3 ...

Page 1472: ...Register Abbreviation Bit 31 23 15 7 Bit 30 22 14 6 Bit 29 21 13 5 Bit 28 20 12 4 Bit 27 19 11 3 Bit 26 18 10 2 Bit 25 17 9 1 Bit 24 16 8 0 TC RLDSAR RLDDAR DO TEMASK HE HIE AM AL DM 1 DM 0 SM 1 SM 0 RS 3 RS 2 RS 1 RS 0 CHCR3 DL DS TB TS 1 TS 0 IE TE DE RSAR3 RDAR3 RDMATCR3 SAR4 DAR4 DMAC DMATCR4 ...

Page 1473: ...le Name Register Abbreviation Bit 31 23 15 7 Bit 30 22 14 6 Bit 29 21 13 5 Bit 28 20 12 4 Bit 27 19 11 3 Bit 26 18 10 2 Bit 25 17 9 1 Bit 24 16 8 0 TC RLDSAR RLDDAR TEMASK HE HIE DM 1 DM 0 SM 1 SM 0 RS 3 RS 2 RS 1 RS 0 CHCR4 TB TS 1 TS 0 IE TE DE RSAR4 RDAR4 RDMATCR4 SAR5 DAR5 DMAC DMATCR5 ...

Page 1474: ...le Name Register Abbreviation Bit 31 23 15 7 Bit 30 22 14 6 Bit 29 21 13 5 Bit 28 20 12 4 Bit 27 19 11 3 Bit 26 18 10 2 Bit 25 17 9 1 Bit 24 16 8 0 TC RLDSAR RLDDAR TEMASK HE HIE DM 1 DM 0 SM 1 SM 0 RS 3 RS 2 RS 1 RS 0 CHCR5 TB TS 1 TS 0 IE TE DE RSAR5 RDAR5 RDMATCR5 SAR6 DAR6 DMAC DMATCR6 ...

Page 1475: ...le Name Register Abbreviation Bit 31 23 15 7 Bit 30 22 14 6 Bit 29 21 13 5 Bit 28 20 12 4 Bit 27 19 11 3 Bit 26 18 10 2 Bit 25 17 9 1 Bit 24 16 8 0 TC RLDSAR RLDDAR TEMASK HE HIE DM 1 DM 0 SM 1 SM 0 RS 3 RS 2 RS 1 RS 0 CHCR6 TB TS 1 TS 0 IE TE DE RSAR6 RDAR6 RDMATCR6 SAR7 DAR7 DMAC DMATCR7 ...

Page 1476: ...0RID 1 CH0RID 0 CH3MID 5 CH3MID 4 CH3MID 3 CH3MID 2 CH3MID 1 CH3MID 0 CH3RID 1 CH3RID 0 DMARS1 CH2MID 5 CH2MID 4 CH2MID 3 CH2MID 2 CH2MID 1 CH2MID 0 CH2RID 1 CH2RID 0 CH5MID 5 CH5MID 4 CH5MID 3 CH5MID 2 CH5MID 1 CH5MID 0 CH5RID 1 CH5RID 0 DMARS2 CH4MID 5 CH4MID 4 CH4MID 3 CH4MID 2 CH4MID 1 CH4MID 0 CH4RID 1 CH4RID 0 CH7MID 5 CH7MID 4 CH7MID 3 CH7MID 2 CH7MID 1 CH7MID 0 CH7RID 1 CH7RID 0 DMAC DMARS...

Page 1477: ...TGFD TGFC TGFB TGFA TCNT_0 TGRA_0 TGRB_0 TGRC_0 TGRD_0 TGRE_0 TGRF_0 TIER2_0 TTGE2 TGIEF TGIEE TSR2_0 TGFF TGFE TBTM_0 TTSE TTSB TTSA TCR_1 CCLR 1 CCLR 0 CKEG 1 CKEG 0 TPSC 2 TPSC 1 TPSC 0 TMDR_1 MD 3 MD 2 MD 1 MD 0 TIOR_1 IOB 3 IOB 2 IOB 1 IOB 0 IOA 3 IOA 2 IOA 1 IOA 0 TIER_1 TTGE TCIEU TCIEV TGIEB TGIEA TSR_1 TCFD TCFU TCFV TGFD TGFC TGFB TGFA TCNT_1 TGRA_1 TGRB_1 TICCR I2BE I2AE I1BE I1AE MTU2 ...

Page 1478: ...C TGFB TGFA TCNT_2 TGRA_2 TGRB_2 TCR_3 CCLR 2 CCLR 1 CCLR 0 CKEG 1 CKEG 0 TPSC 2 TPSC 1 TPSC 0 TMDR_3 BFB BFA MD 3 MD 2 MD 1 MD 0 TIORH_3 IOB 3 IOB 2 IOB 1 IOB 0 IOA 3 IOA 2 IOA 1 IOA 0 TIORL_3 IOD 3 IOD 2 IOD 1 IOD 0 IOC 3 IOC 2 IOC 1 IOC 0 TIER_3 TTGE TCIEV TGIED TGIEC TGIEB TGIEA TSR_3 TCFD TCFV TGFD TGFC TGFB TGFA TCNT_3 TGRA_3 TGRB_3 TGRC_3 TGRD_3 TBTM_3 TTSB TTSA TCR_4 CCLR 2 CCLR 1 CCLR 0 C...

Page 1479: ...E2 TCIEV TGIED TGIEC TGIEB TGIEA TSR_4 TCFD TCFV TGFD TGFC TGFB TGFA TCNT_4 TGRA_4 TGRB_4 TGRC_4 TGRD_4 TBTM_4 TTSB TTSA BF 1 BF 0 TADCR UT4AE DT4AE UT4BE DT4BE ITA3AE ITA4VE ITB3AE ITB4VE TADCORA_4 TADCORB_4 TADCOBRA_4 TADCOBRB_4 TSTR CST4 CST3 CST2 CST1 CST0 TSYR SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 TRWER RWE TOER OE4D OE4C OE3D OE4B OE4A OE3B TOCR1 PSYE TOCL TOCS OLSN PLSP TOCR2 BF 1 BF 0 OLS3N OLS3P ...

Page 1480: ... Bit 25 17 9 1 Bit 24 16 8 0 TCDR TDDR TCNTS TCBR TITCR T3AEN 3ACOR 2 3ACOR 1 3ACOR 0 T4VEN 4VCOR 2 4VCOR 1 4VCOR 0 TITCNT 3ACNT 2 3ACNT 1 3ACNT 0 4VCNT 2 4VCNT 1 4VCNT 0 TBTER BTE 1 BTE 0 TDER TDER TSYCR CE0A CE0B CE0C CE0D CE1A CE1B CE2A CE2B TWCR CCE WRE MTU2 TOLBR OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P CMSTR STR1 STR0 CMCSR0 CMF CMIE CKS 1 CKS 0 CMCNT0 CMCOR0 CMCSR1 CMF CMIE CKS 1 CKS 0 CMCNT1 CM...

Page 1481: ... 1 month 0 1000 years 3 1000 years 2 1000 years 1 1000 years 0 100 years 3 100 years 2 100 years 1 100 years 0 RYRCNT 10 years 3 10 years 2 10 years 1 10 years 0 1 year 3 1 year 2 1 year 1 1 year 0 RSECAR ENB 10 seconds 2 10 seconds 1 10 seconds 0 1 second 3 1 second 2 1 second 1 1 second 0 RMINAR ENB 10 minutes 2 10 minutes 1 10 minutes 0 1 minute 3 1 minute 2 1 minute 1 1 minute 0 RHRAR ENB 10 h...

Page 1482: ... DR SCFRDR_0 RSTRG 2 RSTRG 1 RSTRG 0 SCFCR_0 RTRG 1 RTRG 0 TTRG 1 TTRG 0 MCE TFRST RFRST LOOP T 4 T 3 T 2 T 1 T 0 SCFDR_0 R 4 R 3 R 2 R 1 R 0 SCSPTR_0 SCKIO SCKDT SPB2IO SPB2DT SCLSR_0 ORER SCEMR_0 BGDM ABCS SCSMR_1 C A CHR PE O E STOP CKS 1 CKS 0 SCBRR_1 SCSCR_1 TIE RIE TE RE REIE CKE 1 CKE 0 SCFTDR_1 PER 3 PER 2 PER 1 PER 0 FER 3 FER 2 FER 1 FER 0 SCFSR_1 ER TEND TDFE BRK FER PER RDF DR SCFRDR_1...

Page 1483: ...2 TIE RIE TE RE REIE CKE 1 CKE 0 SCFTDR_2 PER 3 PER 2 PER 1 PER 0 FER 3 FER 2 FER 1 FER 0 SCFSR_2 ER TEND TDFE BRK FER PER RDF DR SCFRDR_2 RSTRG 2 RSTRG 1 RSTRG 0 SCFCR_2 RTRG 1 RTRG 0 TTRG 1 TTRG 0 MCE TFRST RFRST LOOP T 4 T 3 T 2 T 1 T 0 SCFDR_2 R 4 R 3 R 2 R 1 R 0 SCSPTR_2 SCKIO SCKDT SPB2IO SPB2DT SCLSR_2 ORER SCEMR_2 BGDM ABCS SCSMR_3 C A CHR PE O E STOP CKS 1 CKS 0 SCBRR_3 SCSCR_3 TIE RIE TE...

Page 1484: ...TSIO CTSDT SCKIO SCKDT SPB2IO SPB2DT SCLSR_3 ORER SCIF SCEMR_3 BGDM ABCS SSCRH_0 MSS BIDE SOL SOLP CSS 1 CSS 0 SSCRL_0 FCLRM SSUMS SRES DATS 1 DATS 0 SSMR_0 MLS CPOS CPHS CKS 2 CKS 1 CKS 0 SSER_0 TE RE TEIE TIE RIE CEIE SSSR_0 ORER TEND TDRE RDRF CE SSCR2_0 SDOS SSCKOS SCSOS TENDSTS SCSATS SSODTS SSTDR0_0 SSTDR1_0 SSTDR2_0 SSTDR3_0 SSRDR0_0 SSRDR1_0 SSRDR2_0 SSRDR3_0 SSCRH_1 MSS BIDE SOL SOLP CSS ...

Page 1485: ...ACKBR ACKBT ICSR_0 TDRE TEND RDRF NACKF STOP AL OVE AAS ADZ SAR_0 SVA 6 SVA 5 SVA 4 SVA 3 SVA 2 SVA 1 SVA 0 FS ICDRT_0 ICDRR_0 NF2CYC_0 PRS NF2CYC ICCR1_1 ICE RCVD MST TRS CKS 3 CKS 2 CKS 1 CKS 0 ICCR2_1 BBSY SCP SDAO SDAOP SCL IICRST ICMR_1 MLS BCWP BC 2 BC 1 BC 0 ICIER_1 TIE TEIE RIE NAKIE STIE ACKE ACKBR ACKBT ICSR_1 TDRE TEND RDRF NACKF STOP AL OVE AAS ADZ SAR_1 SVA 6 SVA 5 SVA 4 SVA 3 SVA 2 S...

Page 1486: ...CVD MST TRS CKS 3 CKS 2 CKS 1 CKS 0 ICCR2_3 BBSY SCP SDAO SDAOP SCL IICRST ICMR_3 MLS BCWP BC 2 BC 1 BC 0 ICIER_3 TIE TEIE RIE NAKIE STIE ACKE ACKBR ACKBT ICSR_3 TDRE TEND RDRF NACKF STOP AL OVE AAS ADZ SAR_3 SVA 6 SVA 5 SVA 4 SVA 3 SVA 2 SVA 1 SVA 0 FS ICDRT_3 ICDRR_3 IIC3 NF2CYC_3 PRS NF2CYC DMEN UIEN OIEN IIEN DIEN CHNL 1 CHNL 0 DWL 2 DWL 1 DWL 0 SWL 2 SWL 1 SWL 0 SCKD SWSD SCKP SWSP SPDP SDTA ...

Page 1487: ...EN DIEN CHNL 1 CHNL 0 DWL 2 DWL 1 DWL 0 SWL 2 SWL 1 SWL 0 SCKD SWSD SCKP SWSP SPDP SDTA PDTA DEL SSICR_1 BREN CKDV 2 CKDV 1 CKDV 0 MUEN CPEN TRMD EN DMRQ UIRQ OIRQ IIRQ DIRQ SSISR_1 CHNO1 CHNO0 SWNO IDST SSITDR_1 SSIRDR_1 DMEN UIEN OIEN IIEN DIEN CHNL 1 CHNL 0 DWL 2 DWL 1 DWL 0 SWL 2 SWL 1 SWL 0 SCKD SWSD SCKP SWSP SPDP SDTA PDTA DEL SSICR_2 BREN CKDV 2 CKDV 1 CKDV 0 MUEN CPEN TRMD EN DMRQ UIRQ OI...

Page 1488: ... 1 SWL 0 SCKD SWSD SCKP SWSP SPDP SDTA PDTA DEL SSICR_3 BREN CKDV 2 CKDV 1 CKDV 0 MUEN CPEN TRMD EN DMRQ UIRQ OIRQ IIRQ DIRQ SSISR_3 CHNO1 CHNO0 SWNO IDST SSITDR_3 SSI SSIRDR_3 MCR15 MCR14 TST 2 TST 1 TST 0 MCR_0 MCR7 MCR6 MCR5 MCR2 MCR1 MCR0 GSR_0 GSR5 GSR4 GSR3 GSR2 GSR1 GSR0 TSEG1 3 TSEG1 2 TSEG1 1 TSEG1 0 TSEG2 2 TSEG2 1 TSEG2 0 BCR1_0 SJW 1 SJW 0 BSP BCR0_0 BRP 7 BRP 6 BRP 5 BRP 4 BRP 3 BRP 2...

Page 1489: ...1_0 TXACK1 7 TXACK1 6 TXACK1 5 TXACK1 4 TXACK1 3 TXACK1 2 TXACK1 1 TXACK1 0 TXACK0 15 TXACK0 14 TXACK0 13 TXACK0 12 TXACK0 11 TXACK0 10 TXACK0 9 TXACK0 8 TXACK0_0 TXACK0 7 TXACK0 6 TXACK0 5 TXACK0 4 TXACK0 3 TXACK0 2 TXACK0 1 ABACK1 15 ABACK1 14 ABACK1 13 ABACK1 12 ABACK1 11 ABACK1 10 ABACK1 9 ABACK1 8 ABACK1_0 ABACK1 7 ABACK1 6 ABACK1 5 ABACK1 4 ABACK1 3 ABACK1 2 ABACK1 1 ABACK1 0 ABACK0 15 ABACK...

Page 1490: ... 5 RTROFF 4 RTROFF 3 RTROFF 2 RTROFF 1 RTROFF 0 RFTROFF_0 TSR_0 TSR4 TSR3 TSR2 TSR1 TSR0 CCR_0 CCR 5 CCR 4 CCR 3 CCR 2 CCR 1 CCR 0 TCNTR 15 TCNTR 14 TCNTR 13 TCNTR 12 TCNTR 11 TCNTR 10 TCNTR 9 TCNTR 8 TCNTR_0 TCNTR 7 TCNTR 6 TCNTR 5 TCNTR 4 TCNTR 3 TCNTR 2 TCNTR 1 TCNTR 0 CYCTR 15 CYCTR 14 CYCTR 13 CYCTR 12 CYCTR 11 CYCTR 10 CYCTR 9 CYCTR 8 CYCTR_0 CYCTR 7 CYCTR 6 CYCTR 5 CYCTR 4 CYCTR 3 CYCTR 2 C...

Page 1491: ...AFM 7 STDID_ LAFM 6 MBn_LAFM0_0 n 0 to 31 9 STDID_ LAFM 5 STDID_ LAFM 4 STDID_ LAFM 3 STDID_ LAFM 2 STDID_ LAFM 1 STDID_ LAFM 0 EXTID_ LAFM 17 EXTID_ LAFM 16 EXTID_ LAFM 15 EXTID_ LAFM 14 EXTID_ LAFM 13 EXTID_ LAFM 12 EXTID_ LAFM 11 EXTID_ LAFM 10 EXTID_ LAFM 9 EXTID_ LAFM 8 MBn_LAFM1_0 n 0 to 31 EXTID_ LAFM 7 EXTID_ LAFM 6 EXTID_ LAFM 5 EXTID_ LAFM 4 EXTID_ LAFM 3 EXTID_ LAFM 2 EXTID_ LAFM 1 EXTI...

Page 1492: ...MBn_ TTCONTROL_0 n 24 to 29 REP_ FACTOR 2 REP_ FACTOR 1 REP_ FACTOR 0 MCR15 MCR14 TST2 TST1 TST0 MCR_1 MCR7 MCR6 MCR5 MCR2 MCR1 MCR0 GSR_1 GSR5 GSR4 GSR3 GSR2 GSR1 GSR0 TSEG13 TSEG12 TSEG11 TSEG10 TSEG22 TSEG21 TSEG20 BCR1_1 SJW1 SJW0 BSP BCR0_1 BRP7 BRP6 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 IRR15 IRR14 IRR13 IRR12 IRR11 IRR10 IRR9 IRR8 IRR_1 IRR7 IRR6 IRR5 IRR4 IRR3 IRR2 IRR1 IRR0 IMR15 IMR14 IMR13 IMR1...

Page 1493: ... ABACK0 3 ABACK0 2 ABACK0 1 RXPR1 15 RXPR1 14 RXPR1 13 RXPR1 12 RXPR1 11 RXPR1 10 RXPR1 9 RXPR1 8 RXPR1_1 RXPR1 7 RXPR1 6 RXPR1 5 RXPR1 4 RXPR1 3 RXPR1 2 RXPR1 1 RXPR1 0 RXPR0 15 RXPR0 14 RXPR0 13 RXPR0 12 RXPR0 11 RXPR0 10 RXPR0 9 RXPR0 8 RXPR0_1 RXPR0 7 RXPR0 6 RXPR0 5 RXPR0 4 RXPR0 3 RXPR0 2 RXPR0 1 RXPR0 0 RFPR1 15 RFPR1 14 RFPR1 13 RFPR1 12 RFPR1 11 RFPR1 10 RFPR1 9 RFPR1 8 RFPR1_1 RFPR1 7 RF...

Page 1494: ...K 7 RFMK 6 RFMK 5 RFMK 4 RFMK 3 RFMK 2 RFMK 1 RFMK 0 TCMR0 15 TCMR0 14 TCMR0 13 TCMR0 12 TCMR0 11 TCMR0 10 TCMR0 9 TCMR0 8 TCMR0_1 TCMR0 7 TCMR0 6 TCMR0 5 TCMR0 4 TCMR0 3 TCMR0 2 TCMR0 1 TCMR0 0 TCMR1 15 TCMR1 14 TCMR1 13 TCMR1 12 TCMR1 11 TCMR1 10 TCMR1 9 TCMR1 8 TCMR1_1 TCMR1 7 TCMR1 6 TCMR1 5 TCMR1 4 TCMR1 3 TCMR1 2 TCMR1 1 TCMR1 0 TCMR2 15 TCMR2 14 TCMR2 13 TCMR2 12 TCMR2 11 TCMR2 10 TCMR2 9 T...

Page 1495: ...SG_DATA0 MSG_DATA0 MBn_DATA_11_1 n 0 to 31 MSG_DATA1 MSG_DATA1 MSG_DATA1 MSG_DATA1 MSG_DATA1 MSG_DATA1 MSG_DATA1 MSG_DATA1 MSG_DATA2 MSG_DATA2 MSG_DATA2 MSG_DATA2 MSG_DATA2 MSG_DATA2 MSG_DATA2 MSG_DATA2 MBn_DATA_23_1 n 0 to 31 MSG_DATA3 MSG_DATA3 MSG_DATA3 MSG_DATA3 MSG_DATA3 MSG_DATA3 MSG_DATA3 MSG_DATA3 MSG_DATA4 MSG_DATA4 MSG_DATA4 MSG_DATA4 MSG_DATA4 MSG_DATA4 MSG_DATA4 MSG_DATA4 MBn_DATA_45_1...

Page 1496: ...H ADF ADIE ADST TRGS 3 TRGS 2 TRGS 1 TRGS 0 ADC ADCSR CKS 1 CKS 0 MDS 2 MDS 1 MDS 0 CH 2 CH 1 CH 0 DADR0 DADR1 DAC DACR DAOE1 DAOE0 DAE SNAND QTSEL FCKSEL ECCPOS 1 ECCPOS 0 ACM 1 ACM 0 NANDWF FLCMNCR CE0 TYPESEL ADRCNT2 SCTCNT 19 SCTCNT 18 SCTCNT 17 SCTCNT 16 ADRMD CDSRC DOSR SELRW DOADR ADRCNT 1 ADRCNT 0 DOCMD2 DOCMD1 SCTCNT 15 SCTCNT 14 SCTCNT 13 SCTCNT 12 SCTCNT 11 SCTCNT 10 SCTCNT 9 SCTCNT 8 F...

Page 1497: ...ADR 22 ADR 21 ADR 20 ADR 19 ADR 18 ADR 17 ADR 16 ADR 15 ADR 14 ADR 13 ADR 12 ADR 11 ADR 10 ADR 9 ADR 8 FLADR 11 ADR 7 ADR 6 ADR 5 ADR 4 ADR 3 ADR 2 ADR 1 ADR 0 FLADR2 ADR 7 ADR 6 ADR 5 ADR 4 ADR 3 ADR 2 ADR 1 ADR 0 ECFLW 7 ECFLW 6 ECFLW 5 ECFLW 4 ECFLW 3 ECFLW 2 ECFLW 1 ECFLW 0 DTFLW 7 DTFLW 6 DTFLW 5 DTFLW 4 DTFLW 3 DTFLW 2 DTFLW 1 DTFLW 0 DTCNT 11 DTCNT 10 DTCNT 9 DTCNT 8 FLDTCNTR DTCNT 7 DTCNT ...

Page 1498: ...T 9 RBTIMCNT 8 FLBSYCNT RBTIMCNT 7 RBTIMCNT 6 RBTIMCNT 5 RBTIMCNT 4 RBTIMCNT 3 RBTIMCNT 2 RBTIMCNT 1 RBTIMCNT 0 DTFO 31 DTFO 30 DTFO 29 DTFO 28 DTFO 27 DTFO 26 DTFO 25 DTFO 24 DTFO 23 DTFO 22 DTFO 21 DTFO 20 DTFO 19 DTFO 18 DTFO 17 DTFO 16 DTFO 15 DTFO 14 DTFO 13 DTFO 12 DTFO 11 DTFO 10 DTFO 9 DTFO 8 FLDTFIFO DTFO 7 DTFO 6 DTFO 5 DTFO 4 DTFO 3 DTFO 2 DTFO 1 DTFO 0 ECFO 31 ECFO 30 ECFO 29 ECFO 28 E...

Page 1499: ...29 FIFOPORT 28 FIFOPORT 27 FIFOPORT 26 FIFOPORT 25 FIFOPORT 24 FIFOPORT 23 FIFOPORT 22 FIFOPORT 21 FIFOPORT 20 FIFOPORT 19 FIFOPORT 18 FIFOPORT 17 FIFOPORT 16 FIFOPORT 15 FIFOPORT 14 FIFOPORT 13 FIFOPORT 12 FIFOPORT 11 FIFOPORT 10 FIFOPORT 9 FIFOPORT 8 D0FIFO FIFOPORT 7 FIFOPORT 6 FIFOPORT 5 FIFOPORT 4 FIFOPORT 3 FIFOPORT 2 FIFOPORT 1 FIFOPORT 0 FIFOPORT 31 FIFOPORT 30 FIFOPORT 29 FIFOPORT 28 FIFO...

Page 1500: ... DTLN 8 D1FIFOCTR DTLN 7 DTLN 6 DTLN 5 DTLN 4 DTLN 3 DTLN 2 DTLN 1 DTLN 0 TRNCNT 15 TRNCNT 14 TRNCNT 13 TRNCNT 12 TRNCNT 11 TRNCNT 10 TRNCNT 9 TRNCNT 8 D1FIFOTRN TRNCNT 7 TRNCNT 6 TRNCNT 5 TRNCNT 4 TRNCNT 3 TRNCNT 2 TRNCNT 1 TRNCNT 0 VBSE RSME SOFE DVSE CTRE BEMPE NRDYE BRDYE INTENB0 URST SADR SCFG SUSP WDST RDST CMPL SERR BCHGE DTCHE INTENB1 ATCHE SIGNE SACKE BRDYM BRDYENB PIPE7 BRDYE PIPE6 BRDYE...

Page 1501: ... 0 USBREQ BMREQUEST TYPE 7 BMREQUEST TYPE 6 BMREQUEST TYPE 5 BMREQUEST TYPE 4 BMREQUEST TYPE 3 BMREQUEST TYPE 2 BMREQUEST TYPE 1 BMREQUEST TYPE 0 WVALUE 15 WVALUE 14 WVALUE 13 WVALUE 12 WVALUE 11 WVALUE 10 WVALUE 9 WVALUE 8 USBVAL WVALUE 7 WVALUE 6 WVALUE 5 WVALUE 4 WVALUE 3 WVALUE 2 WVALUE 1 WVALUE 0 WINDEX 15 WINDEX 14 WINDEX 13 WINDEX 12 WINDEX 11 WINDEX 10 WINDEX 9 WINDEX 8 USBINDX WINDEX 7 WI...

Page 1502: ...STS INBUFM ATREPM ACLRM SQCLR PIPE1CTR SQSET SQMON PID 1 PID 0 BSTS INBUFM ATREPM ACLRM SQCLR PIPE2CTR SQSET SQMON PID 1 PID 0 BSTS INBUFM ATREPM ACLRM SQCLR PIPE3CTR SQSET SQMON PID 1 PID 0 BSTS INBUFM ATREPM ACLRM SQCLR PIPE4CTR SQSET SQMON PID 1 PID 0 BSTS INBUFM ATREPM ACLRM SQCLR PIPE5CTR SQSET SQMON PID 1 PID 0 BSTS INBUFM ACLRM SQCLR PIPE6CTR SQSET SQMON PID 1 PID 0 BSTS INBUFM ACLRM SQCLR ...

Page 1503: ...R PALS PALEN PALDnn23 PALDnn22 PALDnn21 PALDnn20 PALDnn19 PALDnn18 PALDnn17 PALDnn16 PALDnn15 PALDnn14 PALDnn13 PALDnn12 PALDnn11 PALDnn10 PALDnn9 PALDnn8 LDPRnn nn 00 to FF PALDnn7 PALDnn6 PALDnn5 PALDnn4 PALDnn3 PALDnn2 PALDnn1 PALDnn0 HDCN7 HDCN6 HDCN5 HDCN4 HDCN3 HDCN2 HDCN1 HDCN0 LDHCNR HTCN7 HTCN6 HTCN5 HTCN4 HTCN3 HTCN2 HTCN1 HTCN0 HSYNW3 HSYNW2 HSYNW1 HSYNW0 LDHSYNR HSYNP7 HSYNP6 HSYNP5 HS...

Page 1504: ...10 UINTLN9 UINTLN8 LDUINTLNR UINTLN7 UINTLN6 UINTLN5 UINTLN4 UINTLN3 UINTLN2 UINTLN1 UINTLN0 LCDC LDLIRNR LIRN7 LIRN6 LIRN5 LIRN4 LIRN3 LIRN2 LIRN17 LIRN0 PB11IOR PB10IOR PB9IOR PB8IOR PBIORL PBCRL4 PB12MD 1 PB12MD 0 PB11MD 0 PB10MD 0 PBCRL3 PB9MD 1 PB9MD 0 PB8MD 1 PB8MD 0 PB7MD 1 PB7MD 0 PB6MD 1 PB6MD 0 PBCRL2 PB5MD 1 PB5MD 0 PB4MD 1 PB4MD 0 PB3MD 1 PB3MD 0 PB2MD 1 PB2MD 0 PBCRL1 PB1MD 1 PB1MD 0 ...

Page 1505: ...RL2 PD5MD 2 PD5MD 1 PD5MD 0 PD4MD 2 PD4MD 1 PD4MD 0 PD3MD 2 PD3MD 1 PD3MD 0 PD2MD 2 PD2MD 1 PD2MD 0 PDCRL1 PD1MD 2 PD1MD 1 PD1MD 0 PD0MD 2 PD0MD 1 PD0MD 0 PE15IOR PE14IOR PE13IOR PE12IOR PE11IOR PE10IOR PE9IOR PE8IOR PEIORL PE7IOR PE6IOR PE5IOR PE4IOR PE3IOR PE2IOR PE1IOR PE0IOR PE15MD 1 PE15MD 0 PE14MD 1 PE14MD 0 PECRL4 PE13MD 1 PE13MD 0 PE12MD 1 PE12MD 0 PE11MD 2 PE11MD 1 PE11MD 0 PE10MD 2 PE10M...

Page 1506: ...1 PF5MD 0 PF4MD 1 PF4MD 0 PF3MD 1 PF3MD 0 PF2MD 1 PF2MD 0 PFCRL1 PF1MD 1 PF1MD 0 PF0MD 1 PF0MD 0 S3CKS2 S3CKS1 S3CKS0 S2CKS2 S2CKS1 S2CKS0 PFC SCSR S1CKS2 S1CKS1 S1CKS0 S0CKS2 S0CKS1 S0CKS0 PADRL PA7DR PA6DR PA5DR PA4DR PA3DR PA2DR PA1DR PA0DR PB12DR PB11DR PB10DR PB9DR PB8DR PBDRL PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR PB11PR PB10PR PB9PR PB8PR PBPRL PB7PR PB6PR PB5PR PB4PR PB3PR PB2PR P...

Page 1507: ...2DR PF1DR PF0DR PF30PR PF29PR PF28PR PF27PR PF26PR PF25PR PF24PR PFPRH PF23PR PF22PR PF21PR PF20PR PF19PR PF18PR PF17PR PF16PR PF15PR PF14PR PF13PR PF12PR PF11PR PF10PR PF9PR PF8PR I O Ports PFPRL PF7PR PF6PR PF5PR PF4PR PF3PR PF2PR PF1PR PF0PR STBCR STBY DEEP STBCR2 MSTP10 MSTP9 MSTP8 MSTP7 STBCR3 HIZ MSTP35 MSTP32 MSTP31 MSTP30 STBCR4 MSTP47 MSTP46 MSTP45 MSTP44 MSTP43 MSTP42 MSTP41 MSTP40 STBCR...

Page 1508: ... is the memory type 2 When burst ROM clock asynchronous is the memory type 3 When burst ROM clock synchronous is the memory type 4 Normal memory SRAM with byte selection is the memory type 5 When SDRAM is the memory type 6 When PCMCIA is the memory type 7 When burst MPX I O is the memory type 8 When MCR15 0 9 When MCR15 1 10 In command access mode 11 In sector access mode ...

Page 1509: ...nitialized Retained 3 Initialized Retained Retained 3 RTCNT Initialized Retained 4 Initialized Retained Retained 4 BSC Other than above Initialized Retained Initialized Retained Retained DMAC All registers Initialized Retained Initialized Retained Retained Retained 5 MTU2 All registers Initialized Retained Initialized Initialized Initialized Retained CMT All registers Initialized Retained Initiali...

Page 1510: ...itialized Retained ADC All registers Initialized Retained Initialized Initialized Initialized Retained DAC All registers Initialized Retained Initialized Retained Initialized Retained FLCTL All registers Initialized Retained Initialized Retained Retained Retained USB All registers Initialized Retained Initialized Retained Retained Retained LCDC All registers Initialized Retained Initialized Retain...

Page 1511: ...tialized Retained Retained Retained Notes 1 Retains the previous value after an internal power on reset by means of the WDT 2 The BN3 to BN0 bits are initialized 3 Flag handling continues 4 Counting up continues 5 Transfer operations can be continued 6 Bits RTCEN and START are retained 7 Bits BC3 to BC0 are initialized 8 Since pin states are read out on the port A data register PADRL and the port ...

Page 1512: ...Section 30 List of Registers Rev 0 50 May 18 2006 Page 1482 of 1588 REJ09B0313 0050 ...

Page 1513: ...og power supply voltage AVCC 0 3 to 4 6 V Analog reference voltage AVref 0 3 to AVCC 0 3 V USB transceiver analog power supply voltage I O USBAPVCC TBD V USB transceiver digital power supply voltage I O USBDPVCC TBD V USB transceiver analog power supply voltage internal USBAVCC TBD V USB transceiver digital power supply voltage internal USBDVCC TBD V Input voltage Analog input pin VAN 0 3 to AVCC ...

Page 1514: ...en turning on tpwu TBD ms Time lag between 1 2 V and 3 3 V when turning on tpwd TBD ms State undefined time tunc 100 ms Note The table shown above is recommended values so they represent guidelines rather than strict requirements The 3 3 V power supply PVCC AVCC USBDPVCC and USBDPVCC should be turned on before the 1 2 V power supply VCC PLLVCC USBAVCC and USBDVCC is turned on In addition the 3 3 V...

Page 1515: ...onditions PVCC 3 0 3 3 3 6 V Power supply voltage VCC 1 1 1 2 1 3 V PLL power supply voltage PLLVCC 1 1 1 2 1 3 V Analog power supply voltage AVCC 3 0 3 3 3 6 V USBAPVCC USBDPVCC 3 0 3 3 3 6 V USB power supply voltage USBAVCC USBDVCC 1 1 1 2 1 3 V Normal operation ICC 2 TBD TBD mA Sleep mode Isleep 2 TBD TBD mA VCC 1 2 V Iφ 200 MHz Bφ 66 MHz Pφ 33 MHz TBD TBD mA Ta 50 C VCC 1 2 V Software standby ...

Page 1516: ... Kbytes retained TBD TBD µA Ta 50 C VCC 1 2 V RAM 8 Kbytes retained TBD TBD µA Ta 50 C VCC 1 2 V RAM 12 Kbytes retained Supply current 1 Deep standby mode Idstby 2 TBD TBD µA Ta 50 C VCC 1 2 V RAM 16 Kbytes retained All input pins except PB7 to PB0 1 0 µA Input leakage current PB7 to PB0 Iin 10 µA Vin 0 5 to PVCC 0 5 V All input output pins all output pins except PB7 to PB0 and pins with weak keep...

Page 1517: ...Waiting for A D or D A conversion AICC 1 3 µA Analog reference voltage current AIref 2 4 mA Caution When the A D converter or D A converter is not in use the AVCC and AVSS pins should not be open Notes 1 The supply current values are when all output pins and pins with the pull up function are unloaded 2 ICC Isleep Isstby and Industry represent the total currents supplied in the Vcc and PLLVCC syst...

Page 1518: ...CC 0 3 V PA7 to PA0 2 2 AVCC 0 3 V Input high voltage Input pins other than above except Schmitt pins VIH 2 2 PVCC 0 3 V RES MRES NMI MD MD_CLK1 MD_CLK0 ASEMD TRST EXTAL CKIO 0 3 0 5 V Input low voltage Input pins other than above except Schmitt pins VIL 0 3 0 8 V VT PVCC 0 5 V VT 0 5 V Schmitt trigger input characteristics IRQ7 to IRQ0 PINT7 to PINT0 IOIS16 DREQ3 to DREQ0 TIOC0A to TIOC0D TIOC1A ...

Page 1519: ...USBDVCC 1 1 to 1 3 V PVCC USBDPVCC 3 0 to 3 6 V AVCC 3 0 to 3 6 V USBAVCC 1 1 to 1 3 V USBAPVCC 3 0 to 3 6 V VSS PLLVSS PVSS AVSS USBDVSS USBAVSS USBDPVSS USBAPVSS 0 V Ta 20 to 85 C Item Symbol Min Typ Max Unit Test Conditions Input high voltage VIH PVCC 0 7 PVCC 0 3 V Input low voltage VIL 0 3 PVCC 0 3 V Schmitt trigger input characteristics VIH VIL PVCC 0 05 V Output low voltage VOL 0 4 V IOL 3 ...

Page 1520: ...US VIL TBD TBD TBD V Input high voltage USB_X1 VIH TBD TBD TBD V Input low voltage USB_X1 VIL TBD TBD TBD V Note REFRIN VBUS USB_X1 and USB_X2 pins Table 31 3 DC Characteristics 5 USB Related Pins Full Speed and High Speed Common Items Conditions VCC PLLVCC USBDVCC 1 1 to 1 3 V PVCC USBDPVCC 3 0 to 3 6 V AVCC 3 0 to 3 6 V USBAVCC 1 1 to 1 3 V USBAPVCC 3 0 to 3 6 V VSS PLLVSS PVSS AVSS USBDVSS USBA...

Page 1521: ...SS USBAVSS USBDPVSS USBAPVSS 0 V Ta 20 to 85 C Item Symbol Min Typ Max Unit Test Conditions Input high voltage VIH 2 0 V Input low voltage VIL 0 8 V Differential input sensitivity VDI 0 2 V DP DM Differential common mode range VCM 0 8 2 5 V Output high voltage VOH 2 8 TBD V USBAPVCC 3 6 V from 15 kΩ RL to GND Output low voltage VIH TBD 0 3 V USBAPVCC 3 0 V from 1 5 kΩ RL to 3 6 V Single ended rece...

Page 1522: ...40 mV Output low voltage VHSOL 10 0 10 0 mV Chirp J output voltage difference VCHIRPJ 700 1100 mV Chirp K output voltage difference VCHIRPK 900 500 mV Note DP and DM pins Table 31 4 Permissible Output Currents Conditions VCC PLLVCC USBDVCC 1 1 to 1 3 V PVCC USBDPVCC 3 0 to 3 6 V AVCC 3 0 to 3 6 V USBAVCC 1 1 to 1 3 V USBAPVCC 3 0 to 3 6 V VSS PLLVSS PVSS AVSS USBDVSS USBAVSS USBDPVSS USBAPVSS 0 V ...

Page 1523: ...times for input pins must be followed Table 31 5 Maximum Operating Frequency Conditions VCC PLLVCC USBDVCC 1 1 to 1 3 V PVCC USBDPVCC 3 0 to 3 6 V AVCC 3 0 to 3 6 V USBAVCC 1 1 to 1 3 V USBAPVCC 3 0 to 3 6 V VSS PLLVSS PVSS AVSS USBDVSS USBAVSS USBDPVSS USBAPVSS 0 V Ta 20 to 85 C Item Symbol Min Typ Max Unit Remarks CPU Iφ 80 200 MHz Internal bus external bus Bφ 40 66 MHz Operating frequency Perip...

Page 1524: ...z USB_X1 clock input cycle time tEXcyc TBD TBD ns EXTAL AUDIO_X1 AUDIO_CLK clock input low pulse width tEXL 7 ns EXTAL AUDIO_X1 AUDIO_CLK clock input high pulse width tEXH 7 ns USB_X1 clock input duty tEXH tEXL TBD TBD EXTAL AUDIO_X1 AUDIO_CLK USB_ X1 clock input rise time tEXr 4 ns EXTAL AUDIO_X1 AUDIO_CLK USB_ X1 clock input fall time tEXf 4 ns Figure 31 2 CKIO clock input frequency fCK 40 66 MH...

Page 1525: ...dby tOSC2 10 ms Figure 31 6 Oscillation settling time 2 on return from standby tOSC3 10 ms Figure 31 7 RTC clock oscillation settling time tROSC 3 s Figure 31 8 tEXH tEXf tEXr tEXL tEXcyc VIH VIH VIH 1 2 PVcc 1 2 PVcc VIL VIL EXTAL AUDIO_X1 AUDIO_CLK USB_X1 input Note When the clock is input on the EXTAL AUDIO_X1 AUDIO_CLK or USB_X1 pin Figure 31 2 EXTAL AUDIO_X1 AUDIO_CLK and USB_X1 Clock Input T...

Page 1526: ... Vcc Min tOSC1 Vcc RES MRES CKIO Internal clock Oscillation settling time Note Oscillation settling time when the internal oscillator is used Figure 31 5 Power On Oscillation Settling Time CKIO Internal clock Oscillation settling time Standby period tOSC2 RES MRES Note Oscillation settling time when the internal oscillator is used Figure 31 6 Oscillation Settling Time on Return from Standby Return...

Page 1527: ...scillation settling time Standby period tOSC3 NMI IRQ Note Oscillation settling time when the internal oscillator is used Figure 31 7 Oscillation Settling Time on Return from Standby Return by NMI or IRQ RTC clock internal Oscillation settling time PVCC PVCCmin tROSC Figure 31 8 RTC Clock Oscillation Settling Time ...

Page 1528: ...idth tMRESW 20 2 tcyc Figure 31 9 NMI pulse width tNMIW 20 3 tcyc IRQ pulse width tIRQW 20 3 tcyc PINT pulse width tPINTW 20 tcyc Figure 31 10 IRQOUT REFOUT output delay time tIRQOD 100 ns Figure 31 11 BREQ setup time tBREQS 1 2tcyc 7 ns BREQ hold time tBREQH 1 2tcyc 2 ns BACK delay time tBACKD 1 2tcyc 13 ns Bus tri state delay time 1 tBOFF1 0 100 ns Bus tri state delay time 2 tBOFF2 0 100 ns Bus ...

Page 1529: ...6 Page 1499 of 1588 REJ09B0313 0050 RES MRES tRESW tMRESW Figure 31 9 Reset Input Timing NMI tNMIW tIRQW tPINTW IRQ7 to IRQ0 PINT7 to PINT0 Figure 31 10 Interrupt Signal Input Timing tIRQOD tIRQOD CKIO IRQOUT REFOUT Figure 31 11 Interrupt Signal Output Timing ...

Page 1530: ...00 of 1588 REJ09B0313 0050 CKIO HIZCNT 1 BREQ BACK A25 to A0 D31 to D0 RD RD WR RASU L CASU L CSn WEn BS CKE CKIO HIZCNT 0 tBREQH BOFF2 t tBREQS tBACKD tBACKD BON1 t BOFF1 t BOFF2 t BON2 t BON2 t tBREQH tBREQS When HZCNT 0 When HZCNT 1 Figure 31 12 Bus Release Timing ...

Page 1531: ... 13 ns Figures 31 39 31 40 Address setup time tAS 0 ns Figures 31 13 to 31 16 31 21 Address hold time tAH 0 ns Figures 31 13 to 31 16 BS delay time tBSD 13 ns Figures 31 13 to 31 35 31 39 31 41 to 31 44 CS delay time 1 tCSD1 0 or 1 2 13 ns Figures 31 13 to 31 38 31 41 to 31 44 CS delay time 2 tCSD2 1 2tcyc 1 2tcyc 13 ns Figures 31 39 31 40 Read write delay time 1 tRWD1 0 or 1 2 13 ns Figures 31 13...

Page 1532: ...o 31 17 31 18 31 41 31 42 Write enable delay time 2 tWED2 13 ns Figure 31 20 Write data delay time 1 tWDD1 13 ns Figures 31 13 to 31 20 31 41 to 31 44 Write data delay time 2 tWDD2 13 ns Figures 31 26 to 31 29 31 33 to 31 35 Write data delay time 3 tWDD3 1 2tcyc 13 ns Figure 31 39 Write data hold time 1 tWDH1 1 ns Figures 31 13 to 31 20 31 41 to 31 44 Write data hold time 2 tWDH2 1 ns Figures 31 2...

Page 1533: ...igure 31 17 Multiplexed address delay time tMAD 13 ns Figure 31 17 Multiplexed address hold time tMAH 1 ns Figure 31 17 DACK TEND delay time tDACD Refer to peripheral modules ns Figures 31 13 to 31 35 31 39 31 41 to 31 44 FRAME delay time tFMD 0 13 ns Figure 31 18 ICIORD delay time tICRSD 1 2tcyc 13 ns Figures 31 43 31 44 ICIOWR delay time tICWSD 1 2tcyc 13 ns Figures 31 43 31 44 Note 1 The maximu...

Page 1534: ...eform for DACKn and TENDn is when active low is specified Write T1 tAD1 tAS tCSD1 T2 tAD1 tRWD1 tRWD1 tCSD1 tRSD tRSD tAH tRDH1 tRDS1 tWED1 tWED1 tAH tBSD tBSD tDACD tDACD tWDH4 tWDD1 CKIO A25 to A0 CSn RD WR RD D31 to D0 WEn BS DACKn TENDn D31 to D0 tWDH1 Figure 31 13 Basic Bus Timing for Normal Space No Wait ...

Page 1535: ...WD1 tRWD1 tCSD1 tRSD tRSD tAH tRDS1 tWED1 tWED1 tAH tBSD tBSD tWTH tWTS tDACD tDACD tWDH1 tWDD1 CKIO A25 to A0 CSn RD WR RD D31 to D0 WEn BS WAIT DACKn TENDn D31 to D0 tRDH1 Read Note The waveform for DACKn and TENDn is when active low is specified Write Figure 31 14 Basic Bus Timing for Normal Space One Software Wait Cycle ...

Page 1536: ...tRWD1 tCSD1 tRSD tRSD tAH tRDS1 tWED1 tWED1 tAH tBSD tBSD tWTH tWTS tWTH tWTS tDACD tDACD tWDH1 tWDD1 CKIO A25 to A0 CSn RD WR RD D31 to D0 WEn BS WAIT DACKn TENDn D31 to D0 tRDH1 Read Note The waveform for DACKn and TENDn is when active low is specified Write Figure 31 15 Basic Bus Timing for Normal Space One External Wait Cycle ...

Page 1537: ...BSD tBSD tDACD tDACD tDACD tDACD tBSD tBSD tRWD1 tRWD1 tRWD1 tCSD1 tCSD1 tCSD1 tAS tAD1 tAD1 Tw T2 Taw T1 Tw T2 Taw DACKn TENDn A25 to A0 D15 to D0 CSn RD WR RD WAIT D15 to D0 WEn BS CKIO tWTH tWTS tWTH tWTS tRDH1 tRDH1 Read Note The waveform for DACKn and TENDn is when active low is specified Write Figure 31 16 Basic Bus Timing for Normal Space One Software Wait Cycle External Wait Cycle Valid WM...

Page 1538: ...Tw T2 tAD1 tCSD1 tAD1 tRWD1 tRWD1 tCSD1 tRSD tRSD tRDS1 tWED1 tWED1 Data Data tBSD tBSD tWTH tWTS tAHD tAHD tWTH tWTS tDACD tDACD Address tWDD1 tMAD CKIO A25 toA0 CS5 RD WR RD AH D15 to D0 WE1 WE0 BS WAIT DACKn D15 to D0 Address tMAH tMAD tAHD tDACD tDACD TENDn tMAH tWDH1 tWDH4 tRDH1 Figure 31 17 MPX I O Interface Bus Cycle Three Address Cycles One Software Wait Cycle One External Wait Cycle ...

Page 1539: ...s specified Write Tm1 tAD1 tCSD1 Tmd1w Tmd1 tAD1 tRWD1 tFMD tWDD1 tFMD tFMD tRWD1 tCSD1 CKIO A25 to A0 CS6 RD WR D31 to D0 D31 to D0 BS FRAME WAIT WEn RD DACKn tWDH1 tWDD1 tRDS2 tWDD1 tBSD tDACD tDACD tWTH tWTS TENDn tDACD tDACD tBSD tWDH1 tWDH1 tRDH2 Figure 31 18 Burst MPX I O Interface Bus Cycle Single Read Write One Address Cycle One Software Wait Cycle ...

Page 1540: ...te Th tAD1 tRSD tRSD tRDS1 tCSD1 tRWD1 T1 Twx T2 Tf tWDD1 tBSD tWDH1 tRDH1 tAD1 tCSD1 CKIO A25 to A0 CSn WEn RD D31 to D0 D31 to D0 RD WR RD WR BS WAIT DACKn TENDn tDACD tDACD tBSD tWTS tWTS tRWD1 tRWD1 tRWD1 tWED1 tWED1 tWTH tWTH Figure 31 19 Bus Cycle of SRAM with Byte Selection SW 1 Cycle HW 1 Cycle One Asynchronous External Wait Cycle BAS 0 Write Cycle UB LB Control ...

Page 1541: ...1 tRDH1 tAD1 tCSD1 CKIO A25 to A0 CSn WEn RD D31 to D0 D31 to D0 RD WR RD WR BS WAIT DACKn TENDn tDACD tDACD tBSD tWTS tWTS tWED2 tWED2 tRWD1 tWTH tWTH Read Note The waveform for DACKn and TENDn is when active low is specified Write Figure 31 20 Bus Cycle of SRAM with Byte Selection SW 1 Cycle HW 1 Cycle One Asynchronous External Wait Cycle BAS 1 Write Cycle WE Control ...

Page 1542: ...b T2B tAD2 tAD2 tCSD1 CKIO A25 to A0 CSn RD WR D31 to D0 WEn BS RD WAIT DACKn TENDn tAD1 tBSD tDACD tDACD tBSD tRWD1 tWTS tWTS tRWD1 tWTH tWTH tRDS3 tRDH3 tRDH3 Note The waveform for DACKn and TENDn is when active low is specified Figure 31 21 Burst ROM Read Cycle One Software Wait Cycle One Asynchronous External Burst Wait Cycle Two Burst ...

Page 1543: ... READA command Column address tCASD1 tCASD1 tBSD tBSD High tDQMD1 tDQMD1 tDACD tDACD Notes 1 An address pin to be connected to pin A10 of SDRAM 2 The waveform for DACKn and TENDn is when active low is specified CKIO A25 to A0 CSn RD WR A12 A11 1 D31 to D0 RASU L CASU L BS CKE DQMxx DACKn TENDn 2 Figure 31 22 Synchronous DRAM Single Read Bus Cycle Auto Precharge CAS Latency 2 WTRCD 0 Cycle WTRP 0 C...

Page 1544: ...s specified Trw Tr Tc1 Tcw Td1 Tde Tap tAD1 tAD1 tCSD1 tAD1 tRWD1 tRWD1 tCSD1 tAD1 tAD1 tAD1 tRDH2 tRDS2 CKIO A25 to A0 CSn RD WR A12 A11 1 D31 to D0 tRASD1 tRASD1 RASU L Row address READA command Column address tCASD1 tCASD1 CASU L tBSD tBSD High BS CKE tDQMD1 tDQMD1 DQMxx tDACD tDACD DACKn TENDn 2 Figure 31 23 Synchronous DRAM Single Read Bus Cycle Auto Precharge CAS Latency 2 WTRCD 1 Cycle WTRP...

Page 1545: ...c3 Tc4 Tde tAD1 tAD1 tCSD1 tAD1 tAD1 tAD1 tAD1 tRWD1 tRWD1 tCSD1 tAD1 tAD1 tAD1 tAD1 tRDH2 tRDS2 CKIO A25 to A0 CSn RD WR A12 A11 1 D31 to D0 tRASD1 tRASD1 RASU L Row address READA command READ command Column address 1 to 4 tCASD1 tCASD1 CASU L tBSD tBSD High BS CKE tDQMD1 tDQMD1 DQMxx tDACD tDACD DACKn TENDn 2 tRDH2 tRDS2 Figure 31 24 Synchronous DRAM Burst Read Bus Cycle Four Read Cycles Auto Pr...

Page 1546: ...2 A11 1 D31 to D0 tRASD1 tRASD1 RASU L Row address READ command Column address Notes 1 An address pin to be connected to pin A10 of SDRAM 2 The waveform for DACKn and TENDn is when active low is specified 1 to 4 tCASD1 tCASD1 CASU L tBSD tBSD High BS CKE tDQMD1 tDQMD1 DQMxx tDACD tDACD DACKn TENDn 2 tRDH2 tRDS2 READA command Figure 31 25 Synchronous DRAM Burst Read Bus Cycle Four Read Cycles Auto ...

Page 1547: ... when active low is specified Trwl Tr Tc1 tAD1 tCSD1 tAD1 tAD1 tRWD1 tRWD1 tRWD1 tCSD1 tAD1 tAD1 tAD1 CKIO A25 to A0 CSn RD WR A12 A11 1 D31 to D0 tRASD1 tRASD1 RASU L Row address WRITA command Column address tCASD1 tCASD1 CASU L tBSD tBSD High BS CKE tDQMD1 tDQMD1 DQMxx tDACD tDACD DACKn TENDn 2 tWDH2 tWDD2 Figure 31 26 Synchronous DRAM Single Write Bus Cycle Auto Precharge TRWL 1 Cycle ...

Page 1548: ...e low is specified Trw Tc1 Trwl Tr Trw tAD1 tCSD1 tAD1 tAD1 tRWD1 tRWD1 tRWD1 tCSD1 tAD1 tAD1 tAD1 CKIO A25 to A0 CSn RD WR A12 A11 1 D31 to D0 tRASD1 tRASD1 RASU L Row address WRITA command Column address tCASD1 tCASD1 CASU L tBSD tBSD High BS CKE tDQMD1 tDQMD1 DQMxx tDACD tDACD DACKn TENDn 2 tWDH2 tWDD2 Figure 31 27 Synchronous DRAM Single Write Bus Cycle Auto Precharge WTRCD 2 Cycles TRWL 1 Cyc...

Page 1549: ...wl Tr Tc1 tAD1 tCSD1 tAD1 tAD1 tAD1 tAD1 tAD1 tRWD1 tRWD1 tRWD1 tCSD1 tAD1 tAD1 tAD1 tAD1 CKIO A25 to A0 CSn RD WR A12 A11 1 D31 to D0 tRASD1 tRASD1 RASU L Row address WRITA command WRIT command Column address tCASD1 tCASD1 CASU L tBSD tBSD High BS CKE tDQMD1 tDQMD1 DQMxx tDACD tDACD DACKn TENDn 2 tWDH2 tWDD2 tWDH2 tWDD2 Figure 31 28 Synchronous DRAM Burst Write Bus Cycle Four Write Cycles Auto Pr...

Page 1550: ... Tr Tc1 Trw tAD1 tCSD1 tAD1 tAD1 tAD1 tAD1 tAD1 tRWD1 tRWD1 tRWD1 tCSD1 tAD1 tAD1 tAD1 tAD1 CKIO A25 to A0 CSn RD WR A12 A11 1 D31 to D0 tRASD1 tRASD1 RASU L Row address WRITA command WRIT command Column address tCASD1 tCASD1 CASU L tBSD tBSD High BS CKE tDQMD1 tDQMD1 DQMxx tDACD tDACD DACKn TENDn 2 tWDH2 tWDD2 tWDH2 tWDD2 Figure 31 29 Synchronous DRAM Burst Write Bus Cycle Four Write Cycles Auto ...

Page 1551: ... Td1 Td2 Td3 Td4 Tc1 tCSD1 tAD1 tAD1 tAD1 tAD1 tAD1 tAD1 tRWD1 tRWD1 tCSD1 tAD1 tAD1 tAD1 CKIO A25 to A0 CSn RD WR A12 A11 1 D31 to D0 tRASD1 tRASD1 RASU L Row address READ command Column address tCASD1 tCASD1 CASU L tBSD tBSD High BS CKE tDQMD1 tDQMD1 DQMxx tDACD tDACD DACKn TENDn 2 tRDH2 tRDS2 tRDH2 tRDS2 Figure 31 30 Synchronous DRAM Burst Read Bus Cycle Four Read Cycles Bank Active Mode ACT RE...

Page 1552: ... Tc4 Tde Tc1 Tc3 Td1 Td2 Td3 Td4 tCSD1 tAD1 tAD1 tAD1 tRWD1 tRWD1 tCSD1 tAD1 tAD1 CKIO A25 to A0 CSn RD WR A12 A11 1 D31 to D0 tRASD1 RASU L READ command Column address tCASD1 tCASD1 CASU L tBSD tBSD High BS CKE tDQMD1 tDQMD1 DQMxx tDACD tDACD DACKn TENDn 2 tRDH2 tRDS2 tRDH2 tRDS2 Figure 31 31 Synchronous DRAM Burst Read Bus Cycle Four Read Cycles Bank Active Mode READ Command Same Row Address CAS...

Page 1553: ...SD1 tAD1 tAD1 tAD1 tAD1 tAD1 tAD1 tRWD1 tRWD1 tRWD1 tCSD1 tAD1 tAD1 tAD1 tAD1 CKIO A25 to A0 CSn RD WR A12 A11 1 D31 to D0 tRASD1 tRASD1 tRASD1 tRASD1 RASU L READ command Column address Row address tCASD1 tCASD1 CASU L tBSD tBSD High BS CKE tDQMD1 tDQMD1 DQMxx tDACD tDACD DACKn TENDn 2 tRDH2 tRDS2 tRDH2 tRDS2 Figure 31 32 Synchronous DRAM Burst Read Bus Cycle Four Read Cycles Bank Active Mode PRE ...

Page 1554: ...Tr Tc1 tAD1 tCSD1 tAD1 tAD1 tAD1 tAD1 tAD1 tRWD1 tRWD1 tRWD1 tCSD1 tAD1 tAD1 tAD1 CKIO A25 to A0 CSn RD WR A12 A11 1 D31 to D0 tRASD1 tRASD1 RASU L Row address WRIT command Column address tCASD1 tCASD1 CASU L tBSD tBSD High BS CKE tDQMD1 tDQMD1 DQMxx tDACD tDACD DACKn TENDn 2 tWDH2 tWDD2 tWDH2 tWDD2 Figure 31 33 Synchronous DRAM Burst Write Bus Cycle Four Write Cycles Bank Active Mode ACT WRITE Co...

Page 1555: ...Tc3 Tc4 Tnop Tc1 tAD1 tCSD1 tAD1 tAD1 tAD1 tAD1 tRWD1 tRWD1 tRWD1 tCSD1 tAD1 tAD1 tAD1 CKIO A25 to A0 CSn RD WR A12 A11 1 D31 to D0 RASU L WRIT command Column address tCASD1 tCASD1 CASU L tBSD tBSD High BS CKE tDQMD1 tDQMD1 DQMxx tDACD tDACD DACKn TENDn 2 tWDH2 tWDD2 tWDH2 tWDD2 Figure 31 34 Synchronous DRAM Burst Write Bus Cycle Four Write Cycles Bank Active Mode WRITE Command Same Row Address WT...

Page 1556: ...tAD1 tAD1 tRWD1 tRWD1 tRWD1 tRWD1 tCSD1 tRASD1 tRASD1 tRASD1 tRASD1 tAD1 tAD1 tAD1 tAD1 CKIO A25 to A0 CSn RD WR A12 A11 1 D31 to D0 RASU L WRIT command Row address tAD1 tAD1 Column address tCASD1 tCASD1 CASU L tBSD tBSD High BS CKE tDQMD1 tDQMD1 DQMxx tDACD tDACD DACKn TENDn 2 tWDH2 tWDD2 tWDH2 tWDD2 Figure 31 35 Synchronous DRAM Burst Write Bus Cycle Four Write Cycles Bank Active Mode PRE ACT WR...

Page 1557: ...veform for DACKn and TENDn is when active low is specified Trc Trc Trr Tpw Tp Trc tCSD1 tAD1 tAD1 tRWD1 tRWD1 tRWD1 tCSD1 tCSD1 tCSD1 tRASD1 tRASD1 tRASD1 tRASD1 tAD1 tAD1 CKIO A25 to A0 CSn RD WR A12 A11 1 D31 to D0 RASU L tCASD1 tCASD1 CASU L High Hi Z BS CKE DQMxx DACKn TENDn 2 Figure 31 36 Synchronous DRAM Auto Refreshing Timing WTRP 1 Cycle WTRC 3 Cycles ...

Page 1558: ... waveform for DACKn and TENDn is when active low is specified Trc Trc Trc Trr Tpw Tp tCSD1 tAD1 tAD1 tRWD1 tRWD1 tRWD1 tCSD1 tCSD1 tCSD1 tRASD1 tRASD1 tRASD1 tRASD1 tAD1 tAD1 CKIO A25 to A0 CSn RD WR A12 A11 1 D31 to D0 RASU L tCASD1 tCASD1 CASU L Hi Z BS CKE DQMxx DACKn TENDn 2 tCKED1 tCKED1 Figure 31 37 Synchronous DRAM Self Refreshing Timing WTRP 1 Cycle ...

Page 1559: ...d Trc Trc Trc Tmw Tde Trr Trr Tpw Tp Trc tCSD1 tAD1 tAD1 tAD1 PALL REF REF MRS tRWD1 tRWD1 tRWD1 tCSD1 tCSD1 tCSD1 tRASD1 tRASD1 tRASD1 tRASD1 tAD1 tAD1 CKIO A25 to A0 CSn RD WR A12 A11 1 D31 to D0 RASU L tCASD1 tCASD1 CASU L Hi Z BS CKE DQMxx DACKn TENDn 2 tCSD1 tCSD1 tRASD1 tRASD1 tCASD1 tCASD1 tCSD1 tCSD1 tRWD1 tRWD1 tRASD1 tRASD1 tCASD1 tCASD1 Figure 31 38 Synchronous DRAM Mode Register Write ...

Page 1560: ...11 1 D31 to D0 RASU L CASU L BS CKE DQMxx DACKn TENDn tAD3 tAD3 tAD3 tAD3 2 Row address Column address Row address Column address tAD3 tAD3 tAD3 tAD3 tAD3 tAD3 tAD3 tCSD2 tRWD2 tRWD2 tRWD2 tCASD2 tCASD2 tCASD2 tCASD2 tCASD2 tRASD2 tRASD2 tRASD2 tRASD2 tBSD tBSD tBSD tBSD tDQMD2 tDQMD2 tDQMD2 tDQMD2 tRDS4 tRDH4 tWDD3 tWDH3 tCSD2 tCSD2 tCSD2 tDACD tDACD tDACD tDACD WRITA Command READA Command High H...

Page 1561: ...CKn and TENDn is when active low is specified Trc Trc Trc Trr Tpw Tp CKIO A25 to A0 CSn RD WR A12 A11 1 D31 to D0 RASU L CASU L Hi Z BS CKE DQMxx DACKn TENDn tAD3 tAD3 tCSD2 tCSD2 tCSD2 tCSD2 tCASD2 tDQMD2 tCASD2 tCASD2 tRASD2 tCKED2 tCKED2 tRASD2 tRASD2 tRWD2 tRWD2 tRASD2 tAD3 tAD3 2 Figure 31 40 Synchronous DRAM Self Refreshing Timing in Low Frequency Mode WTRP 2 Cycles ...

Page 1562: ...WR RD D15 to D0 WE D15 to D0 BS tAD1 tCSD1 tAD1 tCSD1 tRWD1 tWDH4 tBSD tDACD tBSD DACKn TENDn tDACD tRDH1 Tpcm1w Tpcm2 Tpcm1 Tpcm1w Tpcm1w tRSD tRDS1 tWED1 tRWD1 tWDD1 tRSD tWED1 tWDH1 Note The waveform for DACKn and TENDn is when active low is specified Figure 31 41 PCMCIA Memory Card Bus Cycle TED 0 Cycle TEH 0 Cycle No Wait ...

Page 1563: ...Write CKIO A25 to A0 CExx RD WR RD D15 to D0 WE D15 to D0 BS WAIT tWTS tAD1 tCSD1 tRWD1 tAD1 tCSD1 tRWD1 tBSD tBSD DACKn TENDn tDACD tDACD tWDH1 tWDD1 tWED1 tWED1 tRSD tRSD tRDH1 tRDS1 tWTH tWTH tWTS Tpcm1w Tpcm2 Tpcm0 Tpcm1 Tpcm1w Tpcm0w Tpcm2w Tpcm1w Tpcm1w Figure 31 42 PCMCIA Memory Card Bus Cycle TED 2 Cycles TEH 1 Cycle Software Wait Cycle 0 Hardware Wait Cycle 1 ...

Page 1564: ...NDn is when active low is specified Write CKIO A25 to A0 CExx RD WR ICIORD D15 to D0 ICIOWR D15 to D0 BS tAD1 tCSD1 tRWD1 tAD1 tCSD1 tRWD1 tWDD1 tWDH4 tBSD tDACD tBSD DACKn TENDn tDACD tICRSD tICWSD tICWSD tRDH1 Tpcm1w Tpcm2 Tpcm1 Tpcm1w Tpcm1w tRDS1 tICRSD tWDH1 Figure 31 43 PCMCIA I O Card Bus Cycle TED 0 Cycle TEH 0 Cycle No Wait ...

Page 1565: ...o A0 CExx RD WR ICIORD D15 to D0 ICIOWR D15 to D0 BS WAIT tWTS tAD1 tCSD1 tRWD1 tAD1 tCSD1 tRWD1 tBSD tBSD DACKn TENDn tDACD tDACD tWDH1 tWDD1 tICWSD tICWSD tICRSD tICRSD tRDH1 tRDS1 tWTH tWTH tWTS IOIS16 Tpcm1w Tpcm2 Tpcm0 Tpcm1 Tpcm1w Tpcm0w Tpcm2w Tpcm1w Tpcm1w tIO16H tIO16S Figure 31 44 PCMCIA I O Card Bus Cycle TED 2 Cycles TEH 1 Cycle Software Wait Cycle 0 Hardware Wait Cycle 1 ...

Page 1566: ...er Timing Conditions VCC PLLVCC USBDVCC 1 1 to 1 3 V PVCC USBDPVCC 3 0 to 3 6 V AVCC 3 0 to 3 6 V USBAVCC 1 1 to 1 3 V USBAPVCC 3 0 to 3 6 V VSS PLLVSS PVSS AVSS USBDVSS USBAVSS USBDPVSS USBAPVSS 0V Ta 20 to 85 C Item Symbol Min Max Unit Figure UBCTRG delay time tUBCTGD 14 ns Figure 31 45 CKIO UBCTRG tUBCTGD Figure 31 45 UBC Trigger Timing ...

Page 1567: ... 3 0 to 3 6 V USBAVCC 1 1 to 1 3 V USBAPVCC 3 0 to 3 6 V VSS PLLVSS PVSS AVSS USBDVSS USBAVSS USBDPVSS USBAPVSS 0 V Ta 20 to 85 C Item Symbol Min Max Unit Figure DREQ setup time tDRQS 15 DREQ hold time tDRQH 15 Figure 31 46 DACK TEND delay time tDACD 15 ns Figure 31 47 Note n 0 to 3 tDRQS tDRQH CKIO DREQn Figure 31 46 DREQ Input Timing Note n 0 1 m 0 to 3 CKIO TENDn DACKm t DACD t DACD Figure 31 4...

Page 1568: ...x Unit Figure Output compare output delay time tTOCD 100 ns Figure 31 48 Input capture input setup time tTICS tcyc 2 20 ns Timer input setup time tTCKS tcyc 20 ns Figure 31 49 Timer clock pulse width single edge tTCKWH L 1 5 tpcyc Timer clock pulse width both edges tTCKWH L 2 5 tpcyc Timer clock pulse width phase counting mode tTCKWH L 2 5 tpcyc Note tpcyc indicates peripheral clock Pφ cycle Outpu...

Page 1569: ...ble 31 12 Watchdog Timer Timing Conditions VCC PLLVCC USBDVCC 1 1 to 1 3 V PVCC USBDPVCC 3 0 to 3 6 V AVCC 3 0 to 3 6 V USBAVCC 1 1 to 1 3 V USBAPVCC 3 0 to 3 6 V VSS PLLVSS PVSS AVSS USBDVSS USBAVSS USBDPVSS USBAPVSS 0 V Ta 20 to 85 C Item Symbol Min Max Unit Figure WDTOVF delay time tWOVD 100 ns Figure 31 50 tWOVD tWOVD CKIO WDTOVF Figure 31 50 Watchdog Timer Timing ...

Page 1570: ...s tScyc 4 tpcyc Figure 31 51 Input clock rise time tSCKr 1 5 tpcyc Figure 31 51 Input clock fall time tSCKf 1 5 tpcyc Figure 31 51 Input clock width tSCKW 0 4 0 6 tScyc Figure 31 51 Transmit data delay time clocked synchronous tTXD 3 tpcyc 15 tpcyc Figure 31 52 Receive data setup time clocked synchronous tRXS 4 tpcyc 15 ns Figure 31 52 Receive data hold time clocked synchronous tRXH 100 ns Figure ...

Page 1571: ... Master 60 Clock high pulse width Slave tHI 60 ns Master 60 Clock low pulse width Slave tLO 60 ns Clock rise time tRISE 20 ns Clock fall time tFALL 20 ns Master 25 Data input setup time Slave tSU 30 ns Master 10 Data input hold time Slave tH 10 ns Master 1 5 SCS setup time Slave tLEAD 1 5 tpcyc Master 1 5 SCS hold time Slave tLAG 1 5 tpcyc Master 40 Data output delay time Slave tOD 40 ns Master 30...

Page 1572: ...tput SSCK output CPOS 1 SSO output SSI input tLEAD tSU tH tOD tFALL tRISE tSUcyc tLAG tOH tLO tHI tHI tLO tTD Figure 31 53 SSU Timing Master CPHS 1 SSCK output CPOS 0 SCS output SSCK output CPOS 1 SSO output SSI input tLEAD tSU tH tOD tFALL tRISE tSUcyc tLAG tOH tLO tHI tHI tLO tTD Figure 31 54 SSU Timing Master CPHS 0 ...

Page 1573: ...CK input CPOS 1 SSO input SSI output tLEAD tFALL tRISE tSUcyc tLAG tTD tREL tOH tOD tSU tSA tLO tHI tHI tLO tH Figure 31 55 SSU Timing Slave CPHS 1 SSCK input CPOS 0 SCS input SSCK input CPOS 1 SSO input SSI output tLEAD tFALL tRISE tSUcyc tLAG tTD tREL tOH tOD tSU tSA tLO tHI tHI tLO tH Figure 31 56 SSU Timing Slave CPHS 0 ...

Page 1574: ...h pulse width tSCLH 3 tpcyc 1 300 ns SCL input low pulse width tSCLL 5 tpcyc 1 300 ns SCL SDA input rise time tSr 300 ns SCL SDA input fall time tSf 300 ns SCL SDA input spike pulse removal time 2 tSP 1 2 tpcyc 1 SDA input bus free time tBUF 5 tpcyc 1 Start condition input hold time tSTAH 3 tpcyc 1 Retransmit start condition input setup time tSTAS 3 tpcyc 1 Stop condition input setup time tSTOS 3 ...

Page 1575: ...6 Page 1545 of 1588 REJ09B0313 0050 Legend S Start condition P Stop condition Sr Start condition for retransmission SCL VIH VIL tSTAH tBUF P S tSf tSr tSCL tSDAH tSCLH tSCLL SDA Sr tSTAS tSP tSTOS tSDAS P Figure 31 57 I 2 C Bus Interface 3 Input Output Timing ...

Page 1576: ...APVSS 0 V Ta 20 to 85 C Item Symbol Min Typ Max Unit Remarks Figure Output clock cycle tO 160 3364 ns Output Input clock cycle tI 80 3364 ns Input Clock high tHC 40 ns Clock low tLC 40 ns Bidirectional Clock rise time tRC 20 ns Output 100 pF Figure 31 58 Delay tDTR 50 ns Transmit Figures 31 59 31 60 Setup time tSR 15 ns Receive Figures 31 61 31 62 Hold time tHTR 5 ns Receive transmit Figures 31 59...

Page 1577: ...9B0313 0050 tDTR tHTR SSISCKn SSIWSn SSIDATAn Figure 31 59 SSI Transmit Timing 1 tDTR tHTR SSISCKn SSIWSn SSIDATAn Figure 31 60 SSI Transmit Timing 2 tSR tHTR SSISCKn SSIWSn SSIDATAn Figure 31 61 SSI Receive Timing 1 tSR tHTR SSISCKn SSIWSn SSIDATAn Figure 31 62 SSI Receive Timing 2 ...

Page 1578: ...C USBDVCC 1 1 to 1 3 V PVCC USBDPVCC 3 0 to 3 6 V AVCC 3 0 to 3 6 V USBAVCC 1 1 to 1 3 V USBAPVCC 3 0 to 3 6 V VSS PLLVSS PVSS AVSS USBDVSS USBAVSS USBDPVSS USBAPVSS 0 V Ta 20 to 85 C Item Symbol Min Max Unit Figure Transmit data delay time tCTXD 100 ns Receive data setup time tCRXS 100 Receive data hold time tCRXH 100 Figure 31 64 tCRXS CKIO CRx receive data CTx transmit data tCRXH tCTXD Figure 3...

Page 1579: ...C USBDPVCC 3 0 to 3 6 V AVCC 3 0 to 3 6 V USBAVCC 1 1 to 1 3 V USBAPVCC 3 0 to 3 6 V VSS PLLVSS PVSS AVSS USBDVSS USBAVSS USBDPVSS USBAPVSS 0V Ta 20 to 85 C Module Item Symbol Min Max Unit Figure B P clock ratio 1 1 17 B P clock ratio 2 1 tcyc 17 A D converter Trigger input setup time B P clock ratio 4 1 tTRGS 3 tcyc 17 ns Figure 31 65 CKIO ADTRG tTRGS Figure 31 65 A D Converter External Trigger I...

Page 1580: ...put setup time 2 tADOS2 0 5 tfcyc 10 ns Data output hold time 2 tADOH2 0 5 tfcyc 10 ns Figure 31 69 FWE cycle time tACWC 2 tfcyc 5 ns Figure 31 67 FWE low pulse width tAWP tfcyc 5 ns Figures 31 66 31 67 31 70 FWE high pulse width tAWPH tfcyc 5 ns Command to address transition time tACAS 4 tfcyc ns Figure 31 67 Address to data read transition time tAADDR 32 tpcyc ns Address to ready busy transition...

Page 1581: ...ns Figure 31 69 FSC to FOE hold time tASOH 2 tfcyc 10 ns Figure 31 68 Note tfcyc indicates the period of one cycle of the FLCTL clock tpcyc indicates the period of one cycle of the peripheral clock Pφ Set so as tfcyc tpcyc tADOS tACDS tAWP tACDH tADOH Command Low Low High High FCE FCDE FOE FWE FSC NAF7 to NAF0 FRB Figure 31 66 AND Type Flash Memory Command Issuance Timing ...

Page 1582: ...ADOH tADOH tACAS Address Address Low Low High High FCE FCDE FOE FWE FSC NAF7 to NAF0 FRB Figure 31 67 AND Type Flash Memory Address Issuance Timing tASP tAADDR tAADRB tARBDR tADRS tASPL tARDS tARDH tASPL tASOH tASP tASCC Data Low High FCE FCDE FOE FWE FSC NAF7 to NAF0 FRB Data Figure 31 68 AND Type Flash Memory Data Read Timing ...

Page 1583: ...2 tADOS2 tADOS2 tADOH2 tADOH2 tASPL tASP tASP tASPL tASCC Low FCE FCDE FOE FWE FSC NAF7 to NAF0 FRB High High Data Data Data Figure 31 69 AND Type Flash Memory Data Write Timing tADOS tACDS tAWP tACDH tADOH Command Low Low High FCE FCDE FOE FWE FSC NAF7 to NAF0 FRB tARDS tARDH Status Figure 31 70 AND Type Flash Memory Status Read Timing ...

Page 1584: ...ransition time 1 tNCDAD1 1 5 tfcyc 10 ns Figures 31 71 31 72 Command to address transition time 2 tNCDAD2 2 tfcyc 10 ns Figure 31 72 FWE cycle time tNWC tfcyc 5 ns Figures 31 72 31 74 FWE low pulse width tNWP 0 5 tfcyc 5 ns Figures 31 71 31 72 31 74 31 75 FWE high pulse width tNWH 0 5 tfcyc 5 ns Figures 31 72 31 74 Address to ready busy transition time tNADRB 32 tpcyc ns Figures 31 72 31 73 Ready ...

Page 1585: ...us read transition time tNCDFSR 3 5 tfcyc ns Status read setup time tNSTS 2 5 tfcyc ns Figure 31 75 Note tfcyc indicates the period of one cycle of the FLCTL clock tpcyc indicates the period of one cycle of the peripheral clock Pφ Set so as tfcyc tpcyc tNDOS tNCDS tNWP tNCDH tNCDAD1 tNDOH Command Low High High FCE FCDE FOE FWE FSC NAF7 to NAF0 FRB Figure 31 71 NAND Type Flash Memory Command Issuan...

Page 1586: ...H tNDOS tNDOH tNWC tNCDAD2 Address Low High High FCE FCDE FOE FWE FSC NAF7 to NAF0 FRB Address Address Figure 31 72 NAND Type Flash Memory Address Issuance Timing tNSP tNRBDR2 tNADRB tNRBDR1 tNSPH tNRDS tNRDH tNSP tNSP tNSCC Data tNRDS tNRDS tNRDH Low Low FCE FCDE FOE FWE FSC NAF7 to NAF0 FRB High Data Figure 31 73 NAND Type Flash Memory Data Read Timing ...

Page 1587: ... tNWC Data tNDOS tNDOS tNDOH Low Low FCE FCDE FOE FWE FSC NAF7 to NAF0 FRB High High Data Figure 31 74 NAND Type Flash Memory Data Write Timing tNDOS tNCDS tNWP tNCDH tNSTS tNCDFSR tNDOH Command Low High FCE FCDE FOE FWE FSC NAF7 to NAF0 FRB Low tNRDS tNSP tNCDSR tNRDH Status Figure 31 75 NAND Type Flash Memory Status Read Timing ...

Page 1588: ...SS AVSS USBDVSS USBAVSS USBDPVSS USBAPVSS 0 V Ta 20 to 85 C Item Symbol Min Typ Max Unit Figure Rise time tFR 4 20 ns Fall time tFF 4 20 ns Rise fall time lag tFR tFF 90 111 11 Figure 31 76 Output driver resistance ZDRV 28 44 Ω DP DM tFR tFF 10 10 90 90 Figure 31 76 DP and DM Output Timing Full Speed Measurement circuit USBDPVCC DP DM USBDPVSS CL 50 pF CL 50 pF The electric capacitance CL includes...

Page 1589: ...SBAVCC 1 1 to 1 3 V USBAPVCC 3 0 to 3 6 V VSS PLLVSS PVSS AVSS USBDVSS USBAVSS USBDPVSS USBAPVSS 0 V Ta 20 to 85 C Item Symbol Min Typ Max Unit Figure Rise time tHSR 500 ps Fall time tHSF 500 ps Figure 31 78 Output driver resistance ZHSDRV 40 5 49 5 Ω DP DM tHSR tHSF 10 10 90 90 Figure 31 78 DP and DM Output Timing High Speed Measurement circuit USBDPVCC DP DM USBDPVSS RL 45Ω RL 45Ω Figure 31 79 M...

Page 1590: ...l Min Max Unit Figure LCD_CLK input clock frequency tFREQ 66 MHz LCD_CLK input clock rise time tr 3 ns LCD_CLK input clock fall time tf 3 ns LCD_CLK input clock duty tDUTY 90 110 Clock LCD_CL2 cycle time tCC 25 ns Clock LCD_CL2 high pulse width tCHW 7 ns Clock LCD_CL2 low pulse width tCLW 7 ns Clock LCD_CL2 transition time rise fall tCT 3 ns Data LCD_DATA delay time tDD 3 5 3 ns Display enable LCD...

Page 1591: ...ge 1561 of 1588 REJ09B0313 0050 tDD tDT tCHW tCLW tCT tCT tCC 0 8Vcc 0 2Vcc tDT LCD_DATA0 to LCD_DATA15 LCD_CL2 LCD_M_DISP LCD_CL1 LCD_FLM tID tIT 0 8Vcc 0 2Vcc tIT tHD tHT 0 8Vcc 0 2Vcc tHT tVT tVD 0 8Vcc 0 2Vcc 0 8Vcc tVT 0 2Vcc Figure 31 80 LCDC Module Timing ...

Page 1592: ... V PVCC USBDPVCC 3 0 to 3 6 V AVCC 3 0 to 3 6 V USBAVCC 1 1 to 1 3 V USBAPVCC 3 0 to 3 6 V VSS PLLVSS PVSS AVSS USBDVSS USBAVSS USBDPVSS USBAPVSS 0 V Ta 20 to 85 C Item Symbol Min Max Unit Figure Output data delay time tPORTD 100 ns Figure 31 81 Input data setup time tPORTS 100 Input data hold time tPORTH 100 tPORTS CKIO Port read Port write tPORTH tPORTD Figure 31 81 I O Port Timing ...

Page 1593: ...AVSS USBDVSS USBAVSS USBDPVSS USBAPVSS 0 V Ta 20 to 85 C Item Symbol Min Max Unit Figure TCK cycle time tTCKcyc 50 ns Figure 31 82 TCK high pulse width tTCKH 0 4 0 6 tTCKcyc TCK low pulse width tTCKL 0 4 0 6 tTCKcyc TDI setup time tTDIS 10 ns Figure 31 83 TDI hold time tTDIH 10 ns TMS setup time tTMSS 10 ns TMS hold time tTMSH 10 ns TDO delay time tTDOD 16 ns Note Should be greater than the periph...

Page 1594: ...acteristics Rev 0 50 May 18 2006 Page 1564 of 1588 REJ09B0313 0050 TCK TMS TDI TDO tTDIS tTDIH tTCKcyc tTMSS tTMSH tTDOD tTDOD TDO change timing after switch command setting Initial value Figure 31 83 H UDI Data Transfer Timing ...

Page 1595: ...to 3 0 V where RES MRES NMI MD MD_CLK1 MD_CLK0 ASEMD TRST and Schmitt trigger input pins are within PVSS to PVCC Input rise and fall times 1 ns IOL IOH CL VREF LSI output pin DUT output Notes CL is the total value that includes the capacitance of measurement tools Each pin is set as follows 30 pF CKIO RASU RASL CASU CASL CS0 to CS7 and BACK 50 pF All other pins IOL and IOH are shown in table 31 3 ...

Page 1596: ...o 1 3 V PVCC USBDPVCC 3 0 to 3 6 V AVCC 3 0 to 3 6 V USBAVCC 1 1 to 1 3 V USBAPVCC 3 0 to 3 6 V VSS PLLVSS PVSS AVSS USBDVSS USBAVSS USBDPVSS USBAPVSS 0 V Ta 20 to 85 C Item Min Typ Max Unit Resolution 10 10 10 bits Conversion time 3 9 µs Analog input capacitance 20 pF Permissible signal source impedance 5 kΩ Nonlinearity error 3 0 LSB Offset error 2 0 LSB Full scale error 2 0 LSB Quantization err...

Page 1597: ...r Characteristics Conditions VCC PLLVCC USBDVCC 1 1 to 1 3 V PVCC USBDPVCC 3 0 to 3 6 V AVCC 3 0 to 3 6 V USBAVCC 1 1 to 1 3 V USBAPVCC 3 0 to 3 6 V VSS PLLVSS PVSS AVSS USBDVSS USBAVSS USBDPVSS USBAPVSS 0 V Ta 20 to 85 C Item Min Typ Max Unit Test Conditions Resolution 8 8 8 bits Conversion time 10 µs Load capacitance 20 pF 2 0 3 0 LSB Load resistance 2 MΩ Absolute accuracy 2 5 LSB Load resistanc...

Page 1598: ...Section 31 Electrical Characteristics Rev 0 50 May 18 2006 Page 1568 of 1588 REJ09B0313 0050 ...

Page 1599: ...k operation mode 2 3 Z 8 Z Z Z Z Z XTAL 2 O 8 O L L O O 0 1 3 O 9 O O Z 3 O Z 3 O O Z 3 Clock CKIO Clock operation mode 2 I 8 I Z I I I RES I 8 I I I I I MRES I I I I I WDTOVF H O H H O O BREQ I Z Z I I System control BACK O Z Z O L MD I 8 I I I I I MD_CLK1 MD_CLK0 I 8 I I I I I Operation mode control ASEMD I 8 I I I I I NMI I 8 I I I I I IRQ7 to IRQ0 PE11 to PE4 I I I I I IRQ7 to IRQ0 PB7 to PB0 ...

Page 1600: ...6 D31 to D16 Area 0 data bus width 32 Z I O Z Z I O Z Data bus D15 to D0 Z I O Z Z I O Z CS0 H 9 O H Z 5 H Z 5 O Z CS7 to CS1 CE1A CE1B CE2A CE2B O H Z 5 H Z 5 O Z RD H 9 O H Z 5 H Z 5 O Z RD WR O H Z 5 H Z 5 O Z BS O H Z 5 H Z 5 O Z FRAME O H Z 5 H Z 5 O Z WAIT I Z Z I Z WE3 DQMUU ICIOWR AH WE2 DQMUL ICIORD WE1 DQMLU WE WE0 DQMLL O H Z 5 H Z 5 O Z RASU RASL CASU CASL O O Z 6 O Z 6 O O Z 6 CKE O O...

Page 1601: ... I O K Z 4 K Z 4 I O I O RTC_X1 2 I 8 I Z 10 I I Z 10 I Z 10 I Z 10 RTC RTC_X2 2 O 8 O H 10 O O H 10 O H 10 O H 10 TxD3 to TxD0 O Z O Z 4 O Z 4 O Z O Z RxD3 to RxD0 I Z Z I I SCK3 to SCK0 I O K Z 4 K Z 4 I O I O RTS3 I O K Z 4 K Z 4 I O I O SCIF CTS3 I O K Z 4 K Z 4 I O I O SSO1 SSO0 I O K Z 4 K Z 4 I O I O SSI1 SSI0 I O K Z 4 K Z 4 I O I O SSCK1 SSCK0 I O K Z 4 K Z 4 I O I O SSU SCS1 SCS0 I O K Z...

Page 1602: ... I DAC DA1 DA0 8 O Z O O O FOE O O Z 4 O Z 4 O O FSC O O Z 4 O Z 4 O O FCE O O Z 4 O Z 4 O O FCDE O O Z 4 O Z 4 O O FRB I Z Z I I FWE O O Z 4 O Z 4 O O FLCTL NAF7 to NAF0 I O K Z 4 K Z 4 I O I O DP DM I O 8 I O I O I O I O I O VBUS I 8 I I I I I REFIN I 8 I I I I I USB_X1 1 I 8 I I I I I USB USB_X0 2 O 8 O O O O O LCD_DATA15 to LCD_DATA0 O O Z 4 O Z 4 O O LCD_DON O O Z 4 O Z 4 O O LCD_CL1 LCD_CL2 ...

Page 1603: ...I O 16 9 PC1 Area 0 data bus width 32 Z I O K Z 4 K Z 4 I O I O 16 Z PD15 to PD0 Area 0 data bus width 32 I O K Z 4 K Z 4 I O I O PE15 to PE0 Z I O K Z 4 K Z 4 I O I O I O port PF30 to PF0 Z I O K Z 4 K Z 4 I O I O TRST I 8 I I I I I TCK I 8 I I I I I TDI I 8 I I I I I TDO O Z 7 8 O Z 7 O Z 7 O Z 7 O Z 7 O Z 7 H UDI TMS I 8 I I I I I AUDSYNC O O O O O AUDCK O O O O O AUDATA3 to AUDATA0 O O O O O E...

Page 1604: ...epends on the setting of the HIZ bit in the standby control register 3 STBCR3 see section 28 Power Down Modes 5 Depends on the setting of the HIZMEM bit in the common control register CMNCR of the BSC see section 9 Bus State Controller BSC 6 Depends on the setting of the HIZCNT bit in the common control register CMNCR of the BSC see section 9 Bus State Controller BSC 7 Z when the TAP controller of...

Page 1605: ...0 0 15 3 95 Max 0 15 0 04 61 60 181 180 120 121 32 34 6 0 2 34 6 0 2 0 to 8 0 5 0 2 UNIT mm 0 10 1 25 1 3 0 22 0 05 0 20 0 04 0 5 0 10 M Package code EIAJ code JEDEC code Mass g Dimension including the plating thickness Base material dimension FP 240 FP 240V Conforms to EDR 7311 7 0 g Figure B 1 Package Dimensions ...

Page 1606: ...Appendix Rev 0 50 May 18 2006 Page 1576 of 1588 REJ09B0313 0050 ...

Page 1607: ...ess spaces of on chip RAM for data retention 1357 Address array write associative operation 209 Address array write non associative operation 208 Addressing modes 34 Analog input pin ratings 1015 AND NAND flash memory controller FLCTL 1025 Arithmetic operation instructions 53 Auto refreshing 325 Auto request mode 402 B Bank active 318 Banked register and input output of banks 163 BCHG interrupt 11...

Page 1608: ...en word write and count up processes of CMCNT 649 Conflict between write and compare match processes of CMCNT 648 Conflict error 797 Control signal timing 1498 Control transfer stage transition interrupt 1154 Control transfers when the function controller function is selected 1180 Control transfers when the host controller function is selected 1179 Controller area network RCAN TL1 885 CPU 23 Cryst...

Page 1609: ...ting point exceptions 79 Floating point format 70 Floating point operation instructions 61 Floating point ranges 72 Floating point registers 75 Floating point unit FPU 69 Flow of the user break operation 185 Format of double precision floating point number 70 Format of single precision foating point number 70 FPU exception handling 79 FPU exception sources 79 FPU related CPU instructions 63 Frame ...

Page 1610: ...ive operation 829 Master transmit operation 827 Memory mapped cache 208 Message control field 897 Message data fields 902 Message receive sequence 980 Message transmission request 966 975 Micro processor interface MPI 888 Module standby function 1397 Module standby mode setting 806 MPX I O interface 290 MTU2 functions 424 MTU2 interrupts 575 MTU2 module timing 1538 MTU2 output pin initialization 6...

Page 1611: ...wn modes 1361 Power down state 67 Power on reset 106 Power on sequence 332 Power supply control sequences 1245 Prefetch operation only for operand cache 204 Procedure register PR 26 Processing of analog input pins 1014 Program counter PC 26 Program execution state 67 PWM Modes 516 Q Quantization error 1012 R RCAN TL1 control registers 909 RCAN TL1 interrupt sources 984 RCAN TL1 mailbox registers 9...

Page 1612: ...47 CS5WCR 239 255 CS6WCR 243 255 259 CS7WCR 232 CSnBCR n 0 to 7 224 CYCTR 954 D0FBCFG 1084 D0FIFO 1085 D0FIFOCTR 1090 D0FIFOSEL 1086 D0FIFOTRN 1093 D1FBCFG 1084 D1FIFO 1085 D1FIFOCTR 1090 D1FIFOSEL 1086 D1FIFOTRN 1093 DACR 1020 DADR0 1019 DADR1 1019 DAR 380 DCPCFG 1122 DCPCTR 1125 DCPMAXP 1124 DMAOR 393 DMARS0 to DMARS3 397 DMATCR 380 DSCTR 1380 DSCTR2 1382 DSFR 1385 DSSSR 1383 DVSTCTR 1079 FLADR ...

Page 1613: ...12 LDLIRNR 1232 LDMTR 1203 LDPALCR 1213 LDPMMR 1224 LDPR 1214 LDPSPR 1226 LDSARL 1211 LDSARU 1210 LDSMR 1208 LDUINTLNR 1231 LDUINTR 1229 LDVDLNR 1217 LDVSYNR 1219 LDVTLNR 1218 MBIMR0 943 MBIMR1 942 MCR 909 NF2CYC 825 NRDYENB 1100 NRDYSTS 1111 PADRL 1330 PBCRL1 1277 PBCRL2 1276 PBCRL3 1274 PBCRL4 1274 PBDRL 1333 PBIORL 1273 PBPRL 1335 PCCRL1 1283 PCCRL2 1282 PCCRL3 1280 PCCRL4 1279 PCDRL 1337 PCIOR...

Page 1614: ... RDAYAR 683 RDAYCNT 676 RDMATCR 392 REC 929 RFMK 955 RFPR0 941 RFPR1 941 RFTROFF 950 RHRAR 681 RHRCNT 674 RMINAR 680 RMINCNT 673 RMONAR 684 RMONCNT 677 RSAR 390 RSECAR 679 RSECCNT 672 RTCNT 270 RTCOR 271 RTCSR 268 RWKAR 682 RWKCNT 675 RXPR0 940 RXPR1 939 RYRAR 685 RYRCNT 678 SAR DMAC 379 SAR IIC3 823 SCBRR 720 SCEMR 738 SCFCR 730 SCFDR 733 SCFRDR 703 SCFSR 712 SCFTDR 704 SCLSR 737 SCRSR 703 SCSCR ...

Page 1615: ...ER 496 TEC 929 TESTMODE 1082 TGCR 487 TGR 474 TICCR 467 TIER 458 TIOR 440 TITCNT 493 TITCR 491 TMDR 437 TOCR1 480 TOCR2 483 TOER 479 TOLBR 486 TRWER 478 TSR 461 951 TSTR 475 TSYCR 468 TSYR 476 TTCR0 945 TTTSEL 957 TWCR 497 TXACK0 937 TXACK1 936 TXCR0 936 TXCR1 935 TXPR0 934 TXPR1 933 UFRMNUM 1117 UMSR0 944 UMSR1 943 USBADDR 1118 USBINDX 1120 USBLENG 1121 USBREQ 1119 USBVAL 1120 WRCSR 657 WTCNT 654...

Page 1616: ...he display resolution 1245 Shift instructions 57 Sign extension of word data 30 SIGN interrupt 1158 Single address mode 413 Single mode 1000 Single read 314 Single write 317 Slave receive operation 834 Slave transmit operation 831 Sleep mode 962 1387 Slot illegal instructions 116 SOF interpolation function 1192 Software standby mode 1388 SRAM interface with byte selection 340 SSI module timing 154...

Page 1617: ... module USB 1069 USB data bus resistor control 1139 USB transceiver timing 1558 User break controller UBC 171 User break interrupt 139 User debugging interface H UDI 1399 Using alarm function 693 Using interval timer mode 663 Using watchdog timer mode 661 V VBUS interrupt 1157 Vector base register VBR 25 W Wait between access cycles 358 Watchdog timer WDT 651 Watchdog timer timing 1539 Write back ...

Page 1618: ...Rev 0 50 May 18 2006 Page 1588 of 1588 REJ09B0313 0050 ...

Page 1619: ...Publication Date Rev 0 50 May 18 2006 Published by Sales Strategic Planning Div Renesas Technology Corp Edited by Customer Support Department Global Strategic Communication Div Renesas Solutions Corp 2006 Renesas Technology Corp All rights reserved Printed in Japan ...

Page 1620: ...8 Renesas Technology Hong Kong Ltd 7th Floor North Tower World Finance Centre Harbour City 1 Canton Road Tsimshatsui Kowloon Hong Kong Tel 852 2265 6688 Fax 852 2730 6071 Renesas Technology Taiwan Co Ltd 10th Floor No 99 Fushing North Road Taipei Taiwan Tel 886 2 2715 2888 Fax 886 2 2713 2999 Renesas Technology Singapore Pte Ltd 1 Harbour Front Avenue 06 10 Keppel Bay Tower Singapore 098632 Tel 65...

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Page 1622: ...SH7203 Group Hardware Manual ...

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