Section 16 Synchronous Serial Communication Unit (SSU)
Rev. 0.50 May 18, 2006 Page 780 of 1588
REJ09B0313-0050
Bit Bit
Name
Initial
Value
R/W Description
3
SCSATS
0
R/W
Selects the assertion timing of the
SCS
pin (valid in
SSU and master mode).
0: Min. values of t
LEAD
and t
LAG
are 1/2
×
t
SUcyc
1: Min. values of t
LEAD
and t
LAG
are 3/2
×
t
SUcyc
2 SSODTS
0 R/W
Selects the data output timing of the SSO pin (valid in
SSU and master mode)
0: While BIDE = 0, MSS = 1, and TE = 1 or while BIDE
= 1, TE = 1, and RE = 0, the SSO pin outputs data
1: While BIDE = 0, MSS = 1, and TE = 1 or while BIDE
= 1, TE = 1, and RE = 0, the SSO pin outputs data
while the
SCS
pin is driven low
1, 0
All
0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
16.3.7
SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3)
SSTDR is an 8-bit register that stores transmit data. When 8-bit data length is selected by bits
DATS1 and DATS0 in SSCRL, SSTDR0 is valid. When 16-bit data length is selected, SSTDR0
and SSTDR1 are valid. When 32-bit data length is selected, SSTDR0 to SSTDR3 are valid. The
SSTDR that has not been enabled must not be accessed.
When the SSU detects that SSTRSR is empty, it transfers the transmit data written in SSTDR to
SSTRSR and starts serial transmission. If the next transmit data has already been written to
SSTDR during serial transmission, the SSU performs consecutive serial transmission.
Although SSTDR can always be read from or written to by the CPU and DTC, to achieve reliable
serial transmission, write transmit data to SSTDR after confirming that the TDRE bit in SSSR is
set to 1.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit Bit
Name
Initial
Value R/W Description
7 to 0
All 0
R/W
Serial transmit data
Summary of Contents for Single-Chip Microcomputer SH7203
Page 2: ...Rev 0 50 May 18 2006 Page ii of xxx ...
Page 30: ...Rev 0 50 May 18 2006 Page xxx of xxx ...
Page 52: ...Section 1 Overview Rev 0 50 May 18 2006 Page 22 of 1588 REJ09B0313 0050 ...
Page 98: ...Section 2 CPU Rev 0 50 May 18 2006 Page 68 of 1588 REJ09B0313 0050 ...
Page 128: ...Section 4 Clock Pulse Generator CPG Rev 0 50 May 18 2006 Page 98 of 1588 REJ09B0313 0050 ...
Page 200: ...Section 6 Interrupt Controller INTC Rev 0 50 May 18 2006 Page 170 of 1588 REJ09B0313 0050 ...
Page 242: ...Section 8 Cache Rev 0 50 May 18 2006 Page 212 of 1588 REJ09B0313 0050 ...
Page 400: ...Section 9 Bus State Controller BSC Rev 0 50 May 18 2006 Page 370 of 1588 REJ09B0313 0050 ...
Page 696: ...Section 13 Watchdog Timer WDT Rev 0 50 May 18 2006 Page 666 of 1588 REJ09B0313 0050 ...
Page 726: ...Section 14 Realtime Clock RTC Rev 0 50 May 18 2006 Page 696 of 1588 REJ09B0313 0050 ...
Page 876: ...Section 17 I2 C Bus Interface 3 IIC3 Rev 0 50 May 18 2006 Page 846 of 1588 REJ09B0313 0050 ...
Page 1054: ...Section 21 D A Converter DAC Rev 0 50 May 18 2006 Page 1024 of 1588 REJ09B0313 0050 ...
Page 1294: ...Section 24 LCD Controller LCDC Rev 0 50 May 18 2006 Page 1264 of 1588 REJ09B0313 0050 ...
Page 1386: ...Section 26 I O Ports Rev 0 50 May 18 2006 Page 1356 of 1588 REJ09B0313 0050 ...
Page 1512: ...Section 30 List of Registers Rev 0 50 May 18 2006 Page 1482 of 1588 REJ09B0313 0050 ...
Page 1598: ...Section 31 Electrical Characteristics Rev 0 50 May 18 2006 Page 1568 of 1588 REJ09B0313 0050 ...
Page 1606: ...Appendix Rev 0 50 May 18 2006 Page 1576 of 1588 REJ09B0313 0050 ...
Page 1618: ...Rev 0 50 May 18 2006 Page 1588 of 1588 REJ09B0313 0050 ...
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Page 1622: ...SH7203 Group Hardware Manual ...