Section 15 Serial Communication Interface with FIFO (SCIF)
Rev. 0.50 May 18, 2006 Page 712 of 1588
REJ09B0313-0050
15.3.7
Serial Status Register (SCFSR)
SCFSR is a 16-bit register. The upper 8 bits indicate the number of receive errors in the receive
FIFO data register, and the lower 8 bits indicate the status flag indicating SCIF operating state.
The CPU can always read and write to SCFSR, but cannot write 1 to the status flags (ER, TEND,
TDFE, BRK, RDF, and DR). These flags can be cleared to 0 only if they have first been read
(after being set to 1). The PER flag (bits 15 to 12 and bit 2) and the FER flag (bits 11 to 8 and bit
3) are read-only bits that cannot be written.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
R
R
R
R
R
R
R
R
R/(W)
*
R/(W)
*
R/(W)
*
R/(W)
*
R
R
R/(W)
*
R/(W)
*
Bit:
Initial value:
R/W:
Note:
Only 0 can be written to clear the flag after 1 is read.
*
PER[3:0]
FER[3:0]
ER
TEND
TDFE
BRK
FER
PER
RDF
DR
Bit Bit
Name
Initial
Value
R/W Description
15 to 12 PER[3:0]
0000
R
Number of Parity Errors
Indicate the quantity of data including a parity error in
the receive data stored in the receive FIFO data
register (SCFRDR). The value indicated by bits 15 to
12 after the ER bit in SCFSR is set, represents the
number of parity errors in SCFRDR. When parity
errors have occurred in all 16-byte receive data in
SCFRDR, PER[3:0] shows 0000.
11 to 8
FER[3:0]
0000
R
Number of Framing Errors
Indicate the quantity of data including a framing error
in the receive data stored in SCFRDR. The value
indicated by bits 11 to 8 after the ER bit in SCFSR is
set, represents the number of framing errors in
SCFRDR. When framing errors have occurred in all
16-byte receive data in SCFRDR, FER[3:0] shows
0000.
Summary of Contents for Single-Chip Microcomputer SH7203
Page 2: ...Rev 0 50 May 18 2006 Page ii of xxx ...
Page 30: ...Rev 0 50 May 18 2006 Page xxx of xxx ...
Page 52: ...Section 1 Overview Rev 0 50 May 18 2006 Page 22 of 1588 REJ09B0313 0050 ...
Page 98: ...Section 2 CPU Rev 0 50 May 18 2006 Page 68 of 1588 REJ09B0313 0050 ...
Page 128: ...Section 4 Clock Pulse Generator CPG Rev 0 50 May 18 2006 Page 98 of 1588 REJ09B0313 0050 ...
Page 200: ...Section 6 Interrupt Controller INTC Rev 0 50 May 18 2006 Page 170 of 1588 REJ09B0313 0050 ...
Page 242: ...Section 8 Cache Rev 0 50 May 18 2006 Page 212 of 1588 REJ09B0313 0050 ...
Page 400: ...Section 9 Bus State Controller BSC Rev 0 50 May 18 2006 Page 370 of 1588 REJ09B0313 0050 ...
Page 696: ...Section 13 Watchdog Timer WDT Rev 0 50 May 18 2006 Page 666 of 1588 REJ09B0313 0050 ...
Page 726: ...Section 14 Realtime Clock RTC Rev 0 50 May 18 2006 Page 696 of 1588 REJ09B0313 0050 ...
Page 876: ...Section 17 I2 C Bus Interface 3 IIC3 Rev 0 50 May 18 2006 Page 846 of 1588 REJ09B0313 0050 ...
Page 1054: ...Section 21 D A Converter DAC Rev 0 50 May 18 2006 Page 1024 of 1588 REJ09B0313 0050 ...
Page 1294: ...Section 24 LCD Controller LCDC Rev 0 50 May 18 2006 Page 1264 of 1588 REJ09B0313 0050 ...
Page 1386: ...Section 26 I O Ports Rev 0 50 May 18 2006 Page 1356 of 1588 REJ09B0313 0050 ...
Page 1512: ...Section 30 List of Registers Rev 0 50 May 18 2006 Page 1482 of 1588 REJ09B0313 0050 ...
Page 1598: ...Section 31 Electrical Characteristics Rev 0 50 May 18 2006 Page 1568 of 1588 REJ09B0313 0050 ...
Page 1606: ...Appendix Rev 0 50 May 18 2006 Page 1576 of 1588 REJ09B0313 0050 ...
Page 1618: ...Rev 0 50 May 18 2006 Page 1588 of 1588 REJ09B0313 0050 ...
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Page 1622: ...SH7203 Group Hardware Manual ...