R&S NRP2, User Manual

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Remote Control - Commands
R&S
®
NRP2
295 User Manual 1173.9157.02 ─ 03
Command Parameter Remark
<srsc>:PTRansition[?] 0..32767 |<non-decimal
numeric>
STATus:PRESet
​
table 6-32
The status reporting system stores all information about the current operating status of
the device and errors that occur. The information is stored in the status registers and the
error queue. The contents of the status registers and error queue can be queried via the
IEC/IEEE bus. The information is hierarchically structured. The highest level is formed
by the Status Byte Register (STB) defined by IEEE 488.2 and the associated Service
Request Enable (SRE) register. The STB receives its information from the Standard
Event Status Register (ESR) also defined by IEEE 488.2 and the associated Standard
Event Status Enable (ESE) Register, as well as from the SCPI-defined Operation Status
Register and the Questionable Status Register, which contain detailed information on the
device, and from the Device Status Register.
The status reporting system also includes the IST flag (Individual STatus) and the Parallel
Poll Enable Register (PPE) assigned to it. The IST flag, like the SRQ, combines the
complete device status in a single bit. The PPE has the same function for the IST flag as
the SRE has for the service request.
The output buffer (output queue) contains the messages the device returns to the con-
troller. It is not part of the status reporting system but since it determines the value of the
MAV bit in the STB it is also shown in
​
figure 6-17
​
Overview on structure of Status Report-
ing System .
6.13.3 Structure of SCPI Status Register
Each SCPI register consists of five 16-bit registers which have different functions (see
​
figure 6-16
​
Standard SCPI status register ). The individual bits are independent of each
other, i.e. each hardware status is assigned a bit number which is the same for all five
registers. For instance, bit 4 of the operation status register is assigned to the hardware
status "Measurement" in all five registers. Bit 15 (the most-significant bit) is set to zero in
all registers. This prevents problems some controllers have with the processing of
unsigned integers.
STATus