PROFACE PL-B900 Series, User Manual

Page: 73 / 98

System Setup
5-11
PL B900/B910 Series Users Manual
! DMA-0 assigned to
-
DMA-7 assigned to
Only after the "Resources Controlled By" setting is set to [Manual] can the
following
DMA-0 assigned to
-
DMA-7 assigned to
settings be changed. These
settings are used for the [PCI/ISA PnP] and [Legacy ISA] items.
[PCI/ISA PnP] : Used for PCI or ISA's PnP Card
[Legacy ISA]
: Used for ISA Cards that do not comply with PnP
INITIAL SETTING INITIAL SETTING
DMA-0 assigned to
PCI/ISA PnP
DMA-5 assigned to
PCI/ISA PnP
DMA-1 assigned to
PCI/ISA PnP
DMA-6 assigned to
PCI/ISA PnP
DMA-3 assigned to
PCI/ISA PnP
DMA-7 assigned to
PCI/ISA PnP
INITIAL SETTING INITIAL SETTING
IRQ-3 assigned to
Legacy ISA
IRQ-10 assigned to
Legacy ISA
IRQ-4 assigned to
Legacy ISA
IRQ-11 assigned to
PCI/ISA PnP
IRQ-5 assigned to
PCI/ISA PnP
IRQ-12 assigned to
Legacy ISA
IRQ-7 assigned to
Legacy ISA
IRQ-14 assigned to
Legacy ISA
IRQ-9 assigned to
Legacy ISA
IRQ-15 assigned to
PCI/ISA PnP
! IRQ-3 assigned to
-
IRQ-15 assigned to
Only after the "Resources Controlled By" setting is set to [Manual] can the
following IRQ-3assigned to - IRQ-15assigned to settings be changed.
These settings are used for the [PCI/ISA PnP] and [Legacy ISA] items.
[PCI/ISA PnP]
:Used for PCI or ISA's PnP Card
[Legacy ISA] :Used for ISA Cards that do not comply with PnP
! CPU to PCI Write Buffer
Setting for the PCI Write Buffer. If [Disabled] is selected, it becomes the
CPU's Read Cycle [Enable] or [Disable] toggle. The [Enabled] selection is
factory set and recommended for most users.
!
PCI Dynamic Bursting
Setting for the PCI's Burst Transmission. The available settings are
[Enable] and [Disable]. [Enabled] is factory set and recommended for most
users.
! PCI Master 0 WS Write
Sets the duration of the wait for the writing to the PCI Bus to "0".
[Enabled] and [Disabled] are available. The [Enabled] setting is factory set
and recommended for most users.
! PCI Delay Transaction
This feature enables or disables the Chip Set's PCI Delay Transaction
Cycle's built in 32Bit Posted Buffer support. [Enabled] and [Disabled] are
available. The [Enabled] setting is factory set and recommended for most
users.
! PCI Master Read Prefetch
Enables or disables the PCI Master Read Prefetch feature.[Enabled] and
[Disabled] are available. The [Enabled] setting is factory set and
recommended for most users.