46
DM Area Allocation in Simple Counter Mode
Section 5-1
5-1
DM Area Allocation in Simple Counter Mode
The following explains DM and IR bit allocation in simple counter mode.
DM Allocation
Note
The Unit in simple counter mode will accept offset phase inputs and the reset
mode will be set to 0.
The Unit will be in counting operation after the Unit is initialized.
IR Bit Allocation
Word
Bit
Function
m
00 to 03
Operating mode (0: Simple counter mode)
04 to 07
Not used.
08 to 11
Not used.
12 to 15
Present counter value mode
(0: BCD; 1: Hexadecimal)
m+1 to m+99
Not used.
Word
(output)
Bit
Flag
Function
n
00
STOP Both Counters
Command
Unit starts operating when this bit is OFF and stops operating when this
bit is ON.
01 to 03
---
Not used.
04
RESET Counter 1
Command
Counter 1 reset at the rising edge of this bit. Refer to
4-10 Counter
Reset Conditions
.
05
RESET Counter 2
Command
Counter 2 reset at the rising edge of this bit. Refer to
4-10 Counter
Reset Conditions
.
06
READ ERROR command Error codes are read at the rising edge of this bit. When this bit is ON
while the Error Flag (word n+6 bit 15) is 1, error codes will be output to
word n+7.
The error code will be set to 0 when the last error code is read.
Repeatedly turn this bit ON until the error code is set to 0.
The Error Flag is set to 1 while there is any error code.
To reset the Error Flag, use the control code “EC” of the IOWR instruc-
tion. Refer to
11-1 Error Processing
.
07 to 15
---
Not used.
n+1
00 to 15
---
Not used.
Summary of Contents for C200H-CT021
Page 1: ...C200H CT021 High speed Counter Unit Operation Manual Revised December 2000 ...
Page 2: ...iv ...
Page 4: ...vi ...