NEC PD78052 User Manual Download Page 99

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CHAPTER 5 CPU ARCHITECTURE

5.1.1 Internal program memory space

The internal program memory space

stores programs and table data. Normally, they are addressed with a program

counter (PC).

Each product of the

PD78054 and 78054Y Subseries has the internal ROM (or PROM) of the size shown below.

Table 5-1. Internal ROM Capacity

Part number

Internal ROM

Type

Capacity

PD78052, 78052Y

Mask ROM

16384 x 8 bits (0000H to 3FFFH)

PD78053, 78053Y

24576 x 8 bits (0000H to 5FFFH)

PD78054, 78054Y

32768 x 8 bits (0000H to 7FFFH)

PD78055, 78055Y

40960 x 8 bits (0000H to 9FFFH)

PD78056, 78056Y

49152 x 8 bits (0000H to BFFFH)

PD78058, 78058Y

61440 x 8 bits (0000H to EFFFH)

PD78P054

PROM

32768 x 8 bits (0000H to 7FFFH)

PD78P058, 78P058Y

61440 x 8 bits (0000H to EFFFH)

The following areas are allocated to the internal program memory space.

(1) Vector table area

The 64-byte area 0000H to 003FH is reserved as a vector table area. The RESET input and program start

addresses for branch upon generation of each interrupt request are stored in the vector table area. Of the

16-bit address, low-order 8 bits are stored at even addresses and high-order 8 bits are stored at odd addresses.

Table 5-2. Vector Table

Vector Table Address

Interrupt Source

Vector Table Address

Interrupt Source

0000H

RESET input

0018H

INTSER

0004H

INTWDT

001AH

INTSR/INTCSI2

0006H

INTP0

001CH

INTST

0008H

INTP1

001EH

INTTM3

000AH

INTP2

0020H

INTTM00

000CH

INTP3

0022H

INTTM01

000EH

INTP4

0024H

INTTM1

0010H

INTP5

0026H

INTTM2

0012H

INTP6

0028H

INTAD

0014H

INTCSI0

003EH

BRK

0016H

INTCSI1

(2) CALLT instruction table area

The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT).

(3) CALLF instruction entry area

The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF).

Summary of Contents for PD78052

Page 1: ...78052Y µPD78053 µPD78053Y µPD78054 µPD78054Y µPD78P054 µPD78055Y µPD78055 µPD78056Y µPD78056 µPD78058Y µPD78058 µPD78P058Y µPD78P058 µPD78052 A µPD78053 A µPD78054 A Document No U11747EJ5V0UM00 5th edition Date Published April 1998 N CP K 1992 User s Manual Printed in Japan ...

Page 2: ...2 MEMO ...

Page 3: ...r CMOS device inputs can be cause of malfunction If no connection is provided to the input pins it is possible that an internal input level may be generated due to noise etc hence causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected to VDD...

Page 4: ...stem Nucleus ITRON is an abbreviation of Industrial TRON The export of these products from Japan is regulated by the Japanese government The export of some or all of these products may be prohibited without governmental license To export or re export some or all of these products from a country other than Japan may also be prohibited without a license from that country Please call an NEC sales rep...

Page 5: ... semiconductor device customers must incorporate sufficient safety measures in its design such as redundancy fire containment and anti failure features NEC devices are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application The re...

Page 6: ...cs Germany GmbH Duesseldorf Germany Tel 0211 65 03 02 Fax 0211 65 03 490 NEC Electronics UK Ltd Milton Keynes UK Tel 01908 691 133 Fax 01908 670 290 NEC Electronics Italiana s r 1 Milano Italy Tel 02 66 75 41 Fax 02 66 75 42 99 NEC Electronics Germany GmbH Benelux Office Eindhoven The Netherlands Tel 040 2445845 Fax 040 2444580 NEC Electronics France S A Velizy Villacoublay France Tel 01 30 67 58 ...

Page 7: ...it receive Interval time to 18 4 3 3 wire serial I O mode operation with automatic transmit receive function p 439 Addition of precaution to 19 1 3 3 wire serial I O mode MSB LSB first switchable p 444 Change of Figure 19 3 Serial Operating Mode Register 2 Format p 446 Change of Table 19 2 Serial Interface Channel 2 Operating Mode Settings p 465 Correction of Figure 19 10 Receive Error Timing p 47...

Page 8: ...8 MEMO ...

Page 9: ...suffix KK T should be used only for experiment or function evaluation because they are not intended for use in equipment that will be mass produced and require high reliability µPD78P054KK T 78P058KK T 78P058YKK T Purpose This manual is intended for users to understand the functions described in the Organization below Organization The µPD78054 78054Y Subseries manual is separated into two parts th...

Page 10: ...ction in detail Refer to the 78K 0 Series User s Manual Instructions U12326E How to interpret the register format For the circled bit number the bit name is defined as a reserved word in RA78K 0 and in CC78K 0 already defined in the header file named sfrbit h To learn the function of a register whose register name is known Refer to Appendix D Register Index To know the electrical specifications of...

Page 11: ... Timer Event Counter Chapter 9 8 Bit Timer Event Counters 1 and 2 Chapter 10 Watch Timer Chapter 11 Watchdog Timer Chapter 12 Clock Output Control Circuit Chapter 13 Buzzer Output Control Circuit Chapter 14 A D Converter Chapter 15 D A Converter Chapter 16 Serial Interface Channel 0 µPD78054 Subseries Chapter 17 Serial Interface Channel 0 µPD78054Y Subseries Chapter 18 Serial Interface Channel 1 C...

Page 12: ...ce channel 0 µPD78054 µPD78054Y Subseries Subseries 3 wire serial I O mode 2 wire serial I O mode SBI serial bus interface mode I2 C Inter IC bus mode Supported Not supported Legend Data significant Left higher digit right lower digit Active low top bar over pin or signal name Note Footnote Caution Important information Remark Supplement Numerical notation Binary or B Decimal Hexadecimal H ...

Page 13: ...D78054 Subseries Special Function Register Table U10102J 78K 0 Series Application Note Basics III U10182J U10182E Floating point operation program IEA 718 IEA 1289 Related documents for µPD78054Y Subseries Document name Document No Japanese English µPD78052Y 78053Y 78054Y 78055Y 78056Y 78058Y Data Sheet U10906J U10906E µPD78P058Y Data Sheet U10907J U10907E µPD78054 78054Y Subseries User s Manual U...

Page 14: ...ries PC DOS Base EEU 5008 U10540E IE 78K0 NS To be prepared To be prepared IE 78001 R A To be prepared To be prepared IE 780308 NS EM1 To be prepared To be prepared IE 780308 R EM U11362J U11362E EP 78230 EEU 985 EEU 1515 EP 78054GK R EEU 932 EEU 1468 SM78K0 System Simulator Windows Base Reference U10181J U10181E SM78K Series System Simulator External component user U10092J U10092E open interface ...

Page 15: ... Technology Manual C10535J C10535E Quality Grade on NEC Semiconductor Devices C11531J C11531E NEC Semiconductor Device Reliability Quality Control System C10983J C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge ESD C11892J C11892E Guide to Quality Assurance for Semiconductor Devices MEI 1202 Microcontroller Related Product Guide Third Party Manufacturers U11416J...

Page 16: ...16 MEMO ...

Page 17: ...p View 51 2 6 78K 0 Series Expansion 54 2 7 Block Diagram 56 2 8 Outline of Function 57 2 9 Mask Options 58 CHAPTER 3 PIN FUNCTION µPD78054 Subseries 59 3 1 Pin Function List 59 3 1 1 Normal operating mode pins 59 3 1 2 PROM programming mode pins PROM versions only 63 3 2 Description of Pin Functions 64 3 2 1 P00 to P07 Port 0 64 3 2 2 P10 to P17 Port 1 65 3 2 3 P20 to P27 Port 2 65 3 2 4 P30 to P...

Page 18: ... P127 Port 12 84 4 2 10 P130 and P131 Port 13 85 4 2 11 AVREF0 85 4 2 12 AVREF1 85 4 2 13 AVDD 85 4 2 14 AVSS 85 4 2 15 RESET 85 4 2 16 X1 and X2 86 4 2 17 XT1 and XT2 86 4 2 18 VDD 86 4 2 19 VSS 86 4 2 20 VPP PROM versions only 86 4 2 21 IC Mask ROM version only 86 4 3 Input output Circuits and Recommended Connection of Unused Pins 87 CHAPTER 5 CPU ARCHITECTURE 91 5 1 Memory Spaces 91 5 1 1 Inter...

Page 19: ...6 6 2 10 Port 12 148 6 2 11 Port 13 149 6 3 Port Function Control Registers 150 6 4 Port Function Operations 156 6 4 1 Writing to input output port 156 6 4 2 Reading from input output port 156 6 4 3 Operations on input output port 157 6 5 Selection of Mask Option 157 CHAPTER 7 CLOCK GENERATOR 159 7 1 Clock Generator Functions 159 7 2 Clock Generator Configuration 159 7 3 Clock Generator Control Re...

Page 20: ...counter mode 218 9 2 8 Bit Timer Event Counters 1 and 2 Configurations 220 9 3 8 Bit Timer Event Counters 1 and 2 Control Registers 223 9 4 8 Bit Timer Event Counters 1 and 2 Operations 228 9 4 1 8 bit timer event counter mode 228 9 4 2 16 bit timer event counter mode 234 9 5 Cautions on 8 Bit Timer Event Counters 1 and 2 238 CHAPTER 10 WATCH TIMER 241 10 1 Watch Timer Functions 241 10 2 Watch Tim...

Page 21: ...INTERFACE CHANNEL 0 µPD78054 Subseries 287 16 1 Serial Interface Channel 0 Functions 288 16 2 Serial Interface Channel 0 Configuration 290 16 3 Serial Interface Channel 0 Control Registers 294 16 4 Serial Interface Channel 0 Operations 301 16 4 1 Operation stop mode 301 16 4 2 3 wire serial I O mode operation 302 16 4 3 SBI mode operation 307 16 4 4 2 wire serial I O mode operation 333 16 4 5 SCK0...

Page 22: ...2 Real Time Output Port Configuration 478 20 3 Real Time Output Port Control Registers 480 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 483 21 1 Interrupt Function Types 483 21 2 Interrupt Sources and Configuration 484 21 3 Interrupt Function Control Registers 488 21 4 Interrupt Servicing Operations 497 21 4 1 Non maskable interrupt request acknowledge operation 497 21 4 2 Maskable interrupt request ac...

Page 23: ...rating modes 552 26 4 2 PROM write procedure 554 26 4 3 PROM reading procedure 558 26 5 Erasure Procedure µPD78P054KK T and 78P058KK T Only 559 26 6 Opaque Film Masking the Window µPD78P054KK T and 78P058KK T Only 559 26 7 Screening of One Time PROM Versions 559 CHAPTER 27 INSTRUCTION SET 561 27 1 Legends Used in Operation List 562 27 1 1 Operand identifiers and description methods 562 27 1 2 Desc...

Page 24: ...for IBM PC 589 B 5 Upgrading Former In circuit Emulators for 78K 0 Series to IE 78001 R A 589 APPENDIX C EMBEDDED SOFTWARE 593 APPENDIX D REGISTER INDEX 595 D 1 Register Index 595 APPENDIX E REVISION HISTORY 599 ...

Page 25: ...PD78058 78058Y 107 5 16 Data Memory Addressing µPD78P058 78P058Y 108 5 17 Program Counter Configuration 109 5 18 Program Status Word Configuration 109 5 19 Stack Pointer Configuration 111 5 20 Data to be Saved to Stack Memory 111 5 21 Data to be Reset from Stack Memory 111 5 22 General Register Configuration 113 6 1 Port Types 129 6 2 P00 and P07 Block Diagram 135 6 3 P01 to P06 Block Diagram 135 ...

Page 26: ... 6 16 Bit Timer Output Control Register Format 187 8 7 Port Mode Register 3 Format 188 8 8 External Interrupt Mode Register 0 Format 189 8 9 Sampling Clock Select Register Format 190 8 10 Control Register Settings for Interval Timer Operation 191 8 11 Interval Timer Configuration Diagram 192 8 12 Interval Timer Operation Timings 192 8 13 Control Register Settings for PWM Output Operation 194 8 14 ...

Page 27: ...hange of Compare Register During Timer Count Operation 212 8 37 Capture Register Data Retention Timing 213 8 38 Operation Timing of OVF0 Flag 214 9 1 8 Bit Timer Event Counters 1 and 2 Block Diagram 221 9 2 Block Diagram of 8 Bit Timer Event Counter Output Control Circuit 1 222 9 3 Block Diagram of 8 Bit Timer Event Counter Output Control Circuit 2 222 9 4 Timer Clock Select Register 1 Format 224 ...

Page 28: ...10 Example of Method of Reducing Current Dissipation in Standby Mode 278 14 11 Analog Input Pin Disposition 279 14 12 A D Conversion End Interrupt Request Generation Timing 280 14 13 Handling of AVDD Pin 280 15 1 D A Converter Block Diagram 282 15 2 D A Converter Mode Register Format 284 15 3 Use Example of Buffer Amplifier 286 16 1 Serial Bus Interface SBI System Configuration Example 289 16 2 Se...

Page 29: ...erface Channel 0 Block Diagram 345 17 3 Timer Clock Select Register 3 Format 349 17 4 Serial Operating Mode Register 0 Format 351 17 5 Serial Bus Interface Control Register Format 352 17 6 Interrupt Timing Specify Register Format 354 17 7 3 Wire Serial I O Mode Timings 359 17 8 RELT and CMDT Operations 359 17 9 Circuit of Switching in Transfer Bit Order 360 17 10 Serial Bus Configuration Example U...

Page 30: ...it Mode 427 18 17 Automatic Transmission Reception Suspension and Restart 429 18 18 System Configuration When the Busy Control Option is Used 430 18 19 Operation Timings when Using Busy Control Option BUSY0 0 431 18 20 Busy Signal and Wait Cancel when BUSY0 0 432 18 21 Operation Timings when Using Busy Strobe Control Option BUSY0 0 433 18 22 Operation Timing of the Bit Slippage Detection Function ...

Page 31: ...n 496 21 10 Flowchart of Generation from Non Maskable Interrupt Request to Acknowledgment 498 21 11 Non Maskable Interrupt Request Acknowledge Timing 498 21 12 Non Maskable Interrupt Request Acknowledge Operation 499 21 13 Interrupt Request Acknowledge Processing Algorithm 501 21 14 Interrupt Request Acknowledge Timing Minimum Time 502 21 15 Interrupt Request Acknowledge Timing Maximum Time 502 21...

Page 32: ...ample with EEPROM using 2 wire serial I O mode 540 25 6 Initialization Routine 541 25 7 ROM Correction Operation 542 25 8 ROM Correction Example 543 25 9 Program Transition Diagram when one place is corrected 544 25 10 Program Transition Diagram when two places are corrected 545 26 1 Memory Size Switching Register Format µPD78P054 549 26 2 Memory Size Switching Register Format µPD78P058 550 26 3 I...

Page 33: ...figuration 159 7 2 Relationship between CPU Clock and Minimum Instruction Execution Time 163 7 3 Maximum Time Required for CPU Clock Switchover 172 8 1 Timer Event Counter Operations 176 8 2 16 Bit Timer Event Counter Interval Times 177 8 3 16 Bit Timer Event Counter Square Wave Output Ranges 178 8 4 16 Bit Timer Event Counter Configuration 179 8 5 INTP0 TI00 Pin Valid Edge and CR00 Capture Trigge...

Page 34: ...65 15 1 D A Converter Configuration 282 16 1 Differences between Channels 0 1 and 2 287 16 2 Serial Interface Channel 0 Configuration 290 16 3 Various Signals in SBI Mode 323 17 1 Differences between Channels 0 1 and 2 341 17 2 Serial Interface Channel 0 Configuration 344 17 3 Serial Interface Channel 0 Interrupt Request Signal Generation 347 17 4 Signals in I2 C Bus Mode 376 18 1 Serial Interface...

Page 35: ...22 3 Values when the Memory Size Switching Register is Reset 517 23 1 HALT Mode Operating Status 527 23 2 Operation after HALT Mode Release 529 23 3 STOP Mode Operating Status 530 23 4 Operation after STOP Mode Release 532 24 1 Hardware Status after Reset 535 25 1 ROM Correction Configuration 537 26 1 Differences between µPD78P054 78P058 and Mask ROM Versions 547 26 2 Differences between µPD78P054...

Page 36: ...36 MEMO ...

Page 37: ...ion A D converter 8 channels 8 bit resolution D A converter 2 channels Serial interface 3 channels 3 wire serial I O SBI 2 wire serial I O mode 1 channel 3 wire serial I O mode Automatic transmit receive function 1 channel 3 wire serial I O UART mode 1 channel Timer 5 channels 16 bit timer event counter 1 channel 8 bit timer event counter 2 channels Watch timer 1 channel Watchdog timer 1 channel 2...

Page 38: ...0 pin plastic QFP 14 14 mm Resin thickness 1 4 mm One time PROM µPD78P054GK BE9 80 pin plastic TQFP Fine pitch 12 12 mm One time PROM µPD78P054KK T 80 pin ceramic WQFN 14 14 mm EPROM µPD78055GC 8BT 80 pin plastic QFP 14 14 mm Resin thickness 1 4 mm Mask ROM µPD78055GK BE9 80 pin plastic TQFP Fine pitch 12 12 mm Mask ROM µPD78056GC 8BT 80 pin plastic QFP 14 14 mm Resin thickness 1 4 mm Mask ROM µPD...

Page 39: ...14 mm Resin thickness 1 4 mm Standard µPD78056GK BE9 80 pin plastic TQFP Fine pitch 12 12 mm Standard µPD78058GC 8BT 80 pin plastic QFP 14 14 mm Resin thickness 1 4 mm Standard µPD78058GK BE9 80 pin plastic TQFP Fine pitch 12 12 mm Standard µPD78P058GC 8BT 80 pin plastic QFP 14 14 mm Resin thickness 1 4 mm Standard µPD78P058KK T 80 pin ceramic WQFN 14 14 mm Not applicable for function evalution µP...

Page 40: ...µPD78P054 78P058 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P15 ANI5 P16 ANI6 P17 ANI7 AVSS P130 ANO0 P131 ANO1 AVREF1 P70 SI2 RxD P71 SO2 TxD P72 SCK2 ASCK P20 SI1 P21 SO1 P22 SCK1 P23 STB P24 BUSY P25 SI0 SB0 P26 SO0 SB1 P27 SCK0 P40 AD0 P41 AD1 RESET P127 RTP7 P126 RTP6 P125 RTP5 P124 RTP4 P123 RTP3 P122 RTP2 P121 RTP1 P120 RTP...

Page 41: ...erence Voltage SCK0 to SCK2 Serial Clock AVSS Analog Ground S10 to S12 Serial Input BUSY Busy SO0 to SO2 Serial Output BUZ Buzzer Clock STB Strobe IC Internally Connected TI00 TI01 Timer Input INTP0 to INTP6 Interrupt from Peripherals TI1 TI2 Timer Input P00 to P07 Port0 TO0 to TO2 Timer Output P10 to P17 Port1 TxD Transmit Data P20 to P27 Port2 VDD Power Supply P30 to P37 Port3 VPP Programming Po...

Page 42: ...ct to the ground 3 RESET Set to the low level 4 Open Leave this pin unconnected A0 to A16 Address Bus RESET Reset CE Chip Enable VDD Power Supply D0 to D7 Data Bus VPP Programming Power Supply OE Output Enable VSS Ground PGM Program 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 VSS RESET D7 D6 D5 D4 D3 D2 D1 D0 CE V SS V DD L Open V ...

Page 43: ...18FY µPD78014Y 64 pin 64 pin 64 pin Low voltage 1 8 V version of µPD78014 and enhanced ROM RAM size options Added A D and 16 bit timer to µPD78002 Added A D to µPD78002 Basic subseries for control applications Equipped with UART and operates at low voltage 1 8 V Enhanced I O and FIP C D of µPD78044F 53 display outputs Enhanced I O and FIP C D of µPD78044H 48 display outputs µPD780964 µPD780924 64 ...

Page 44: ...o 32 K 2 7 V µPD780001 8 K 1 ch 39 µPD78002 8 K to 16 K 1 ch 53 µPD78083 8 ch 1 ch UART 1 ch 33 1 8 V Inverter µPD780988 32 K to 60 K 3 ch Note 1 1 ch 8 ch 3 ch UART 2 ch 47 4 0 V control µPD780964 8 K to 32 K Note 2 2 ch UART 2 ch 2 7 V µPD780924 8 ch FIP µPD780208 32 K to 60 K 2 ch 1 ch 1 ch 1 ch 8 ch 2 ch 74 2 7 V driving µPD780228 48 K to 60 K 3 ch 1 ch 72 4 5 V µPD78044H 32 K to 48 K 2 ch 1 c...

Page 45: ...DD VSS IC VPP 78K 0 CPU CORE ROM RAM PORT 0 PORT 1 PORT 2 PORT 3 PORT 4 PORT 5 PORT 6 PORT 7 PORT 12 PORT 13 REAL TIME OUTPUT PORT EXTERNAL ACCESS SYSTEM CONTROL P00 P01 P06 P07 P10 P17 P20 P27 P30 P37 P40 P47 P50 P57 P60 P67 P70 P72 P120 P127 P130 P131 RTP0 P120 RTP7 P127 AD0 P40 AD7 P47 A8 P50 A15 P57 RD P64 WR P65 WAIT P66 ASTB P67 RESET X1 X2 XT1 P07 XT2 TO0 P30 TI00 INTP0 P00 TI01 INTP1 P01 T...

Page 46: ...le 1 channel 3 wire serial I O mode Max 32 byte on chip auto transmit receive 1 channel 3 wire serial I O UART mode selectable 1 channel Timer 16 bit timer event counter 1 channel 8 bit timer event counter 2 channels Watch timer 1 channel Watchdog timer 1 channel Timer output Three outputs 14 bit PWM output enable 1 Clock output 19 5 kHz 39 1 kHz 78 1 kHz 156 kHz 313 kHz 625 kHz 1 25 MHz 2 5 MHz 5...

Page 47: ...Resin thickness 2 7 mm µPD78P054 only 80 pin plastic QFPNote 3 14 14 mm Resin thickness 1 4 mm 80 pin plastic TQFP Fine pitch 12 12 mm except µPD78P058 80 pin ceramic WQFN 14 14 mm µPD78P054 78P058 only Notes 1 The µPD78P054 is the PROM version for the µPD78052 78053 78054 2 The µPD78P058 is the PROM version for the µPD78055 78056 78058 3 The µPD78P054 is under development Item Part Number µPD7805...

Page 48: ... 7 mm 80 pin plastic TQFP Fine pitch 12 12 mm Recommended Refer to separate Data Sheets soldering conditions 1 10 Mask Options The mask ROM versions µPD78052 78053 78054 78055 78056 78058 provide pull up resistor mask options which allow users to specify whether to connect a pull up resistor to a specific port pin when the user places an order for the device production Using this mask option when ...

Page 49: ...ts 4 8 bit resolution A D converter 8 channels 8 bit resolution D A converter 2 channels Serial interface 3 channels 3 wire serial I O 2 wire serial I O I2C bus mode 1 channel 3 wire serial I O mode Automatic transmit receive function 1 channel 3 wire serial I O UART mode 1 channel Timer Five channels 16 bit timer event counter 1 channel 8 bit timer event counter 2 channels Watch timer 1 channel W...

Page 50: ...58YKK T 80 pin ceramic WQFN 14 14 mm EPROM Remark indicates ROM code suffix 2 4 Quality Grade Part number Package Quality grade µPD78052YGC 8BT 80 pin plastic QFP 14 14 mm Resin thickness 1 4 mm Standard µPD78053YGC 8BT 80 pin plastic QFP 14 14 mm Resin thickness 1 4 mm Standard µPD78054YGC 8BT 80 pin plastic QFP 14 14 mm Resin thickness 1 4 mm Standard µPD78055YGC 8BT 80 pin plastic QFP 14 14 mm ...

Page 51: ...5 ANI5 P16 ANI6 P17 ANI7 AVSS P130 ANO0 P131 ANO1 AVREF1 P70 SI2 RxD P71 SO2 TxD P72 SCK2 ASCK P20 SI1 P21 SO1 P22 SCK1 P23 STB P24 BUSY P25 SI0 SB0 SDA0 P26 SO0 SB1 SDA1 P27 SCK0 SCL P40 AD0 P41 AD1 RESET P127 RTP7 P126 RTP6 P125 RTP5 P124 RTP4 P123 RTP3 P122 RTP2 P121 RTP1 P120 RTP0 P37 P36 BUZ P35 PCL P34 TI2 P33 TI1 P32 TO2 P31 TO1 P30 TO0 P67 ASTB P66 WAIT P65 WR P14 ANI4 P13 ANI3 P12 ANI2 P1...

Page 52: ...Voltage SCL Serial Clock AVSS Analog Ground SDA0 SDA1 Serial Data BUSY Busy SI0 SI1 Serial Input BUZ Buzzer Clock SO0 SO1 Serial Output IC Internally Connected STB Strobe INTP0 to INTP6 Interrupt from Peripherals TI1 TI2 Timer Input P00 to P07 Port0 TI00 to TI01 Timer Input P10 to P17 Port1 TO0 to TO2 Timer Output P20 to P27 Port2 TxD Transmit Data P30 to P37 Port3 VDD Power Supply P40 to P47 Port...

Page 53: ... A16 Address Bus RESET Reset CE Chip Enable VDD Power Supply D0 to D7 Data Bus VPP Programming Power Supply OE Output Enable VSS Ground PGM Program 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 VSS RESET D7 D6 D5 D4 D3 D2 D1 D0 CE V SS V DD L Open V PP L Open V DD PGM L A9 A2 A3 A4 A5 A6 A7 A8 A16 A10 A11 A12 A13 V SS A14 A15 OE 21 2...

Page 54: ...8FY µPD78014Y 64 pin 64 pin 64 pin Low voltage 1 8 V version of µPD78014 and enhanced ROM RAM size options Added A D and 16 bit timer to µPD78002 Added A D to µPD78002 Basic subseries for control applications Equipped with UART and operates at low voltage 1 8 V Enhanced I O and FIP C D of µPD78044F 53 display outputs Enhanced I O and FIP C D of µPD78044H 48 display outputs µPD780964 µPD780924 64 p...

Page 55: ... wire time division UART 1 ch µPD78058FY 48K to 60K 3 wire 2 wire I2C 1 ch 69 2 7 V µPD78054Y 16K to 60K 3 wire with automatic transmit receive function 1 ch 2 0 V 3 wire UART 1 ch µPD780034Y 8K to 32K UART 1 ch 51 1 8 V 3 wire 1 ch µPD780024Y I2C bus supports multi master 1 ch µPD78018FY 8K to 60K 3 wire 2 wire I2C 1 ch 53 3 wire with automatic transmit receive function 1 ch µPD78014Y 8K to 32K 3...

Page 56: ...VPP 78K 0 CPU CORE ROM RAM PORT 0 PORT 1 PORT 2 PORT 3 PORT 4 PORT 5 PORT 6 PORT 7 PORT 12 PORT 13 REAL TIME OUTPUT PORT EXTERNAL ACCESS SYSTEM CONTROL P00 P01 P06 P07 P10 P17 P20 P27 P30 P37 P40 P47 P50 P57 P60 P67 P70 P72 P120 P127 P130 P131 RTP0 P120 RTP7 P127 AD0 P40 AD7 P47 A8 P50 A15 P57 RD P64 WR P65 WAIT P66 ASTB P67 RESET X1 X2 XT1 P07 XT2 TO0 P30 TI00 INTP0 P00 TI01 INTP1 P01 TO1 P31 TI1...

Page 57: ... O 2 wire serial I O I2C bus mode selection possible 1 channel 3 wire serial I O mode Max 32 byte on chip auto transmit receive 1 channel 3 wire serial I O UART mode selectable 1 channel Timer 16 bit timer event counter 1 channel 8 bit timer event counter 2 channels Watch timer 1 channel Watchdog timer 1 channel Timer output Three outputs 14 bit PWM output enable 1 Clock output 19 5 kHz 39 1 kHz 7...

Page 58: ...054Y 78055Y 78056Y 78058Y provide pull up resistor mask options which allow users to specify whether to connect a pull up resistor to a specific port pin when the user places an order for the device production Using this mask option when pull up resistors are required reduces the number of components to add to the device resulting in board space saving The mask options provided in the µPD78054Y su...

Page 59: ...utput mode can be specified in 1 bit units Input ANI0 to ANI7 When used as input port an on chip pull up resistor can be used by softwareNote2 P20 SI1 P21 SO1 P22 Port 2 SCK1 P23 Input 8 bit input output port STB P24 output Input output mode can be specified in 1 bit units BUSY P25 When used as an input port an on chip pull up resistor can be used by SI0 SB0 P26 software SO0 SB1 P27 SCK0 Notes 1 W...

Page 60: ...ction Port 5 8 bit input output port Input LED can be driven directly output Input output mode can be specified in 1 bit units When used as an input port an on chip pull up resistor can be used by software P60 P61 P62 Port 6 P63 Input 8 bit input output port P64 output Input output mode can be When used as an input port an Input RD P65 specified in 1 bit units on chip pull up resistor can be used ...

Page 61: ...t Input output mode can be specified in 1 bit units When used as an input port an on chip pull up resistor can be used by software Input Port 13 output 2 bit input output port Input output mode can be specified in 1 bit units When used as an input port an on chip pull up resistor can be used by software P130 to P131 Input ANO0 to ANO1 P120 to P127 Input RTP0 to RTP7 ...

Page 62: ...tic transmit receive busy input Input P24 RxD Input Asynchronous serial interface serial data input Input P70 SI2 TxD Output Asynchronous serial interface serial data output Input P71 SO2 ASCK Input Asynchronous serial interface serial clock input Input P72 SCK2 TI00 External count clock input to 16 bit timer TM0 P00 INTP0 TI01 Capture trigger signal input to capture register CR00 P01 INTP1 TI1 Ex...

Page 63: ...put AVREF1 Input D A converter reference voltage input AVDD A D converter analog power supply Connect to VDD AVSS A D and D A converter ground potential Connect to VSS RESET Input System reset input X1 Input X2 XT1 Input Input P07 XT2 VDD Positive power supply High voltage application for program write verify Directly connect to VSS in normal operating mode VSS Ground potential IC Internally conne...

Page 64: ...hen they are used as input ports on chip pull up resistors can be used to them by defining the pull up resistor option register L PUOL 2 Control mode In this mode these ports function as an external interrupt request input an external count clock input to the timer and crystal connection for subsystem clock oscillation a INTP0 to INTP6 INTP0 to INTP6 are external interrupt request input pins which...

Page 65: ...7 Port 2 These are 8 bit input output ports Besides serving as input output ports they function as data input output to from the serial interface clock input output automatic transmit receive busy input and strobe output functions The following operating modes can be specified in 1 bit units 1 Port mode These ports function as 8 bit input output ports They can be specified in 1 bit units as input ...

Page 66: ...t ports Beside serving as input output ports they function as timer input output clock output and buzzer output The following operating modes can be specified in 1 bit units 1 Port mode These ports function as 8 bit input output ports They can be specified in 1 bit units as input or output ports with port mode register 3 PM3 When they are used as input ports on chip pull up resistors can be used b...

Page 67: ...output ports with port mode register 5 PM5 When they are used as input ports on chip pull up resistors can be used by defining the pull up resistor option register L PUOL 2 Control mode These ports function as high order address bus pins A8 to A15 in external memory expansion mode When pins are used as an address bus the on chip pull up resistor is automatically disabled 3 2 7 P60 to P67 Port 6 Th...

Page 68: ...put ports on chip pull up resistors can be used by defining the pull up resistor option register L PUOL 2 Control mode Port 7 functions as serial interface data input output and clock input output a SI2 SO2 Serial interface serial data input output pins b SCK2 Serial interface serial clock input output pin c RxD TxD Asynchronous serial interface serial data input output pins d ASCK Asynchronous se...

Page 69: ...following operating modes can be specified in 1 bit units 1 Port mode These ports function as 2 bit input output ports They can be specified in 1 bit units as input or output ports with port mode register 13 PM13 When they are used as input ports on chip pull up resistors can be used by defining the pull up resistor option register H PUOH 2 Control mode These ports allow D A converter analog outpu...

Page 70: ... clock oscillation For external clock supply input it to XT1 and its inverted signal to XT2 3 2 18 VDD Positive power supply pin 3 2 19 VSS Ground potential pin 3 2 20 VPP PROM versions only High voltage apply pin for PROM programming mode setting and program write verify Directly connect to VSS in the normal operating mode 3 2 21 IC Mask ROM version only The IC Internally Connected pin is provide...

Page 71: ... P30 TO0 P31 TO1 5 A P32 TO2 P33 TI1 P34 TI2 P35 PCL P36 BUZ 5 A P37 P40 AD0 to P47 AD7 5 E Input Output Individually connect to VDD via a resistor P50 A8 to P57 A15 5 A Input output Individually connect to VDD or VSS via a resistor Input Output 8 A Input Output Pin Name Input Output Recommended Connection of Unused Pins 8 A 3 3 Input output Circuits and Recommended Connection of Unused Pins Table...

Page 72: ...ia a resistor P60 to P63 PROM version 13 D P64 RD Input output Individually connect to VDD or VSS via a resistor P65 WR P66 WAIT P67 ASTB P70 SI2 RxD 8 A P71 SO2 TxD 5 A P72 SCK2 ASCK 8 A P120 RTP0 to P127 RTP7 5 A P130 ANO0 P131 ANO1 12 A Input output Individually connect to VSS via a resistor RESET 2 Input XT2 16 Leave open AVREF0 Connect to VSS AVREF1 Connect to VDD AVDD AVSS Connect to VSS IC ...

Page 73: ...gered Input with Hysteresis Characteristics Type 5 E Type 11 Type 10 A Type 8 A pullup enable VDD P ch IN OUT output disable data VDD P ch N ch pullup enable VDD P ch IN OUT output disable data VDD P ch N ch pullup enable VDD P ch IN OUT open drain output disable data VDD P ch N ch pullup enable VDD P ch IN OUT output disable data VDD P ch N ch P ch comparator N ch input enable VREF Threshold volt...

Page 74: ...breakdown input buffer data P ch XT2 XT1 feedback cut off P ch Type 16 output disable VDD VDD N ch Mask Option IN OUT RD medium breakdown input buffer data P ch pullup enable VDD P ch IN OUT output disable data VDD P ch N ch input enable P ch N ch analog output voltage Figure 3 1 Pin Input Output Circuit of List 2 2 ...

Page 75: ...mode can be specified in 1 bit units Input ANI0 to ANI7 When used as input port an on chip pull up resistor can be used by softwareNote2 P20 SI1 P21 SO1 P22 Port 2 SCK1 P23 Input 8 bit input output port STB P24 output Input output mode can be specified in1 bit units BUSY P25 When used as an input port an on chip pull up resistor can be used by SI0 SB0 SDA0 P26 software SO0 SB1 SDA1 P27 SCK0 SCL No...

Page 76: ...ut output mode can be specified in 8 bit units output When used as an input port an on chip pull up resistor can be used by software Test input flag KRIF is set to 1 by falling edge detection Port 5 8 bit input output port Input LED can be driven directly output Input output mode can be specified in 1 bit units When used as an input port an on chip pull up resistor can be used by software P60 P61 ...

Page 77: ...t Input output mode can be specified in 1 bit units When used as an input port an on chip pull up resistor can be used by software Input Port 13 output 2 bit input output port Input output mode can be specified in 1 bit units When used as an input port an on chip pull up resistor can be used by software P130 to P131 Input ANO0 to ANO1 P120 to P127 Input RTP0 to RTP7 ...

Page 78: ...3 BUSY Input Serial interface automatic transmit receive busy input Input P24 RxD Input Asynchronous serial interface serial data input Input P70 SI2 TxD Output Asynchronous serial interface serial data output Input P71 SO2 ASCK Input Asynchronous serial interface serial clock input Input P72 SCK2 TI00 External count clock input to 16 bit timer TM0 P00 INTP0 TI01 Capture trigger signal input to ca...

Page 79: ...r supply Connect to VDD AVSS A D and D A converter ground potential Connect to VSS RESET Input System reset input X1 Input X2 XT1 Input Input P07 XT2 VDD Positive power supply High voltage application for program write verify Directly connect to VSS in normal operating mode VSS Ground potential IC Internally connected Connect directly to VSS 4 1 2 PROM programming mode pins PROM versions only Pin ...

Page 80: ...When they are used as input ports on chip pull up resistors can be used to them by defining the pull up resistor option register L PUOL 2 Control mode In this mode these ports function as an external interrupt request input an external count clock input to the timer and crystal connection for subsystem clock oscillation a INTP0 to INTP6 INTP0 to INTP6 are external interrupt request input pins whic...

Page 81: ...nsmit receive busy input and strobe output functions The following operating modes can be specified in 1 bit units 1 Port mode These ports function as 8 bit input output ports They can be specified in 1 bit units as input or output ports with port mode register 2 PM2 When they are used as input ports on chip pull up resistors can be used to them by defining the pull up resistor option register L P...

Page 82: ...ut to the 8 bit timer event counter b TO0 to TO2 Timer output pins c PCL Clock output pin d BUZ Buzzer output pin 4 2 5 P40 to P47 Port 4 These are 8 bit input output ports Besides serving as input output ports they function as an address data bus The test input flag KRIF can be set to 1 by detecting a falling edge The following operating mode can be specified in 8 bit units 1 Port mode These port...

Page 83: ...P67 Port 6 These are 8 bit input output ports Besides serving as input output ports they are used for control in external memory expansion mode P60 to P63 can drive LEDs directly The following operating modes can be specified in 1 bit units 1 Port mode These ports function as 8 bit input output ports They can be specified in 1 bit units as input or output ports with port mode register 6 PM6 P60 to...

Page 84: ...n c RxD TxD Asynchronous serial interface serial data input output pins d ASCK Asynchronous serial interface serial clock input output pin Caution When this port is used as a serial interface the I O and output latches must be set according to the function the user requires For the setting see to the operation mode setting list in Table 19 2 Serial Interface Channel 2 4 2 9 P120 to P127 Port 12 Th...

Page 85: ... VDD the other pins that are not used as analog outputs must be set as follows Set PM13x bit of the port mode register 13 PM13 to 1 input mode and connect the pin to VSS Set PM13x bit of the port mode register 13 PM13 to 0 output mode and the output latch to 0 to output low level from the pin 4 2 11 AVREF0 A D converter reference voltage input pin When A D converter is not used connect this pin to...

Page 86: ...ly High voltage apply pin for PROM programming mode setting and program write verify Directly connect to VSS in the normal operating mode 4 2 21 IC Mask ROM version only The IC Internally Connected pin is provided to set the test mode to check the µPD78054Y Subseries before shipment Directly connect the pin to the VSS with the shortest possible wire in the normal operating mode When a voltage diff...

Page 87: ...CL resistor P30 TO0 5 A P31 TO1 P32 TO2 P33 TI1 P34 TI2 P35 PCL 5 A P36 BUZ P37 P50 A8 to P57 A15 5 A Input output Individually connect to VDD or VSS via a resistor P40 AD0 to P47 AD7 5 E Input Output Individually connect to VDD via a resistor Input Output Input Output Pin Name Input Output Recommended Connection of Unused Pins 8 A 4 3 Input output Circuits and Recommended Connection of Unused Pin...

Page 88: ...t Individually connect to VDD or VSS via a resistor P65 WR P66 WAIT P67 ASTB P70 SI2 RxD 8 A P71 SO2 TxD 5 A P72 SCK2 ASCK 8 A P120 RTP0 to P127 RTP7 5 A P130 ANO0 to P131 ANO1 12 A Input output Individually connect to VSS via a resistor RESET 2 Input XT2 16 Leave open AVREF0 Connect to VSS AVREF1 Connect to VDD AVDD AVSS Connect to VSS IC Mask ROM version Directly connect to VSS VPP PROM version ...

Page 89: ...gered Input with Hysteresis Characteristics Type 5 E Type 11 Type 10 A Type 8 A pullup enable VDD P ch IN OUT output disable data VDD P ch N ch pullup enable VDD P ch IN OUT output disable data VDD P ch N ch pullup enable VDD P ch IN OUT open drain output disable data VDD P ch N ch pullup enable VDD P ch IN OUT output disable data VDD P ch N ch P ch comparator N ch input enable VREF Threshold volt...

Page 90: ...pe 13 D output disable VDD N ch IN OUT RD medium breakdown input buffer data P ch XT2 XT1 feedback cut off P ch Type 16 output disable VDD VDD N ch Mask Option IN OUT RD medium breakdown input buffer data P ch pullup enable VDD P ch IN OUT output disable data VDD P ch N ch input enable P ch N ch analog output voltage ...

Page 91: ...egisters 32 8 bits Internal ROM 16384 8 bits 3FFFH 1000H 0FFFH 0800H 07FFH 0080H 007FH 0040H 003FH 0000H CALLF Entry Area CALLT Table Area Vector Table Area Program Area Program Area Internal Buffer RAM 32 8 bits External Memory 47744 8 bits Reserved Program memory space 4000H 3FFFH FA80H FA7FH FAC0H FABFH FAE0H FADFH FEE0H FEDFH FF00H FEFFH FFFFH Internal High speed RAM 512 8 bits Special Functio...

Page 92: ...H 0080H 007FH 0040H 003FH 0000H CALLF Entry Area CALLT Table Area Vector Table Area Program Area Program Area Internal Buffer RAM 32 8 bits External Memory 39552 8 bits Reserved Program memory space 6000H 5FFFH FA80H FA7FH FAC0H FABFH FAE0H FADFH FEE0H FEDFH FF00H FEFFH FFFFH Internal High speed RAM 1024 8 bits Special Function Registers SFRs 256 8 bits Reserved FB00H FAFFH ...

Page 93: ...H 0080H 007FH 0040H 003FH 0000H CALLF Entry Area CALLT Table Area Vector Table Area Program Area Program Area Internal Buffer RAM 32 8 bits External Memory 31360 8 bits Reserved Program memory space 8000H 7FFFH FA80H FA7FH FAC0H FABFH FAE0H FADFH FEE0H FEDFH FF00H FEFFH FFFFH Internal High speed RAM 1024 8 bits Special Function Registers SFRs 256 8 bits Reserved FB00H FAFFH ...

Page 94: ... CALLF Entry Area CALLT Table Area Vector Table Area Program Area Program Area Internal Buffer RAM 32 8 bits External Memory 31360 8 bits Reserved Program memory space 8000H 7FFFH FA80H FA7FH FAC0H FABFH FAE0H FADFH FEE0H FEDFH FF00H FEFFH FFFFH Internal High speed RAM 1024 8 bits Special Function Registers SFRs 256 8 bits Reserved FB00H FAFFH General Registers 32 8 bits ...

Page 95: ...H 0080H 007FH 0040H 003FH 0000H CALLF Entry Area CALLT Table Area Vector Table Area Program Area Program Area Internal Buffer RAM 32 8 bits External Memory 23168 8 bits Reserved Program memory space A000H 9FFFH FA80H FA7FH FAC0H FABFH FAE0H FADFH FEE0H FEDFH FF00H FEFFH FFFFH Internal High speed RAM 1024 8 bits Special Function Registers SFRs 256 8 bits Reserved FB00H FAFFH ...

Page 96: ...H 0080H 007FH 0040H 003FH 0000H CALLF Entry Area CALLT Table Area Vector Table Area Program Area Program Area Internal Buffer RAM 32 8 bits External Memory 14976 8 bits Reserved Program memory space C000H BFFFH FA80H FA7FH FAC0H FABFH FAE0H FADFH FEE0H FEDFH FF00H FEFFH FFFFH Internal High speed RAM 1024 8 bits Special Function Registers SFRs 256 8 bits Reserved FB00H FAFFH ...

Page 97: ... memory space General Registers 32 8 bits Internal ROM 61440 8 bits EFFFH 1000H 0FFFH 0800H 07FFH 0080H 007FH 0040H 003FH 0000H CALLF Entry Area CALLT Table Area Vector Table Area Program Area Program Area Internal Buffer RAM 32 8 bits Reserved Note Reserved Program memory space F000H EFFFH F800H F7FFH FAC0H FABFH FAE0H FADFH FEE0H FEDFH FF00H FEFFH FFFFH Internal High speed RAM 1024 8 bits Specia...

Page 98: ...ata memory space General Registers 32 8 bits Internal PROM 61440 8 bits EFFFH 1000H 0FFFH 0800H 07FFH 0080H 007FH 0040H 003FH 0000H CALLF Entry Area CALLT Table Area Vector Table Area Program Area Program Area Internal Buffer RAM 32 8 bits Reserved Program memory space F000H EFFFH F800H F7FFH FAC0H FABFH FAE0H FADFH FEE0H FEDFH FF00H FEFFH FFFFH Internal High speed RAM 1024 8 bits Special Function...

Page 99: ...m memory space 1 Vector table area The 64 byte area 0000H to 003FH is reserved as a vector table area The RESET input and program start addresses for branch upon generation of each interrupt request are stored in the vector table area Of the 16 bit address low order 8 bits are stored at even addresses and high order 8 bits are stored at odd addresses Table 5 2 Vector Table Vector Table Address Int...

Page 100: ...AC0H to FADFH The buffer RAM is used to store transmit receive data of serial interface channel 1 in three wire serial I O mode with automatic transfer receive function If the three wire serial I O mode with automatic transfer receive function is not used the buffer RAM can also be used as normal RAM Buffer RAM can also be used as normal RAM 3 Internal expansion RAM µPD78058 78058Y 78P058 78P058Y ...

Page 101: ...l registers This area is between FD00H and FFFFH for the µPD78052 and 78052Y and between FB00H and FFFFH for the µPD78053 78053Y 78054 78054Y 78P054 78055 78055Y 78056 78056Y 78058 78058Y 78P058 and 78P058Y The data memory space is the entire 64K byte space 0000H to FFFFH Figure 5 9 to 5 16 show the data memory addressing modes For details of each addressing refer to 5 4 Operand Address Addressing...

Page 102: ...l Memory 39552 8 bits Reserved 6000H 5FFFH FA80H FA7FH FAC0H FABFH FAE0H FADFH FEE0H FEDFH FF00H FEFFH FFFFH Internal High speed RAM 1024 8 bits Reserved FB00H FAFFH FF20H FF1FH FE20H FE1FH Special Function Registers SFRs 256 8 bits SFR Addressing Register Addressing Short Direct Addressing Direct Addressing Register Indirect Addressing Based Addressing Based Indexed Addressing ...

Page 103: ...l Memory 31360 8 bits Reserved 8000H 7FFFH FA80H FA7FH FAC0H FABFH FAE0H FADFH FEE0H FEDFH FF00H FEFFH FFFFH Internal High speed RAM 1024 8 bits Reserved FB00H FAFFH FF20H FF1FH FE20H FE1FH Special Function Registers SFRs 256 8 bits SFR Addressing Register Addressing Short Direct Addressing Direct Addressing Register Indirect Addressing Based Addressing Based Indexed Addressing ...

Page 104: ...Memory 31360 8 bits Reserved 8000H 7FFFH FA80H FA7FH FAC0H FABFH FAE0H FADFH FEE0H FEDFH FF00H FEFFH FFFFH Internal High speed RAM 1024 8 bits Reserved FB00H FAFFH FF20H FF1FH FE20H FE1FH Special Function Registers SFRs 256 8 bits SFR Addressing Register Addressing Short Direct Addressing Direct Addressing Register Indirect Addressing Based Addressing Based Indexed Addressing ...

Page 105: ...l Memory 23168 8 bits Reserved A000H 9FFFH FA80H FA7FH FAC0H FABFH FAE0H FADFH FEE0H FEDFH FF00H FEFFH FFFFH Internal High speed RAM 1024 8 bits Reserved FB00H FAFFH FF20H FF1FH FE20H FE1FH Special Function Registers SFRs 256 8 bits SFR Addressing Register Addressing Short Direct Addressing Direct Addressing Register Indirect Addressing Based Addressing Based Indexed Addressing ...

Page 106: ...l Memory 14976 8 bits Reserved C000H BFFFH FA80H FA7FH FAC0H FABFH FAE0H FADFH FEE0H FEDFH FF00H FEFFH FFFFH Internal High speed RAM 1024 8 bits Reserved FB00H FAFFH FF20H FF1FH FE20H FE1FH Special Function Registers SFRs 256 8 bits SFR Addressing Register Addressing Short Direct Addressing Direct Addressing Register Indirect Addressing Based Addressing Based Indexed Addressing ...

Page 107: ...0H General Registers 32 8 bits Internal ROM 61440 8 bits Internal Buffer RAM 32 8 bits Reserved F000H EFFFH F800H F7FFH FAC0H FABFH FAE0H FADFH FEE0H FEDFH FF00H FEFFH FFFFH Internal High speed RAM 1024 8 bits Reserved FB00H FAFFH F400H F3FFH FF20H FF1FH FE20H FE1FH Special Function Registers SFRs 256 8 bits Internal Expansion RAM 1024 8 bits SFR Addressing Register Addressing Short Direct Address...

Page 108: ... 0000H General Registers 32 8 bits Internal PROM 61440 8 bits Internal Buffer RAM 32 8 bits Reserved F000H EFFFH F800H F7FFH FAC0H FABFH FAE0H FADFH FEE0H FEDFH FF00H FEFFH FFFFH Internal High speed RAM 1024 8 bits Reserved FB00H FAFFH F400H F3FFH FF20H FF1FH FE20H FE1FH Special Function Registers SFRs 256 8 bits Internal Expansion RAM 1024 8 bits SFR Addressing Register Addressing Short Direct Ad...

Page 109: ...s are automatically stacked upon interrupt request generation or PUSH PSW instruction execution and are automatically reset upon execution of the RETB RETI and POP PSW instructions RESET input sets the PSW to 02H Figure 5 18 Program Status Word Configuration a Interrupt enable flag IE This flag controls the interrupt request acknowledge operations of the CPU When IE 0 all interrupts except the non...

Page 110: ...ed by the status of the interrupt enable flag IE f Carry flag CY This flag stores overflow and underflow upon add subtract instruction execution It stores the shift out value upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction execution 3 Stack pointer SP This is a 16 bit register to hold the start address of the memory stack area Only the inter...

Page 111: ...ta to be Saved to Stack Memory Figure 5 21 Data to be Reset from Stack Memory 15 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 0 PC0 SP Interrupt and BRK Instruction PSW PC15 PC8 PC15 PC8 PC7 PC0 Register Pair Lower SP SP _ 2 SP _ 2 Register Pair Upper CALL CALLF and CALLT Instruction PUSH rp Instruction SP _ 1 SP SP SP _ 2 SP _ 2 SP _ 1 SP PC7 PC0 SP _ 3 SP _ 2 SP _ 1 SP SP SP...

Page 112: ...ruction SEL RBn Because of the 4 register bank configuration an efficient program can be created by switching between a register for normal processing and a register for interruption for each bank Table 5 5 Correspondent Table of Absolute Addresses in the General Registers Bank Register Absolute Bank Register Absolute Functional Name Absolute Name Address Functional Name Absolute Name Address BANK...

Page 113: ...L D E B C A X 16 Bit Processing 8 Bit Processing FEF0H FEEFH FEE8H FEE7H Figure 5 22 General Register Configuration a Absolute Name b Function Name BANK0 BANK1 BANK2 BANK3 FEFFH FEF8H FEF7H FEE0H RP3 RP2 RP1 RP0 R7 15 0 7 0 R6 R5 R4 R3 R2 R1 R0 16 Bit Processing 8 Bit Processing FEF0H FEEFH FEE8H FEE7H ...

Page 114: ...ulation can also be specified with an address 16 bit manipulation Describe the symbol reserved with assembler for the 16 bit manipulation instruction operand sfrp When addressing an address describe an even address Table 5 6 gives a list of special function registers The meaning of items in the table is as follows Symbol Symbols indicating the addresses of special function register These symbols a...

Page 115: ...t register ADCR R FF20H Port mode register 0 PM0 FF21H Port mode register 1 PM1 FF22H Port mode register 2 PM2 FF23H Port mode register 3 PM3 FF25H Port mode register 5 PM5 FF26H Port mode register 6 PM6 FF27H Port mode register 7 PM7 FF2CH Port mode register 12 PM12 FF2DH Port mode register 13 PM13 FF30H Real time output buffer register L RTBL FF31H Real time output buffer register H RTBH FF34H R...

Page 116: ...de register 1 CSIM1 FF69H Automatic data transmit receive control register ADTC FF6AH Automatic data transmit receive address pointer ADTP FF6BH Automatic data transmit receive interval specify register ADTI FF70H Asynchronous serial interface mode register ASIM FF71H Asynchronous serial interface status register ASIS R FF72H Serial operating mode register 2 CSIM2 RW FF73H Baud rate generator cont...

Page 117: ...up resistor option register H PUOH R W FFF4H Internal expansion RAM size IXS W 0AH switching register Note3 FFF6H Key return mode register KRM 02H FFF7H Pull up resistor option register L PUOL 00H FFF8H Memory expansion mode register MM 10H FFF9H Watchdog timer mode register WDTM 00H FFFAH Oscillation stabilization time select register OSTS FFFBH Processor clock control register PCC Table 5 6 Spec...

Page 118: ...nformation is set to the PC and branched by the following addressing For details of instructions refer to 78K 0 Series User s Manual Instruction U12326E 5 3 1 Relative addressing Function The value obtained by adding 8 bit immediate data displacement value jdisp8 of an instruction code to the start address of the following instruction is transferred to the program counter PC and branched The displ...

Page 119: ...addr16 or CALLF addr11 instruction is executed The CALL addr16 and BR addr16 instruction can branch in the entire memory space The CALLF addr11 instruction branches to an area of addresses 0800H through 0FFFH Illustration In the case of CALL addr16 and BR addr16 instructions 15 0 PC 8 7 7 0 fa10 8 11 10 0 0 0 0 1 6 4 3 CALLF fa7 0 15 0 PC 8 7 7 0 CALL or BR Low Addr High Addr In the case of CALLF ...

Page 120: ...truction references an address stored in the memory table at addresses 40H through 7FH and can branch in the entire memory space Illustration 5 3 4 Register addressing Function Register pair AX contents to be specified with an instruction word are transferred to the program counter PC and branched This function is carried out when the BR AX instruction is executed Illustration 15 1 15 0 PC 7 0 Low...

Page 121: ...ister to be Specified by Implied Addressing MULU A register for multiplicand and AX register for product storage DIVUW AX register for dividend and quotient storage ADJBA ADJBS A register for storage of numeric values which become decimal correction targets ROR4 ROL4 A register for storage of digit data which undergoes digit rotation Operand format Because implied addressing can be automatically e...

Page 122: ...g operand format is executed When an 8 bit register is specified one of the eight registers is specified with 3 bits in the operation code Operand format Identifier Description r X A C B E D L H rp AX BC DE HL r and rp can be described with function names X A C B E D L H AX BC DE and HL as well as absolute names R0 to R7 and RP0 to RP3 Description example MOV A C when selecting C register as r Ope...

Page 123: ...d by the immediate data in an instruction word Operand format Identifier Description addr16 Label or 16 bit immediate data Description example MOV A 0FE00H when setting addr16 to FE00H Operation code 1 0 0 0 1 1 1 0 OP code 0 0 0 0 0 0 0 0 00H 1 1 1 1 1 1 1 0 FEH Illustration Memory 0 7 OP code saddr16 low saddr16 high ...

Page 124: ...egisters of timer event counters are mapped These SFRs can be manipulated with a short byte length and a few clocks When 8 bit immediate data is at 20H to FFH bit 8 of an effective address is set to 0 When it is at 00H to 1FH bit 8 is set to 1 Refer to Illustration on next page Operand format Identifier Description saddr Label of FE20H to FF1FH immediate data saddrp Label of FE20H to FF1FH immedia...

Page 125: ...rd This addressing is applied to the 240 byte spaces FF00H to FFCFH and FFE0H to FFFFH However the SFR mapped at FF00H to FF1FH can be accessed with short direct addressing Operand format Identifier Description sfr Special function register name sfrp 16 bit manipulatable special function register name even address only Description example MOV PM0 A when selecting PM0 FF20H as sfr Operation code 1 ...

Page 126: ...egister bank select flags RBS0 and RBS1 and register pair specify code in an instruction code This addressing can be carried out for all the memory spaces Operand format Identifier Description DE HL Description example MOV A DE when selecting DE as register pair Operation code 1 0 0 0 0 1 0 1 Illustration 15 0 8 D 7 E 0 7 7 0 A DE Memory Contents of addressed memory are transferred Memory address ...

Page 127: ...e HL register pair to be accessed is in the register bank specified by the register bank select flags RBS0 and RBS1 Addition is performed by expanding the offset data as a positive number to 16 bits A carry from the 16th bit is ignored This addressing can be carried out for all the memory spaces Operand format Identifier Description HL byte Description example MOV A HL 10H when setting byte to 10H...

Page 128: ...er to 16 bits as a positive number A carry from the 16th bit is ignored This addressing can be carried out for all the memory spaces Operand format Identifier Description HL B HL C Description example In the case of MOV A HL B Operation code 1 0 1 0 1 0 1 1 5 4 9 Stack addressing Function The stack area is indirectly addressed with the stack pointer SP contents This addressing method is automatica...

Page 129: ...ONS 6 1 Port Functions The µPD78054 and 78054Y subseries units incorporate two input ports and sixty seven input output ports Figure 6 1 shows the port configuration Every port is capable of 1 bit and 8 bit manipulations and can carry out considerably varied control operations Besides port functions the ports can also serve as on chip hardware input output pins Figure 6 1 Port Types ...

Page 130: ...ts BUSY P25 When used as an input port an on chip pull up resistor can be used by software SI0 SB0 P26 SO0 SB1 P27 SCK0 P30 TO0 P31 TO1 P32 Port 3 TO2 P33 8 bit input output port TI1 P34 Input output mode can be specified in 1 bit units TI2 P35 When used as an input port an on chip pull up resistor can be used by software PCL P36 BUZ P37 Port 4 8 bit input output port P40 to P47 Input output mode ...

Page 131: ...can be specified in 1 bit When used as an input port an on chip RD P65 units pull up resistor can be used by software WR P66 WAIT P67 ASTB Port 7 3 bit input output port Input output mode can be specified in 1 bit units When used as an input port an on chip pull up resistor can be used by software Port 12 8 bit input output port Input output mode can be specified in 1 bit units When used as an inp...

Page 132: ... output mode can be specified in 1 bit units BUSY P25 When used as an input port an on chip pull up resistor can be used by software SI0 SB0 SDA0 P26 SO0 SB1 SDA1 P27 SCK0 SCL P30 TO0 P31 TO1 P32 Port 3 TO2 P33 8 bit input output port TI1 P34 Input output mode can be specified in 1 bit units TI2 P35 When used as an input port an on chip pull up resistor can be used by software PCL P36 BUZ P37 Port...

Page 133: ...can be specified in 1 bit When used as an input port an on chip RD P65 units pull up resistor can be used by software WR P66 WAIT P67 ASTB Port 7 3 bit input output port Input output mode can be specified in 1 bit units When used as an input port an on chip pull up resistor can be used by software Port 12 8 bit input output port Input output mode can be specified in 1 bit units When used as an inp...

Page 134: ... pins can specify the input mode output mode in 1 bit units with the port mode register 0 PM0 P00 and P07 pins are input only ports When P01 to P06 pins are used as input ports an on chip pull up resistor can be used to them in 6 bit units with a pull up resistor option register L PUOL Alternate functions include external interrupt request input external count clock input to the timer and crystal ...

Page 135: ...P06 INTP6 Selector PUO0 Output Latch P01 to P06 PM01 PM06 Internal bus P00 INTP0 TI00 P07 XT1 RD Internal bus Figure 6 2 P00 and P07 Block Diagram Figure 6 3 P01 to P06 Block Diagram PUO Pull up resistor option register PM Port mode register RD Port 0 read signal WR Port 0 write signal ...

Page 136: ... P17 pins are used as input ports an on chip pull up resistor can be used to them in 8 bit units with a pull up resistor option register L PUOL Alternate functions include an A D converter analog input RESET input sets port 1 to input mode Figure 6 4 shows a block diagram of port 1 Caution A pull up resistor cannot be used for pins used as A D converter analog input Figure 6 4 P10 to P17 Block Dia...

Page 137: ... include serial interface data input output clock input output automatic transmit receive busy input and strobe output RESET input sets port 2 to input mode Figures 6 5 and 6 6 show block diagrams of port 2 Cautions 1 When used as a serial interface set the input output and output latch according to its functions For the setting method refer to Figure 16 4 Serial Operating Mode Register 0 Format a...

Page 138: ...d P27 Block Diagram PUO Pull up resistor option register PM Port mode register RD Port 2 read signal WR Port 2 write signal P ch WRPM WRPORT RD WRPUO VDD Selector PUO2 Output Latch P22 P27 PM22 PM27 Internal bus Alternate Function P22 SCK1 P27 SCK0 ...

Page 139: ... be used to them in 8 bit units with a pull up resistor option register L PUOL Alternate functions include serial interface data input output clock input output automatic transmit receive busy input and strobe output RESET input sets port 2 to input mode Figures 6 7 and 6 8 show block diagrams of port 2 Caution When used as a serial interface set the input output and output latch according to its ...

Page 140: ...RPUO VDD Selector PUO2 Output Latch P22 and P27 PM22 PM27 Internal bus Alternate Function P22 SCK1 P27 SCK0 SCL Figure 6 8 P22 and P27 Block Diagram PUO Pull up resistor option register PM Port mode register RD Port 2 read signal WR Port 2 write signal ...

Page 141: ...t mode in 1 bit units with the port mode register 3 PM3 When P30 to P37 pins are used as input ports an on chip pull up resistor can be used to them in 8 bit units with a pull up resistor option register L PUOL Alternate functions include timer input output clock output and buzzer output RESET input sets port 3 to input mode Figure 6 9 shows a block diagram of port 3 Figure 6 9 P30 to P37 Block Di...

Page 142: ... as input ports an on chip pull up resistor can be used to them in 8 bit units with pull up resistor option register L PUOL The test input flag KRIF can be set to 1 by detecting falling edges Alternate function includes address data bus function in external memory expansion mode RESET input sets port 4 to input mode Figures 6 10 and 6 11 show a block diagram of port 4 and block diagram of falling ...

Page 143: ...er 5 PM5 When P50 to P57 pins are used as input ports an on chip pull up resistor can be used to them in 8 bit units with a pull up resistor option register L PUOL Port 5 can drive LEDs directly Alternate function includes address bus function in external memory expansion mode RESET input sets port 5 to input mode Figure 6 12 shows a block diagram of port 5 Figure 6 12 P50 to P57 Block Diagram PUO...

Page 144: ...6 of pull up resistor option register L PUOL Pins P60 to P63 can drive LEDs directly Pins P64 to P67 also serve as control signal output in external memory expansion mode RESET input sets port 6 to input mode Figures 6 13 and 6 14 show block diagrams of port 6 Cautions 1 When external wait is not used in external memory expansion mode P66 can be used as an input output port 2 The value of the low ...

Page 145: ...Output Latch P60 to P63 PM60 PM63 Internal bus P60 P63 Mask Option Resistor Mask ROM products only PROM versions have no pull up resistor Figure 6 13 P60 to P63 Block Diagram PM Port mode register RD Port 6 read signal WR Port 6 write signal Figure 6 14 P64 to P67 Block Diagram PUO Pull up resistor option register PM Port mode register RD Port 6 read signal WR Port 6 write signal ...

Page 146: ...ial interface channel 2 data input output and clock input output RESET input sets the input mode Figures 6 15 and 6 16 show block diagrams of port 7 Caution When used as a serial interface set the input output and output latch according to its functions For the setting method refer to Table 19 2 Serial Interface Channel 2 Operating Mode Setting Figure 6 15 P70 Block Diagram PUO Pull up resistor op...

Page 147: ...O VDD Selector PUO7 Output Latch P71 and P72 PM71 PM72 Internal bus Alternate Function P71 SO2 TxD P72 SCK2 ASCK Figure 6 16 P71 and P72 Block Diagram PUO Pull up resistor option register PM Port mode register RD Port 7 read signal WR Port 7 write signal ...

Page 148: ...by means of port mode register 12 PM12 When pins P120 to P127 are used as input port pins an on chip pull up resistor can be used as an 8 bit unit by means of pull up resistor option register H PUOH Alternate function includes real time output RESET input sets the input mode Figure 6 17 shows a block diagram of port 12 Figure 6 17 P120 to P127 Block Diagram PUO Pull up resistor option register PM ...

Page 149: ... H PUOH Alternate function includes D A converter analog output RESET input sets the input mode Figure 6 18 shows a block diagram of port 13 Caution When only either one of the D A converter channels is used with AVREF1 VDD the other pins that are not used as analog outputs must be set as follows Set PM13 bit of the port mode register 13 PM13 to 1 input mode and connect the pin to VSS Set PM13x bi...

Page 150: ...3 are independently set with a 1 bit or 8 bit memory manipulation instruction RESET input sets registers to FFH When port pins are used as the dual function pins set the port mode register and output latch according to Table 6 5 Cautions 1 Pins P00 and P07 are input only pins 2 As port 0 has a dual function as external interrupt request input when the port function output mode is specified and the...

Page 151: ...Name P PM Input Output Pin Name Notes 1 If these ports are read out when these pins are used in the alternative function mode undefined values are read 2 When the P40 to P47 pins P50 to P57 pins and P64 to P67 pins are used for dual functions set the function by the memory extension mode register MM Cautions 1 When not using external wait in the external memory extension mode the P66 pin can be us...

Page 152: ...10 PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20 PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 PM57 PM56 PM55 PM54 PM53 PM52 PM51 PM50 PM6 PM7 FF26H FF27H FFH FFH R W R W PM67 PM66 PM65 PM64 PM63 PM62 PM61 PM60 1 1 1 1 1 PM72 PM71 PM70 PM05 PM04 PM12 PM13 PMmn Pmn Pin Input Output Mode Selection m 0 3 5 7 12 13 n 0 7 0 1 Output mode output buffer ON Input mode output buffer OFF FF2CH FF2DH FFH FFH R W R W PM1...

Page 153: ...ip pull up resistor use has been specified with PUOH PUOL No on chip pull up resistors can be used to the bits set to the output mode or to the bits used as an analog input pin irrespective of PUOH or PUOL setting PUOH and PUOL are set with a 1 bit or 8 bit memory manipulation instruction RESET input sets this register to 00H Cautions 1 P00 and P07 pins do not incorporate a pull up resistor 2 When...

Page 154: ...etting port 4 input output MM also sets the wait count and external expansion area 0 0 PW1 0 MM FFF8H 10H R W 7 6 5 4 3 2 Symbol Address After Reset R W 1 PW0 MM2 MM1 MM0 0 MM2 MM1 MM0 0 0 0 0 0 1 0 1 1 1 0 0 1 0 1 1 1 1 Other than above Setting prohibited Single chip Memory Expansion Mode Selection Single chip mode 256 byte mode 4 Kbyte mode 16 Kbyte mode Full Note address mode Memory expansion m...

Page 155: ...Standby mode release disabled Address After Reset R W 02H R W 4 Key return mode register KRM This register sets enabling disabling of standby function release by a key return signal falling edge detection of port 4 KRM is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets KRM to 02H Figure 6 22 Key Return Mode Register Format Caution When falling edge detection of port4 is ...

Page 156: ... the output buffer is OFF the pin status does not change Once data is written to the output latch it is retained until data is written to the output latch again Caution In the case of 1 bit memory manipulation instruction although a single bit is manipulated the port is accessed as an 8 bit unit Therefore on a port with a mixture of input and output pins the output latch contents for pins specifie...

Page 157: ... change Caution In the case of 1 bit memory manipulation instruction although a single bit is manipulated the port is accessed as an 8 bit unit Therefore on a port with a mixture of input and output pins the output latch contents for pins specified as input are undefined even for bits other than the manipulated bit 6 5 Selection of Mask Option The following mask option is provided in mask ROM vers...

Page 158: ...158 MEMO ...

Page 159: ...bsystem clock oscillator The circuit oscillates at a frequency of 32 768 kHz Oscillation cannot be stopped If the subsystem clock oscillator is not used not using the internal feedback resistance can be set by the processor clock control register PCC This enables to decrease power consumption in the STOP mode 7 2 Clock Generator Configuration The clock generator consists of the following hardware ...

Page 160: ...Control Circuit To INTP0 Sampling Clock 2 fXX 22 fXX 2 3 fXX 24 fXX Prescaler Clock to Peripheral Hardware Prescaler Oscillation Mode Selection Register Watch Timer Clock Output Function fXX CPU Clock fCPU Wait Control Circuit Scaler Selector fX fXT 2 fX MCS Processor Clock Control Register 2 fXT PCC0 3 Selector 1 2 Figure 7 1 Block Diagram of Clock Generator ...

Page 161: ...PCC Oscillation mode selection register OSMS 1 Processor clock control register PCC The PCC sets whether to use CPU clock selection the ratio of division main system clock oscillator operation stop and subsystem clock oscillator internal feedback resistor The PCC is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets the PCC to 04H Figure 7 2 Subsystem Clock Feedback Resisto...

Page 162: ... Feedback Resistor Selection MCC 0 1 Oscillation possible Oscillation stopped Main System Clock Oscillation Control Note 2 R W R W R W R fx 2 fx 22 fx 23 fx 2 4 fx fx 2 2 fx 23 fx 24 fx 2 5 fx 2 MCS 1 MCS 0 0 1 Figure 7 3 Processor Clock Control Register Format Notes 1 Bit 5 is Read Only 2 When the CPU is operating on the subsystem clock MCC should be used to stop the main system clock oscillation...

Page 163: ... instruction execution time are as shown in Table 7 2 Table 7 2 Relationship between CPU Clock and Minimum Instruction Execution Time CPU Clock fCPU Minimum Instruction Execution Time 2 fCPU fX 0 4 µs fX 2 0 8 µs fX 22 1 6 µs fX 23 3 2 µs fX 24 6 4 µs fX 25 12 8 µs fXT 2 122 µs Remarks 1 fX 5 0 MHz fXT 32 768 kHz 2 fX Main system clock oscillation frequency 3 fXT Subsystem clock oscillation freque...

Page 164: ...scillation Mode Selection Register Format Cautions 1 The main system clock cycle is longer by up to 2 fx only when writing data to OSMS including when writing the same data that was written previously as shown in Figure 7 5 This causes a temporary error in the count clock cycle of timers in the peripheral hardware that operates with the main system clock In addition when the oscillation mode is ch...

Page 165: ... In this case input a clock signal to the X1 pin and an antiphase clock signal to the X2 pin Figure 7 6 shows an external circuit of the main system clock oscillator Figure 7 6 External Circuit of Main System Clock Oscillator a Crystal and ceramic oscillation b External clock Caution Do not execute the STOP instruction or do not set MCC bit 7 of processor clock control register PCC to 1 if an exte...

Page 166: ... XT2 XT1 32 768 kHz IC Cautions 1 When using a main system clock oscillator and a subsystem clock oscillator carry out wiring in the broken line area in Figures 7 6 and 7 7 to prevent any effects from wiring capacities Minimize the wiring length Do not allow wiring to intersect with other signal conductors Do not allow wiring to come near changing high current Set the potential of the grounding po...

Page 167: ...s are fetched Remark When using a subsystem clock replace X1 and X2 with XT1 and XT2 respectively Also insert resistors in series on the XT2 side Cautions 2 In Figure 7 8 f XT2 and X1 are wired in parallel Thus the cross talk noise of X1 may increase with XT2 resulting in malfunctioning To prevent that from occurring it is recommended to wire XT2 and X1 so that they are not in parallel and to corr...

Page 168: ...ons and clock operations connect the XT1 and XT2 pins as follows XT1 Connect to VDD XT2 Leave open In this state however some current may leak via the internal feedback resistor of the subsystem clock oscillator when the main system clock stops To suppress the leakage current disconnect the above internal feedback resistor by using the bit 6 FRC of the processor clock control register PCC In this ...

Page 169: ...lable In a system where the subsystem clock is not used the current consumption in the STOP mode can be further reduced by specifying with bit 6 FRC of the PCC not to use the feedback resistor d The PCC can be used to select the subsystem clock and to operate the system with low current consumption 122 µs when operated at 32 768 kHz e With the subsystem clock selected main system clock oscillation...

Page 170: ...ntee instruction execution speed depends on the power supply voltage the minimum instruction execution time can be changed by bits 0 to 2 PCC0 to PCC2 of the PCC b If bit 7 MCC of the PCC is set to 1 when operated with the main system clock the main system clock oscillation does not stop When bit 4 CSS of the PCC is set to 1 and the operation is switched to subsystem clock operation CLS 1 after th...

Page 171: ...bits 0 to 2 PCC0 to PCC2 of the PCC b Watchdog timer counting stops Caution Do not execute the STOP instruction while the subsystem clock is in operation 7 6 Changing System Clock and CPU Clock Settings 7 6 1 Time required for switchover between system clock and CPU clock The system clock and CPU clock can be switched over by means of bits 0 to 2 PCC0 to PCC2 and bit 4 CSS of the processor clock c...

Page 172: ...ons fX 64fXT instruction 3 instructions MSC 1 MSC 0 Set Values After Switchover Set Values before Switchover CSS CSS CSS CSS CSS 1 instruction 1 instruction 1 instruction 1 instruction 1 instruction 1 instruction 1 instruction CSS 1 instruction 1 instruction Remarks 1 One instruction is the minimum instruction execution time with the pre switchover CPU clock 2 MCS Oscillation mode selection regist...

Page 173: ...clock 12 8 µs when operated at 5 0 MHz 2 After the lapse of a sufficient time for the VDD voltage to increase to enable operation at maximum speeds the processor clock control register PCC and oscillation mode selection register OSMS are rewritten and the maximum speed operation is carried out 3 Upon detection of a decrease of the VDD voltage due to an interrupt request signal the main system cloc...

Page 174: ...174 MEMO ...

Page 175: ...e waves with any selected frequency Two 8 bit timer event counters can be used as one 16 bit timer event counter See CHAPTER 9 8 BIT TIMER EVENT COUNTERS 1 AND 2 3 Watch timer TM3 This timer can set a flag every 0 5 sec and simultaneously generates interrupt requests at the preset time intervals See CHAPTER 10 WATCH TIMER 4 Watchdog timer WDTM WDTM can perform the watchdog timer function or genera...

Page 176: ...e output One shot pulse output Interrupt source Test input Notes 1 Watch timer can perform both watch timer and interval timer functions at the same time 2 Watchdog timer can perform either the watchdog timer function or the interval timer function 3 When capture compare registers CR00 CR01 are specified as compare registers Function Operating mode Watch Timer Watchdog Timer 16 bit Timer 8 bit Tim...

Page 177: ...ycle 2 1 fX 216 1 fX 1 fX 400 ns 13 1 ms 200 ns 2 1 fX 22 1 fX 216 1 fX 217 1 fX 1 fX 2 1 fX 400 ns 800 ns 13 1 ms 26 2 ms 200 ns 400 ns 22 1 fX 23 1 fX 217 1 fX 218 1 fX 2 1 fX 22 1 fX 800 ns 1 6 µs 26 2 ms 52 4 ms 400 ns 800 ns 23 1 fX 24 1 fX 218 1 fX 219 1 fX 22 1 fX 23 1 fX 1 6 µs 3 2 µs 52 4 ms 104 9 ms 800 ns 1 6 µs 2 watch timer output cycle 216 watch timer output cycle Watch timer output ...

Page 178: ... 217 1 fX 1 fX 2 1 fX 400 ns 800 ns 13 1 ms 26 2 ms 200 ns 400 ns 22 1 fX 23 1 fX 217 1 fX 218 1 fX 2 1 fX 22 1 fX 800 ns 1 6 µs 26 2 ms 52 4 ms 400 ns 800 ns 23 1 fX 24 1 fX 218 1 fX 219 1 fX 22 1 fX 23 1 fX 1 6 µs 3 2 µs 52 4 ms 104 9 ms 800 ns 1 6 µs 2 watch timer output cycle 216 watch timer output cycle Watch timer output edge cycle Remarks 1 fX Main system clock oscillation frequency 2 MCS O...

Page 179: ...of Interrupt Function TCL06 TCL05 TCL04 Timer Clock Selection Register 0 3 Internal bus Capture Compare Control Register 0 CRC02 CRC01 CRC00 Selector TI01 P01 INTP1 INTTM3 2fXX fXX fXX 2 fXX 22 Selector 16 Bit Capture Compare Control Register CR01 Internal Bus 16 Bit Capture Compare Control Register CR00 Clear Match Clear Circuit TMC03 TMC02 TMC01 OVF0 OSPTOSPETOC04 LVS0 LVR0TOC01TOE0 16 Bit Timer...

Page 180: ...tput Control Circuit Edge Detection Circuit TI00 P00 INTP0 OSPT 16 Bit Timer Output Control Register OSPE TOC04 LVS0 LVR0 TOC01 TOE0 Selector Selector INV S R Q 3 Level Inversion CRC02 INTTM01 CRC00 INTTM00 One Shot Pulse Output Control Circuit 2 ES11 ES10 External Interrupt Mode Register 0 16 Bit Timer Mode Control Register TMC03 TMC02 TMC01 P30 Output Latch PM30 Port Mode Register 3 TO0 P30 Inte...

Page 181: ...ising edge 0 1 Rising edge Falling edge 1 0 Setting prohibited 1 1 Both rising and falling edges No capture operation CR00 is set by a 16 bit memory manipulation instruction After RESET input the value of CR00 is undefined Cautions 1 Set the data of PWM 14 bits to the higher 14 bits of CR00 At this time clear the lower 2 bits to 00 2 Set a value other than 0000H to CR00 When the event counter func...

Page 182: ...iously set is lost 8 4 16 Bit Timer Event Counter Control Registers The following seven types of registers are used to control the 16 bit timer event counter Timer clock select register 0 TCL0 16 bit timer mode control register TMC0 Capture compare control register 0 CRC0 16 bit timer output control register TOC0 Port mode register 3 PM3 External interrupt mode register 0 INTM0 Sampling clock sele...

Page 183: ...ing prohibited fX 5 0 MHz 0 1 0 fXX fX 5 0 MHz fX 2 2 5 MHz 0 1 1 fXX 2 fX 2 2 5 MHz fX 2 2 1 25 MHz 1 0 0 fXX 2 2 fX 2 2 1 25 MHz fX 2 3 625 kHz 1 1 1 Watch timer output INTTM 3 MCS 1 16 Bit Timer Register Count Clock Selection MCS 0 Other than above Setting prohibited CLOE 1 Output enabled PCL Output Control 0 Output disabled Figure 8 3 Timer Clock Selection Register 0 Format Cautions 1 The TI00...

Page 184: ...theses apply to operation with fX 5 0 MHz of fXT 32 768 kHz 2 16 bit timer mode control register TMC0 This register sets the 16 bit timer operating mode the 16 bit timer register clear mode and output timing and detects an overflow TMC0 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets TMC0 value to 00H Caution The 16 bit timer register starts operation at the moment a ...

Page 185: ...M0 and CR01 Match between TM0 and CR00 match between TM0 and CR01 or TI00 valid edge Clear start on TI00 valid edge Clear start on match between TM0 and CR00 Generated on match between TM0 and CR00 or match between TM0 and CR01 Figure 8 4 16 Bit Timer Mode Control Register Format Remarks 1 TO0 16 bit timer event counter output pin 2 TI00 16 bit timer event counter input pin 3 TM0 16 bit timer regi...

Page 186: ...de Selection Operates as compare register Operates as capture register 0 1 Cautions 1 Timer operation must be stopped before setting CRC0 2 When clear start mode on a match between TM0 and CR00 is selected with the 16 bit timer mode control register CR00 should not be specified as a capture register 4 16 bit timer output control register TOC0 This register controls the operation of the 16 bit time...

Page 187: ...0 0 No change 0 1 Timer output F F reset 0 1 0 Timer output F F set 1 1 1 Setting prohibited TOC04 Timer output F F control by match of CR01 and TM0 0 Inversion operation disabled 1 Inversion operation enabled OSPE One Shot Pulse Output Control 0 Continuous pulse output 1 One shot pulse output OSPT Control of One Shot Pulse Output Trigger by Software 0 One shot pulse trigger not used 1 One shot pu...

Page 188: ...election n 0 to 7 0 Output mode output buffer ON 1 Input mode output buffer OFF 5 Port mode register 3 PM3 This register sets port 3 input output in 1 bit units When using the P30 TO0 pin for timer output set PM30 and output latch of P30 to 0 PM3 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM3 value to FFH Figure 8 7 Port Mode Register 3 Format ...

Page 189: ...sing edges 1 ES31 INTP2 Valid Edge Selection ES30 0 Falling edge 0 0 Rising edge 1 1 Setting prohibited 0 1 Both falling and rising edges 1 6 External interrupt mode register 0 INTM0 This register is used to set INTP0 to INTP2 valid edges INTM0 is set with an 8 bit memory manipulation instruction RESET input sets INTM0 value to 00H Figure 8 8 External Interrupt Mode Register 0 Format Caution Befoe...

Page 190: ...eception is carried out using INTP0 digital noise is removed with sampling clock SCS is set with an 8 bit memory manipulation instruction RESET input sets SCS value to 00H Figure 8 9 Sampling Clock Select Register Format Caution fXX 2N is the clock supplied to the CPU and fXX 25 fXX 26 and fXX 27 are clocks supplied to peripheral hardware fXX 2N is stopped in HALT mode Remarks 1 N Value set in bit...

Page 191: ...tinues with the TM0 value cleared to 0 and the interrupt request signal INTTM00 is generated Count clock of the 16 bit timer event counter can be selected with bits 4 to 6 TCL04 to TCL06 of the timer clock select register 0 TCL0 For the operation when the value of the compare register is changed during the timer count operation refer to 8 6 16 Bit Timer Event Counter Precautions 3 Figure 8 10 Cont...

Page 192: ...r Circuit INTTM00 Figure 8 11 Interval Timer Configuration Diagram Figure 8 12 Interval Timer Operation Timings t Count Clock TM0 Count Value CR00 INTTM00 TO0 Interval Time Interval Time Interval Time 0000 0001 N 0000 0001 N 0000 0001 N Count Start Clear Clear N N N N Interrupt Request Acknowledge Interrupt Request Acknowledge Remark Interval time N 1 t N 0001H to FFFFH ...

Page 193: ...put operations Setting the 16 bit timer mode control register TMC0 capture compare control register 0 CRC0 and the 16 bit timer output control register TOC0 as shown in Figure 8 13 allows operation as PWM output Pulses with the duty rate determined by the value set in 16 bit capture compare register 00 CR00 beforehand are output from the TO0 P30 pin Set the active level width of the PWM pulse to t...

Page 194: ... 0 1 0 0 0 0 0 0 OVF0 TMC01 TMC02 TMC03 PWM mode Figure 8 13 Control Register Settings for PWM Output Operation a 16 bit timer mode control register TMC0 b Capture compare control register 0 CRC0 c 16 bit timer output control register TOC0 Remark 0 1 Setting 0 or 1 allows another function to be used simultaneously with PWM output See the description of the respective control registers for details ...

Page 195: ...can be converted to an analog voltage and used for electronic tuning and D A converter applications etc The analog output voltage VAN used for D A conversion with the configuration shown in Figure 8 14 is as follows VAN VREF 216 VREF External switching circuit reference voltage Figure 8 14 Example of D A Converter Configuration with PWM Output capture compare register 00 CR00 value Figure 8 15 sho...

Page 196: ...ode control register TMC0 and capture compare control register 0 CRC0 as shown in Figure 8 16 allows operation as PPG Programmable Pulse Generator output In the PPG output operation square waves are output from the TO0 P30 pin with the pulse width and the cycle that correspond to the count values set beforehand in 16 bit capture compare register 01 CR01 and in 16 bit capture compare register 00 CR...

Page 197: ...dge specified by external interrupt mode register 0 INTM0 is input to the TI00 P00 pin the value of TM0 is taken into 16 bit capture compare register 01 CR01 and an external interrupt request signal INTP0 is set Any of three edge specifications can be selected rising falling or both edges by means of bits 2 and 3 ES10 and ES11 of INTM0 For valid edge detection sampling is performed at the interval...

Page 198: ...00 INTP00 Count Clock TM0 Count Value TI00 Pin Input CR01 Captured Value INTP0 OVF0 0000 0001 D0 D1 FFFF 0000 D2 D3 D0 D1 D2 D3 D1 D0 t 10000H D1 D2 t D3 D2 t t Figure 8 18 Configuration Diagram for Pulse Width Measurement by Free Running Counter Figure 8 19 Timing of Pulse Width Measurement Operation by Free Running Counter and One Capture Register with Both Edges Specified ...

Page 199: ...and 5 ES20 and ES21 of INTM0 is input to the TI01 P01 pin the value of TM0 is taken into 16 bit capture compare register 00 CR00 and an external interrupt request signal INTP1 is set Any of three edge specifications can be selected rising falling or both edges as the valid edges for the TI00 P00 pin and the TI01 P01 pin by means of bits 2 and 3 ES10 and ES11 and bits 4 and 5 ES20 and ES21 of INTM0...

Page 200: ...nput CR01 Captured Value INTP0 TI01 Pin Input t CR00 Captured Value INTP1 OVF0 D1 D0 t 10000H D1 D2 t 10000H D1 D2 1 t D3 D2 t 0000 0001 D0 D1 0000 D3 D2 FFFF D0 D1 D3 D2 D1 Figure 8 21 Timing of Pulse Width Measurement Operation with Free Running Counter with Both Edges Specified ...

Page 201: ...into CR01 the value of TM0 is taken into 16 bit capture compare register 00 CR00 Either of two edge specifications can be selected rising or falling as the valid edges for the TI00 P00 pin by means of bits 2 and 3 ES10 and ES11 of INTM0 For TI00 P00 pin valid edge detection sampling is performed at the interval selected by means of the sampling clock selection register SCS and a capture operation ...

Page 202: ...00 Pin Input CR01 Captured Value CR00 Captured Value INTP0 OVF0 D1 D0 t 10000H D1 D2 t D3 D2 t D1 D3 D0 D2 D3 D2 0000 FFFF D1 D0 0000 0001 t Figure 8 23 Timing of Pulse Width Measurement Operation by Free Running Counter and Two Capture Registers with Rising Edge Specified ...

Page 203: ...lid edge detection the sampling is performed by a cycle selected by the sampling clock selection register SCS and a capture operation is only performed when a valid level is detected twice thus eliminating noise with a short pulse width Caution If the valid edge of TI00 P00 is specified to be both rising and falling edge the 16 bit capture compare register 00 CR00 cannot perform the capture operat...

Page 204: ...eared to 0 and the interrupt request signal INTTM00 is generated Set the value other than 0000H to CR00 1 pulse count operation cannot be performed The rising edge the falling edge or both edges can be selected with bits 2 and 3 ES10 and ES11 of INTM0 Because operation is carried out only after the valid edge is detected twice by sampling at the interval selected with the sampling clock select reg...

Page 205: ...ompare Register 00 CR00 Clear INTTM00 INTP0 16 Bit Timer Register TM0 16 Bit Capture Compare Register 01 CR01 Internal Bus TI00 Valid Edge OVF0 Figure 8 27 External Event Counter Configuration Diagram Figure 8 28 External Event Counter Operation Timings with Rising Edge Specified Caution When reading the external event counter count value TM0 should be read ...

Page 206: ... selected frequency at intervals of the count value preset to the 16 bit capture compare register 00 CR00 The TO0 P30 pin output status is reversed at intervals of the count value preset to CR00 by setting bit 0 TOE0 and bit 1 TOC01 of the 16 bit timer output control register TOC0 to 1 This enables a square wave with any selected frequency to be output Figure 8 29 Control Register Settings in Squa...

Page 207: ...I00 input edge cycle 2 1 fX 216 1 fX 1 fX 400 ns 13 1 ms 200 ns 2 1 fX 22 1 fX 216 1 fX 217 1 fX 1 fX 2 1 fX 400 ns 800 ns 13 1 ms 26 2 ms 200 ns 400 ns 22 1 fX 23 1 fX 217 1 fX 218 1 fX 2 1 fX 22 1 fX 800 ns 1 6 µs 26 2 ms 52 4 ms 400 ns 800 ns 23 1 fX 24 1 fX 218 1 fX 219 1 fX 22 1 fX 23 1 fX 1 6 µs 3 2 µs 52 4 ms 104 9 ms 800 ns 1 6 µs 2 watch timer output cycle 216 watch timer output cycle Wat...

Page 208: ...oftware a one shot pulse is output from the TO0 P30 pin By setting 1 in OSPT the 16 bit timer event counter is cleared and started and output is activated by the count value set beforehand in 16 bit capture compare register 01 CR01 Thereafter output is inactivated by the count value set beforehand in 16 bit capture compare register 00 CR00 TM0 continues to operate after one shot pulse is output To...

Page 209: ... Output 0000 0001 N N 1 0000 N 1 N M 1 M 0000 0001 0002 N M N M N M N M Set 0CH to TMC0 TM0 count start Figure 8 32 Timing of One Shot Pulse Output Operation Using Software Trigger Caution The 16 bit timer register starts operation at the moment a value other than 0 0 0 operation stop mode is set to TMC01 to TMC03 respectively ...

Page 210: ...ng falling or both edges as the valid edges for the TI00 P00 pin by means of bits 2 and 3 ES10 and ES11 of external interrupt mode register 0 INTM0 When a valid edge is input to the TI00 P00 pin the 16 bit timer event counter is cleared and started and output is activated by the count values set beforehand in 16 bit capture compare register 01 CR01 Thereafter output is inactivated by the count val...

Page 211: ...0000 0001 0000 N N 1 N 2 M 2 M 1 M M 1 M 2 M 3 N M N M N M N M Set 08H to TMC0 TM0 count start Figure 8 34 Timing of One Shot Pulse Output Operation Using External Trigger With Rising Edge Specified Caution The 16 bit timer register starts operation at the moment a value other than 0 0 0 operation stop mode is set to TMC01 to TMC03 respectively ...

Page 212: ... 2 16 bit compare register setting Set a value other than 0000H to the 16 bit capture compare register 00 CR00 Thus when using the 16 bit capture compare register as event counter one pulse count operation cannot be carried out 3 Operation after compare register change during timer count operation If the value after the 16 bit capture compare register CR00 is changed is smaller than that of the 16...

Page 213: ... Data Retention Timing 5 Valid edge setting Set the valid edge of the TI00 P00 INTP0 pin after setting bits 1 to 3 TMC01 to TMC03 of the 16 bit timer mode control register TMC0 to 0 0 and 0 respectively and then stopping timer operation Valid edge is set with bits 2 and 3 ES10 and ES11 of the external interrupt mode register 0 INTM0 6 Re trigger of one shot pulse a One shot pulse output using soft...

Page 214: ...TM00 FFFFH FFFEH FFFFH 0000H 0001H 7 Operation of OVF0 flag OFV0 flag is set to 1 in the following case The clear start mode on match between TM0 and CR00 is selected CR00 is set to FFFFH When TM0 is counted up from FFFFH to 0000H Figure 8 38 Operation Timing of OVF0 Flag ...

Page 215: ...l 8 bit timer event counters to be used separately the 8 bit timer event counter mode and the other is a mode for the 8 bit timer event counter to be used as 16 bit timer event counter the 16 bit timer event counter mode 9 1 1 8 bit timer event counter mode The 8 bit timer event counters 1 and 2 TM1 and TM2 have the following functions Interval timer External event counter Square wave output ...

Page 216: ...25 1 fX 3 2 µs 6 4 µs 819 2 µs 1 64 ms 3 2 µs 6 4 µs 25 1 fX 26 1 fX 213 1 fX 214 1 fX 25 1 fX 26 1 fX 6 4 µs 12 8 µs 1 64 ms 3 28 ms 6 4 µs 12 8 µs 26 1 fX 27 1 fX 214 1 fX 215 1 fX 26 1 fX 27 1 fX 12 8 µs 25 6 µs 3 28 ms 6 55 ms 12 8 µs 25 6 µs 27 1 fX 28 1 fX 215 1 fX 216 1 fX 27 1 fX 28 1 fX 25 6 µs 51 2 µs 6 55 ms 13 1 ms 25 6 µs 51 2 µs 28 1 fX 29 1 fX 216 1 fX 217 1 fX 28 1 fX 29 1 fX 51 2 ...

Page 217: ...µs 24 1 fX 25 1 fX 212 1 fX 213 1 fX 24 1 fX 25 1 fX 3 2 µs 6 4 µs 819 2 µs 1 64 ms 3 2 µs 6 4 µs 25 1 fX 26 1 fX 213 1 fX 214 1 fX 25 1 fX 26 1 fX 6 4 µs 12 8 µs 1 64 ms 3 28 ms 6 4 µs 12 8 µs 26 1 fX 27 1 fX 214 1 fX 215 1 fX 26 1 fX 27 1 fX 12 8 µs 25 6 µs 3 28 ms 6 55 ms 12 8 µs 25 6 µs 27 1 fX 28 1 fX 215 1 fX 216 1 fX 27 1 fX 28 1 fX 25 6 µs 51 2 µs 6 55 ms 13 1 ms 25 6 µs 51 2 µs 28 1 fX 29...

Page 218: ...3 2 µs 24 1 fX 25 1 fX 220 1 fX 221 1 fX 24 1 fX 25 1 fX 3 2 µs 6 4 µs 209 7 ms 419 4 ms 3 2 µs 6 4 µs 25 1 fX 26 1 fX 221 1 fX 222 1 fX 25 1 fX 26 1 fX 6 4 µs 12 8 µs 419 4 ms 838 9 ms 6 4 µs 12 8 µs 26 1 fX 27 1 fX 222 1 fX 223 1 fX 26 1 fX 27 1 fX 12 8 µs 25 6 µs 838 9 ms 1 7 s 12 8 µs 25 6 µs 27 1 fX 28 1 fX 223 1 fX 224 1 fX 27 1 fX 28 1 fX 25 6 µs 51 2 µs 1 7 s 3 4 s 25 6 µs 51 2 µs 28 1 fX ...

Page 219: ...04 9 ms 209 7 ms 1 6 µs 3 2 µs 24 1 fX 25 1 fX 220 1 fX 221 1 fX 24 1 fX 25 1 fX 3 2 µs 6 4 µs 209 7 ms 419 4 ms 3 2 µs 6 4 µs 25 1 fX 26 1 fX 221 1 fX 222 1 fX 25 1 fX 26 1 fX 6 4 µs 12 8 µs 419 4 ms 838 9 ms 6 4 µs 12 8 µs 26 1 fX 27 1 fX 222 1 fX 223 1 fX 26 1 fX 27 1 fX 12 8 µs 25 6 µs 838 9 ms 1 7 s 12 8 µs 25 6 µs 27 1 fX 28 1 fX 223 1 fX 224 1 fX 27 1 fX 28 1 fX 25 6 µs 51 2 µs 1 7 s 3 4 s ...

Page 220: ... 8 Bit Timer Event Counters 1 and 2 Configurations Item Configuration Timer register 8 bits 2 TM1 TM2 Register Compare register 8 bits 2 CR10 CR20 Timer output 2 TO1 TO2 Timer clock select register 1 TCL1 8 bit timer mode control register 1 TMC1 8 bit timer output control register TOC1 Port mode register 3 PM3 Note Note Refer to Figure 6 9 Block Diagram of P30 to P37 Control register ...

Page 221: ...XX 2 fXX 2 9 fXX 2 11 TI1 P33 fXX 2 fXX 2 9 fXX 2 11 TI2 P34 4 TCL 17 TCL 16 TCL 15 TCL 14 TCL 13 TCL 12 TCL 11 TCL 10 Timer Clock Select Register 1 8 Bit Timer Mode Control Register TMC12 TCE2 TCE1 Internal Bus LVS2 LVR2 TOC 15 TOE2LVS1 LVR1 TOC 11 TOE1 4 8 Bit Timer Register 2 TM2 8 Bit Timer Event Counter Output Control Circuit 8 Bit Timer Output Control Register 8 Bit Timer Event Counter Outpu...

Page 222: ...n output control circuit Figure 9 3 Block Diagram of 8 Bit Timer Event Counter Output Control Circuit 2 Remarks 1 The section in the broken line is an output control circuit 2 fSCK Serial clock frequency LVR2 LVS2 TOC15 INTTM2 R S INV Level F F LV2 fSCK P32 Output Latch PM32 TOE2 TO2 P32 Q LVR1 LVS1 TOC11 INTTM1 R S INV Q P31 Output Latch TOE1 PM31 TO1 P31 Level F F LV1 ...

Page 223: ...RESET input makes CR10 and CR20 undefined Caution When using the compare register as 16 bit timer event counter be sure to set data after stopping timer operation 2 8 bit timer registers 1 2 TM1 TM2 These are 8 bit registers to count count pulses When TM1 and TM2 are used in the 8 bit timer 2 channel mode they are read with an 8 bit memory manipulation instruction When TM1 and TM2 are used as 16 b...

Page 224: ...kHz fX 2 5 156 kHz 1 0 1 1 fXX 2 5 fX 2 5 156 kHz fX 2 6 78 1 kHz 1 1 0 0 fXX 2 6 fX 2 6 78 1 kHz fX 2 7 39 1 kHz 1 1 0 1 fXX 2 7 fX 2 7 39 1 kHz fX 2 8 19 5 kHz 1 1 1 0 fXX 2 8 fX 2 8 19 5 kHz fX 2 9 9 8 kHz 1 1 1 1 fXX 2 9 fX 2 9 9 8 kHz fX 2 10 4 9 kHz MCS 1 8 Bit Timer Register 1 Count Clock Selection MCS 0 Other than above Setting prohibited fXX 2 11 fX 2 11 2 4 kHz fX 2 12 1 2 kHz TCL17 TCL1...

Page 225: ...1 Format Cautions 1 Switch the operating mode after stopping timer operation 2 When used as 16 bit timer register TCE1 should be used for control enable stop 0 1 2 3 4 5 6 7 Symbol TCE1 FF49H 00H R W Address After Reset R W TCE2 TMC12 0 0 0 0 0 TMC1 TCE1 8 Bit Timer Register 1 Operation Control 0 Operation stop TM1 clear to 0 1 Operation enable TCE2 8 Bit Timer Register 2 Operation Control Operati...

Page 226: ... TOE1 TOC11 LVR1 LVS1 TOE2 TOC15 LVR2 LVS2 TOC1 FF4FH 00H R W Address After Reset R W TOE1 8 Bit Timer Event Counter 1 Outptut Control 0 Output disable port mode 1 Output enable TOC11 8 Bit Timer Event Counter 1 Timer Output F F Control 0 Inverted operation disable 1 Inverted operation enable LVS1 LVR1 8 Bit Timer Event Counter 1 Timer Output F F Status Set 0 0 Unchanged 0 1 Timer output F F reset...

Page 227: ...31 PM32 and output latches of P31 and P32 to 0 PM3 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM3 to FFH Figure 9 7 Port Mode Register 3 Format 0 1 2 3 4 5 6 7 Symbol PM30 FF23H FFH R W Address After Reset R W PM31 PM32 PM33 PM34 PM35 PM36 PM37 PM3 PM3n P3n Pin Input Output Mode Selection n 0 to 7 0 Output mode output buffer ON 1 Input mode output buffer OFF ...

Page 228: ...to 0 and the interrupt request signals INTTM1 and INTTM2 are generated Count clock of TM1 can be selected with bits 0 to 3 TCL10 to TCL13 of the timer clock select register 1 TCL1 Count clock of TM2 can be selected with bits 4 to 7 TCL14 to TCL17 of the timer clock select register 1 TCL1 For the operation when the value of the compare register is changed during the timer count operation refer to 9...

Page 229: ... 25 1 fX 26 1 fX 6 4 µs 12 8 µs 1 64 ms 3 28 ms 6 4 µs 12 8 µs 26 1 fX 27 1 fX 214 1 fX 215 1 fX 26 1 fX 27 1 fX 12 8 µs 25 6 µs 3 28 ms 6 55 ms 12 8 µs 25 6 µs 27 1 fX 28 1 fX 215 1 fX 216 1 fX 27 1 fX 28 1 fX 25 6 µs 51 2 µs 6 55 ms 13 1 ms 25 6 µs 51 2 µs 28 1 fX 29 1 fX 216 1 fX 217 1 fX 28 1 fX 29 1 fX 51 2 µs 102 4 µs 13 1 ms 26 2 ms 51 2 µs 102 4 µs 29 1 fX 210 1 fX 217 1 fX 218 1 fX 29 1 f...

Page 230: ...5 1 fX 26 1 fX 6 4 µs 12 8 µs 1 64 ms 3 28 ms 6 4 µs 12 8 µs 26 1 fX 27 1 fX 214 1 fX 215 1 fX 26 1 fX 27 1 fX 12 8 µs 25 6 µs 3 28 ms 6 55 ms 12 8 µs 25 6 µs 27 1 fX 28 1 fX 215 1 fX 216 1 fX 27 1 fX 28 1 fX 25 6 µs 51 2 µs 6 55 ms 13 1 ms 25 6 µs 51 2 µs 28 1 fX 29 1 fX 216 1 fX 217 1 fX 28 1 fX 29 1 fX 51 2 µs 102 4 µs 13 1 ms 26 2 ms 51 2 µs 102 4 µs 29 1 fX 210 1 fX 217 1 fX 218 1 fX 29 1 fX ...

Page 231: ...valid edge specified with the timer clock select register TCL1 is input Either the rising or falling edge can be selected When the TM1 and TM2 counted values match the values of 8 bit compare registers CR10 and CR20 TM1 and TM2 are cleared to 0 and the interrupt request signals INTTM1 and INTTM2 are generated Figure 9 9 External Event Counter Operation Timings with Rising Edge Specified Remark N 0...

Page 232: ... ns 1 6 µs 204 8 µs 409 6 µs 800 ns 1 6 µs 23 1 fX 24 1 fX 211 1 fX 212 1 fX 23 1 fX 24 1 fX 1 6 µs 3 2 µs 409 6 µs 819 2 µs 1 6 µs 3 2 µs 24 1 fX 25 1 fX 212 1 fX 213 1 fX 24 1 fX 25 1 fX 3 2 µs 6 4 µs 819 2 µs 1 64 ms 3 2 µs 6 4 µs 25 1 fX 26 1 fX 213 1 fX 214 1 fX 25 1 fX 26 1 fX 6 4 µs 12 8 µs 1 64 ms 3 28 ms 6 4 µs 12 8 µs 26 1 fX 27 1 fX 214 1 fX 215 1 fX 26 1 fX 27 1 fX 12 8 µs 25 6 µs 3 28...

Page 233: ...10 Square Wave Output Operation Timing Note The initial value of TO1 pin output can be set with the bits 2 and 3 LVR1 LVS1 of 8 bit timer output control register TOC1 Count Clock TM1 Count Value CR10 INTTM1 TO1 Pin OutputNote 00 01 02 N 1 N 00 01 02 N 1 N 00 N ...

Page 234: ...bit timer register 2 TM2 and CR20 values match counting continues with the TM1 and TM2 values cleared to 0 and the interrupt request signal INTTM2 is generated For the timing of interval timer operation refer to Figure 9 11 The count clock is selected with bits 0 to 3 TCL10 to TCL13 of timer clock select register 1 TCL1 and the overflow signal of TM1 becomes the count clock of TM2 Figure 9 11 Inte...

Page 235: ...6 4 µs 25 1 fX 26 1 fX 221 1 fX 222 1 fX 25 1 fX 26 1 fX 6 4 µs 12 8 µs 419 4 ms 838 9 ms 6 4 µs 12 8 µs 26 1 fX 27 1 fX 222 1 fX 223 1 fX 26 1 fX 27 1 fX 12 8 µs 25 6 µs 838 9 ms 1 7 s 12 8 µs 25 6 µs 27 1 fX 28 1 fX 223 1 fX 224 1 fX 27 1 fX 28 1 fX 25 6 µs 51 2 µs 1 7 s 3 4 s 25 6 µs 51 2 µs 28 1 fX 29 1 fX 224 1 fX 225 1 fX 28 1 fX 29 1 fX 51 2 µs 102 4 µs 3 4 s 6 7 s 51 2 µs 102 4 µs 29 1 fX ...

Page 236: ...ers 10 and 20 CR10 and CR20 TM1 and TM2 are cleared to 0 and the interrupt request signal INTTM2 is generated Figure 9 12 External Event Counter Operation Timings with Rising Edge Specified Caution Even if the 16 bit timer event counter mode is used when the TM1 count value matches the CR10 value interrupt request INTTM1 is generated and the F F of 8 bit timer event counter output control circuit ...

Page 237: ...s 52 4 ms 400 ns 800 ns 22 1 fX 23 1 fX 218 1 fX 219 1 fX 22 1 fX 23 1 fX 800 ns 1 6 µs 52 4 ms 104 9 ms 800 ns 1 6 µs 23 1 fX 24 1 fX 219 1 fX 220 1 fX 23 1 fX 24 1 fX 1 6 µs 3 2 µs 104 9 ms 209 7 ms 1 6 µs 3 2 µs 24 1 fX 25 1 fX 220 1 fX 221 1 fX 24 1 fX 25 1 fX 3 2 µs 6 4 µs 209 7 ms 419 4 ms 3 2 µs 6 4 µs 25 1 fX 26 1 fX 221 1 fX 222 1 fX 25 1 fX 26 1 fX 6 4 µs 12 8 µs 419 4 ms 838 9 ms 6 4 µs...

Page 238: ...mer start errors An error with a maximum of one clock may occur concerning the time required for a match signal to be generated after timer start This is because 8 bit timer registers 1 and 2 TM1 and TM2 starts asynchronously with the count pulse Figure 9 14 8 Bit Timer Registers 1 and 2 Start Timing Count Clock TM1 TM2 Count Value CR10 CR20 INTTM2 TO2 Pin OutputNote 0000 0001 0002 N 1 N 0000 0001...

Page 239: ...tion Timing 3 Operation after compare register change during timer count operation If the values after the 8 bit compare registers 10 and 20 CR10 and CR20 are changed are smaller than those of 8 bit timer registers TM1 and TM2 TM1 and TM2 continue counting overflow and then restart counting from 0 Thus if the value M after CR10 and CR20 change is smaller than value N before the change it is necess...

Page 240: ...240 MEMO ...

Page 241: ...main system clock You should switch to the 32 768 kHz subsystem clock to generate 0 5 second intervals 2 Interval timer Interrupt requests INTTM3 are generated at the preset time interval Table 10 1 Interval Timer Interval Time When operated at When operated at When operated at fXX 5 0 MHz fXX 4 19 MHz fXT 32 768 kHz 24 1 fW 410 µs 488 µs 488 µs 25 1 fW 819 µs 977 µs 977 µs 26 1 fW 1 64 ms 1 95 ms...

Page 242: ...egisters The following two types of registers are used to control the watch timer Timer clock select register 2 TCL2 Watch timer mode control register TMC2 1 Timer clock select register 2 TCL2 Refer to Figure 10 2 This register sets the watch timer count clock TCL2 is set with an 8 bit memory manipulation instruction RESET input sets TCL2 to 00H Remark Besides setting the watch timer count clock T...

Page 243: ...NTTM3 To 16 Bit Timer Event Counter Watch Timer Mode Control Register TMC26 TMC25 TMC24 TMC23 TMC22 TMC21 TMC20 Internal Bus TCL24 Timer Clock Select Register 2 3 fW 24 fW 25 fW 26 fW 27 fW 28 fW 29 fW fXX 27 fXT Clear Clear Selector Selector Selector Figure 10 1 Watch Timer Block Diagram ...

Page 244: ...0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 TCL22 TCL21 TCL20 fXX 23 fXX 24 fXX 25 fXX 26 fXX 27 fXX 28 fXX 29 fXX 211 MCS 1 fX 23 625 kHz fX 24 313 kHz fX 25 156 kHz fX 26 78 1 kHz fX 27 39 1 kHz fX 28 19 5 kHz fX 29 9 8 kHz fX 211 2 4 kHz MCS 0 fX 24 313 kHz fX 25 156 kHz fX 26 78 1 kHz fX 27 39 1 kHz fX 28 19 5 kHz fX 29 9 8 kHz fX 210 4 9 kHz fX 212 1 2 kHz Watchdog Timer Count Clock Selecti...

Page 245: ... R W R W 0 1 TMC23 fXX 5 0 MHz Operation 214 fW 0 4 sec 213 fW 0 2 sec Watch Flag Set Time Selection 0 0 0 0 1 1 Other than above 0 0 1 1 0 0 0 1 0 1 0 1 TMC26 TMC25 TMC24 fXX 5 0 MHz Operation 24 fW 410 s 25 fW 819 s 26 fW 1 64 ms 27 fW 3 28 ms 28 fW 6 55 ms 29 fW 13 1 ms Setting prohibited fXX 4 19 MHz Operation 24 fW 488 s 25 fW 977 s 26 fW 1 95 ms 27 fW 3 91 ms 28 fW 7 81 ms 29 fW 15 6 ms fXT ...

Page 246: ... 0 MHz 10 4 2 Interval timer operation The watch timer operates as interval timer which generates interrupt requests repeatedly at an interval of the preset count value The interval time can be selected with bits 4 to 6 TMC24 to TMC26 of the watch timer mode control register Table 10 3 Interval Timer Interval Time When operated at When operated at When operated at fXX 5 0 MHz fXX 4 19 MHz fXT 32 7...

Page 247: ... be generated Table 11 1 Watchdog Timer Runaway Detection Times Runaway Detection Time MCS 1 MCS 0 211 1 fXX 211 1 fX 410 µs 212 1 fX 819 µs 212 1 fXX 212 1 fX 819 µs 213 1 fX 1 64 ms 213 1 fXX 213 1 fX 1 64 ms 214 1 fX 3 28 ms 214 1 fXX 214 1 fX 3 28 ms 215 1 fX 6 55 ms 215 1 fXX 215 1 fX 6 55 ms 216 1 fX 13 1 ms 216 1 fXX 216 1 fX 13 1 ms 217 1 fX 26 2 ms 217 1 fXX 217 1 fX 26 2 ms 218 1 fX 52 4...

Page 248: ...213 1 fX 1 64 ms 214 1 fX 3 28 ms 214 1 fXX 214 1 fX 3 28 ms 215 1 fX 6 55 ms 215 1 fXX 215 1 fX 6 55 ms 216 1 fX 13 1 ms 216 1 fXX 216 1 fX 13 1 ms 217 1 fX 26 2 ms 217 1 fXX 217 1 fX 26 2 ms 218 1 fX 52 4 ms 219 1 fXX 219 1 fX 104 9 ms 220 1 fX 209 7 ms Remarks 1 fXX Main system clock frequency fX or fX 2 2 fX Main system clock oscillation frequency 3 MCS Oscillation mode selection register bit ...

Page 249: ...chdog timer mode control register WDTM Figure 11 1 Watchdog Timer Block Diagram Control register Prescaler fXX 24 fXX 25 fXX 26 fXX 27 fXX 28 fXX 29 Selector Watchdog Timer Mode Register Internal Bus Internal Bus TCL22 TCL21TCL20 fXX 23 fXX 211 Timer Clock Select Register 2 3 WDTM4 RUN WDTM3 8 Bit Counter TMMK4 RUN TMIF4 INTWDT Maskable Interrupt Request INTWDT Non Maskable Interrupt Request RESET...

Page 250: ...lock select register 2 TCL2 Watchdog timer mode register WDTM 1 Timer clock select register 2 TCL2 This register sets the watchdog timer count clock TCL2 is set with 8 bit memory manipulation instruction RESET input sets TCL2 to 00H Remark Besides setting the watchdog timer count clock TCL2 sets the watch timer count clock and buzzer output frequency ...

Page 251: ...0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 TCL22 TCL21 TCL20 fXX 23 fXX 24 fXX 25 fXX 26 fXX 27 fXX 28 fXX 29 fXX 211 MCS 1 fX 23 fX 24 fX 25 fX 26 fX 27 fX 28 fX 29 fX 211 MCS 0 fX 24 fX 25 fX 26 fX 27 fX 28 fX 29 fX 210 fX 212 Watchdog Timer Count Clock Selection 0 1 TCL24 fXX 27 fXT 32 768 kHz MCS 1 fX 27 39 1 kHz MCS 0 fX 28 19 5 kHz Watchdog Timer Count Clock Selection 0 1 1 1 1 0 0 1 1 ...

Page 252: ...verflow time is up to 0 5 shorter than the time set by timer clock select register 2 TCL2 2 To use watchdog timer modes 1 and 2 make sure that the interrupt request flag TMIF4 is 0 and then set WDTM4 to 1 If WDTM4 is set to 1 when TMIF4 is 1 the non maskable interrupt request occurs regardless of the contents of WDTM3 Remark Don t care RUM 7 0 6 0 WDTM4 4 WDTM3 3 2 1 0 FFF9H Address WDTM Symbol 0 ...

Page 253: ...STOP mode Thus set RUN to 1 before the STOP mode is set clear the watchdog timer and then execute the STOP instruction Cautions 1 The actual runaway detection time may be shorter than the set time by a maximum of 0 5 2 When the subsystem clock is selected for CPU clock watchdog timer count operation is stopped Table 11 4 Watchdog Timer Runaway Detection Times TCL22 TCL21 TCL20 Runaway Detection Ti...

Page 254: ...cute the STOP instruction Cautions 1 Once bit 4 WDTM4 of WDTM is set to 1 with the watchdog timer mode selected the interval timer mode is not set unless RESET input is applied 2 The interval time just after setting with WDTM may be shorter than the set time by a maximum of 0 5 3 When the subsystem clock is selected for CPU clock watchdog timer count operation is stopped Table 11 5 Interval Timer ...

Page 255: ...t clock pulses 1 Select the clock pulse output frequency with clock pulse output disabled with bits 0 to 3 TCL00 to TCL03 of TCL0 2 Set the P35 output latch to 0 3 Set bit 5 PM35 of port mode register 3 PM3 to 0 set to output mode 4 Set bit 7 CLOE of timer clock select register 0 TCL0 to 1 Caution Clock output cannot be used when setting P35 output latch to 1 Remark When clock output enable disabl...

Page 256: ... Selector Timer Clock Select Register 0 Port Mode Register 3 PCL P35 12 2 Clock Output Control Circuit Configuration The clock output control circuit consists of the following hardware Table 12 1 Clock Output Control Circuit Configuration Item Configuration Timer clock select register 0 TCL0 Port mode register 3 PM3 Figure 12 2 Clock Output Control Circuit Block Diagram Control register ...

Page 257: ...ol the clock output function Timer clock select register 0 TCL0 Port mode register 3 PM3 1 Timer clock select register 0 TCL0 This register sets PCL output clock TCL0 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets TCL0 to 00H Remark Besides setting PCL output clock TCL0 sets the 16 bit timer register count clock ...

Page 258: ...1 0 1 0 1 0 1 0 1 TCL06 TCL05 TCL04 TI00 Valid edge specifiable 2fXX fXX fXX 2 fXX 22 Watch Timer Output INTTM3 Setting prohibited MCS 1 Setting prohibited fX 5 0 MHz fX 2 2 5 MHz fX 22 1 25 MHz MCS 0 fX 5 0 MHz fX 2 2 5 MHz fX 22 1 25 MHz fX 23 625 kHz 16 Bit Timer Register Count Clock Selection TCL00 0 1 0 1 0 1 0 1 0 Figure 12 3 Timer Clock Select Register 0 Format Cautions 1 Set the TI00 P00 I...

Page 259: ... with fX 5 0 MHz or fXT 32 768 kHz 2 Port mode register 3 PM3 This register set port 3 input output in 1 bit units When using the P35 PCL pin for clock output function set PM35 and output latch of P35 to 0 PM3 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM3 to FFH Figure 12 4 Port Mode Register 3 Format PM37 7 PM36 6 PM35 PM34 4 PM33 3 2 1 0 FF23H Address PM3 Symb...

Page 260: ...260 MEMO ...

Page 261: ...in Follow the procedure below to output the buzzer frequency 1 Select the buzzer output frequency with bits 5 to 7 TCL25 to TCL27 of TCL2 2 Set the P36 output latch to 0 3 Set bit 6 PM36 of port mode register 3 PM3 to 0 Set to output mode Caution Buzzer output cannot be used when setting P36 output latch to 1 13 2 Buzzer Output Control Circuit Configuration The buzzer output control circuit consis...

Page 262: ...t function Timer clock select register 2 TCL2 Port mode register 3 PM3 1 Timer clock select register 2 TCL2 This register sets the buzzer output frequency TCL2 is set with an 8 bit memory manipulation instruction RESET input sets TCL2 to 00H Remark Besides setting the buzzer output frequency TCL2 sets the watch timer count clock and the watchdog timer count clock ...

Page 263: ... W R W 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 TCL22 TCL21 TCL20 fXX 23 fXX 24 fXX 25 fXX 26 fXX 27 fXX 28 fXX 29 fXX 211 MCS 1 fX 23 fX 24 fX 25 fX 26 fX 27 fX 28 fX 29 fX 211 MCS 0 fX 24 fX 25 fX 26 fX 27 fX 28 fX 29 fX 210 fX 212 Watchdog Timer Count Clock Selection 0 1 TCL24 fXX 27 fXT 32 768 kHz MCS 1 fX 27 39 1 kHz MCS 0 fX 28 19 5 kHz Watchdog Timer Count Clock Selection 0 1 1 1 1 0...

Page 264: ...e Selection n 0 to 7 Output mode output buffer ON Input mode output buffer OFF 2 Port mode register 3 PM3 This register sets port 3 input output in 1 bit units When using the P36 BUZ pin for buzzer output function set PM36 and output latch of P36 to 0 PM3 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM3 to FFH Figure 13 3 Port Mode Register 3 Format ...

Page 265: ...channel of analog input from ANI0 to ANI7 and perform A D conversion In the case of hardware start A D conversion operation stops when an A D conversion ends and an interrupt request INTAD is generated In the case of software start the A D conversion operation is repeated Each time an A D conversion operation ends an interrupt request INTAD is generated 14 2 A D Converter Configuration The A D con...

Page 266: ...D Voltage Comparator Tap Selector INTAD INTP3 Successive Approximation Register SAR A D Converter Input Select Register ADIS2 ADIS1 ADIS0 Note 1 Note 2 ADM1 ADM3 INTP3 P03 TRG FR1 FR0 ADM3 ADM2 ADM1 A D Conversion Result Register ADCR AVREF0 AVSS Selector HSC Figure 14 1 A D Converter Block Diagram Notes 1 Selector to select the number of channels to be used for analog input 2 Selector to select t...

Page 267: ...ut voltage 5 Series resistor string The series resistor string is connected between AVREF0 and AVSS and generates a voltage to be compared to the analog input 6 ANI0 to ANI7 pins These are 8 channel analog input pins to input analog signals to undergo A D conversion to the A D converter Pins other than those selected as analog input by the A D converter input select register ADIS can be used as in...

Page 268: ...l to the serial resistor string between the AVREF0 pin and the AVSS pin so that the reference voltage error increases 8 AVSS pin This is a GND potential pin of the A D converter Keep it at the same potential as the VSS pin when not using the A D converter 9 AVDD pin This is an A D converter analog power supply pin Keep it at the same potential as the VSS pin when not using the A D converter Cautio...

Page 269: ...rter mode register ADM A D converter input select register ADIS External interrupt mode register 1 INTM1 1 A D converter mode register ADM This register sets the analog input channel for A D conversion conversion time conversion start stop and external trigger ADM is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets ADM to 01H ...

Page 270: ...3 2 1 0 FF80H Address ADM Symbol ADM2 ADM1 HSC 5 01H After Reset R W R W ADM3 0 0 0 0 1 1 1 1 ADM2 0 0 1 1 0 0 1 1 ADM1 0 1 0 1 0 1 0 1 Analog Input Channel Selection ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 TRG 0 1 External Trigger Selection No external trigger software starts Conversion started by external trigger hardware starts FR1 0 0 1 1 FR0 0 1 0 0 Other than above A D Conversion Time Select...

Page 271: ...ls set for analog input with ADIS 2 No internal pull up resistor can be used to the channels set for analog input with ADIS irrespective of the value of bit 1 PUO1 of the pull up resistor option register L PUOL Figure 14 4 A D Converter Input Select Register Format 0 7 0 6 0 0 4 ADIS3 3 2 1 0 FF84H Address ADIS Symbol ADIS2 ADIS1 ADIS0 5 00H After Reset R W R W ADIS3 0 0 0 0 0 0 0 0 1 Other than a...

Page 272: ...S41 ES40 5 00H After Reset R W R W ES41 0 0 1 1 ES40 0 1 0 1 INTP3 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES51 0 0 1 1 ES50 0 1 0 1 INTP4 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES61 0 0 1 1 ES60 0 1 0 1 INTP5 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling a...

Page 273: ...age tap and analog input is compared with a voltage comparator If the analog input is greater than 1 2 AVREF0 the MSB of SAR remains set If the input is smaller than 1 2 AVREF0 the MSB is reset 7 Next bit 6 of SAR is automatically set and the operation proceeds to the next comparison In this case the series resistor string voltage tap is selected according to the preset value of bit 7 as described...

Page 274: ...rite to the ADM is performed during an A D conversion operation the conversion operation is initialized and if the CS bit is set 1 conversion starts again from the beginning After RESET input the value of ADCR is undefined SAR ADCR INTAD A D Converter Operation Sampling Time Sampling A D Conversion Conversion Time Undefined 80H C0H or 40H Conversion Result Conversion Result ...

Page 275: ...0 5 Where INT Function which returns integer parts of value in parentheses VIN Analog input voltage AVREF0 AVREF0 pin voltage ADCR Value of A D conversion result register ADCR Figure 14 7 shows the relation between the analog input voltage and the A D conversion result Figure 14 7 Relations between Analog Input Voltage and A D Conversion Result VIN AVREF0 AVREF0 256 AVREF0 256 1 512 1 256 3 512 2 ...

Page 276: ...g input pins specified with bits 1 to 3 ADM1 to ADM3 of ADM Upon termination of the A D conversion the conversion result is stored in the A D conversion result register ADCR and the interrupt request signal INTAD is generated After one A D conversion operation is started and terminated another operation is not started until a new external trigger signal is input If data with CS set to 1 is written...

Page 277: ... terminated the next A D conversion operation starts immediately The A D conversion operation continues repeatedly until new data is written to ADM If data with CS set to 1 is written to ADM again during A D conversion the converter suspends its A D conversion operation and starts A D conversion on the newly written data If data with CS set to 0 is written to ADM during A D conversion the A D conv...

Page 278: ...tandby mode However there is no precision to the actual AVREF0 voltage and therefore the conversion values themselves lack precision and can only be used for relative comparison Figure 14 10 Example of Method of Reducing Current Dissipation in Standby Mode 2 Input range of ANI0 to ANI7 The input voltages of ANI0 to ANI7 should be within the specification range In particular if a voltage above AVRE...

Page 279: ...reduce the conversion resolution Also if digital pulses are applied to a pin adjacent to the pin in the process of A D conversion the expected A D conversion value may not be obtainable due to coupling noise Therefore avoid applying pulses to pins adjacent to the pin undergoing A D conversion 5 AVREF0 pin input impedance A series resistor string of approximately 10 kΩ is connected between the AVRE...

Page 280: ...version is stopped and then resumed clear the ADIF before it is resumed Figure 14 12 A D Conversion End Interrupt Request Generation Timing 7 AVDD pin The AVDD pin is the analog circuit power supply pin and supplies power to the input circuits of ANI0 P10 to ANI7 P17 Therefore be sure to apply the same voltage as VDD to this pin even when the application circuit is designed so as to switch to a ba...

Page 281: ... Start the A D conversion by setting the DACE0 and DACE1 of the D A converter mode register DAM There are two types of modes for the D A converter as follows 1 Normal mode Outputs an analog voltage signal immediately after the D A conversion 2 Real time output mode Outputs an analog voltage signal synchronously with the output trigger after the D A conversion Since a sine wave can be generated in ...

Page 282: ... A conversion value set register 1 DACS1 Control register D A converter mode register DAM Figure 15 1 D A Converter Block Diagram Register Selector D A Conversion Value Set Register 1 DACS1 Internal Bus Internal Bus 2R 2R 2R 2R R R 2R 2R 2R 2R R R DAM5 ANO1 P131 ANO0 P130 D A Converter Mode Register DACS1 Write INTTM2 DACS0 Write INTTM1 AVREF1 AVSS D A Conversion Value Set Register 0 DACS0 DAM4 DA...

Page 283: ...input sets these registers to 00H Analog voltage output to the ANO0 and ANO1 pins is determined by the following expression ANOn output voltage AVREF1 where n 0 1 Cautions 1 In the real time output mode when data that are set in DACS0 and DACS1 are read before an output trigger is generated the previous data are read rather than the set data 2 In the real time output mode data should be set to DAC...

Page 284: ...D A Converter Control Registers The D A converter mode register DAM controls the D A converter This register sets D A converter operation enable stop The DAM is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets this register to 00H Figure 15 2 D A Converter Mode Register Format Cautions 1 When using the D A converter a dual function port pin should be set to the input mode...

Page 285: ...n operations can be started by setting DACE0 and DACE1 of the DAM respectively 4 In the normal mode the analog voltage signals are output to the ANO0 P130 and ANO1 P131 pins immediately after the D A conversion In the real time output mode the analog voltage signals are output synchronously with the output triggers 5 In the normal mode the analog voltage signals to be output are held until new dat...

Page 286: ...ing may be long design the ground pattern so as to be close to those lines or use some other expedient to achieve shorter wiring Figure 15 3 Use Example of Buffer Amplifier a Inverting amplifier b Voltage follower 2 Output voltage of D A converter Because the output voltage of the converter changes in steps use the D A converter output signals in general by connecting a low pass filter 3 AVREF1 pi...

Page 287: ... 23 fXX 24 fXX 25 fXX 26 fXX 27 fXX 28 external clock TO2 output MSB LSB switchable as the start bit Serial transfer end interrupt request flag CSIIF0 Channel 1 fXX 2 fXX 22 fXX 23 fXX 24 fXX 25 fXX 26 fXX 27 fXX 28 external clock TO2 output MSB LSB switchable as the start bit Automatic transmit receive function Serial transfer end interrupt request flag CSIIF1 Channel 2 Baud rate generator output...

Page 288: ...s which incorporate a conventional synchronous clocked serial interface as is the case with the 75X XL 78K and 17K series 3 SBI serial bus interface mode MSB first This mode is used for 8 bit data transfer with two or more devices using two lines of serial clock SCK0 and serial data bus SB0 or SB1 The SBI mode conforms to the NEC serial bus format and transmits receives transfer data discriminatin...

Page 289: ... This mode enables to cope with any one of the possible data transfer formats by controlling the SCK0 level and the SB0 or SB1 output level Thus the handshake line previously necessary for connection of two or more devices can be used as input output ports Figure 16 1 Serial Bus Interface SBI System Configuration Example Master CPU SCK0 SB0 SCK0 SB0 Slave CPU1 SCK0 SB0 Slave CPU2 SCK0 SB0 Slave CP...

Page 290: ...0 Configuration Item Configuration Serial I O shift register 0 SIO0 Slave address register SVA Timer clock select register 3 TCL3 Serial operating mode register 0 CSIM0 Control register Serial bus interface control register SBIC Interrupt timing specify register SINT Port mode register 2 PM2 Note Note Refer to Figure 6 5 Block Diagram of P20 P21 P23 to P26 and Figure 6 6 Block Diagram of P22 P27 R...

Page 291: ...M27 Selector P25 Output Latch P26 Output Latch CLD P27 Output Latch Internal Bus BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT Internal Bus Bus Release Command Acknowledge Detector Serial Clock Counter Serial Clock Control Circuit CLR D SET Q Match Busy Acknowledge Output Circuit Interrupt Request Signal Generator ACKD CMDD RELD WUP Selector Selector TCL33 TCL32 TCL31 TCL30 4 Timer Clock Select Register...

Page 292: ...ipulation instruction This register is not used in the 3 wire serial I O mode The master device outputs a slave address for selection of a particular slave device to the connected slave device These two data the slave address output from the master device and the SVA value are compared with an address comparator If they match the slave device has been selected In that case bit 6 COI of serial oper...

Page 293: ... signal generation It generates the interrupt request signal in the following cases In the 3 wire serial I O mode and 2 wire serial I O mode This circuit generates an interrupt request signal every eight serial clocks In the SBI mode When WUP is 0 Generates an interrupt request signal every eight serial clocks When WUP is 1 Generates an interrupt request signal when the serial I O shift register 0...

Page 294: ...erial interface channel 0 Timer clock select register 3 TCL3 Serial operating mode register 0 CSIM0 Serial bus interface control register SBIC Interrupt timing specify register SINT 1 Timer clock select register 3 TCL3 This register sets the serial clock of serial interface channel 0 TCL3 is set with an 8 bit memory manipulation instruction RESET input sets TCL3 to 88H ...

Page 295: ... MHz fX 23 625 kHz fX 24 313 kHz fX 25 156 kHz fX 26 78 1 kHz fX 27 39 1 kHz fX 28 19 5 kHz MCS 0 fX 22 1 25 MHz fX 23 625 kHz fX 24 313 kHz fX 25 156 kHz fX 26 78 1 kHz fX 27 39 1 kHz fX 28 19 5 kHz fX 29 9 8 kHz Other than above Setting prohibited Serial Interface Channel 1 Serial Clock Selection TCL37 TCL36 TCL35 TCL34 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 fXX 2 fXX 22...

Page 296: ...6 5 4 3 2 1 0 7 Symbol CSIM0 CSIE0 COI WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 CSIM01 0 1 Serial Interface Channel 0 Clock Selection Input Clock to SCK0 pin from off chip 8 bit timer register 2 TM2 output 0 0 SCK0 CMOS input output R W 1 Clock specified with bits 0 to 3 of timer clock select register 3 TCL3 CSIM 04 0 1 CSIM00 0 1 FF60H 00H R WNote 1 Address After Reset R W R W CSIM 03 CSIM 02 PM25 ...

Page 297: ...be able to be used as a normal port WUP 0 1 Wake up Function ControlNote 1 Interrupt request signal generation with each serial transfer in any mode Interrupt request signal generation when the address received after bus release when CMDD RELD 1 matches the slave address register SVA data in SBI mode R W COI 0 1 Slave Address Comparison Result FlagNote 2 Slave address register SVA not equal to ser...

Page 298: ...Address After Reset R W CMDT Used for command signal output When CMDT 1 SO0 Iatch is cleared to 0 After SO0 latch clearance automatically cleared to 0 Also cleared to 0 when CSIE0 0 R W R RELD Bus Release Detection Set Conditions RELD 1 Clear Conditions RELD 0 When bus release signal REL is detected When transfer start instruction is executed If SIO0 and SVA values do not match in address receptio...

Page 299: ...dge of SCK0 just after execution of the instruction to be set to 1 automatically output when ACKE 1 However not automatically cleared to 0 after acknowledge signal output After completion of transfer 1 R W R ACKD Acknowledge Detection Clear Conditions ACKD 0 Falling edge of the SCK0 immediately after the busy mode is released while executing the transfer start instruction When CSIE0 0 When RESET i...

Page 300: ...to 0 3 When CSIE0 0 CLD becomes 0 Caution Be sure to set bits 0 to 3 to 0 Remark SVA Slave address register CSIIF0 Interrupt request flag corresponding to INTCSI0 CSIE0 Bit 7 of serial operating mode register 0 CSIM0 6 5 4 3 2 1 0 7 Symbol SINT 0 CLD SIC SVAM 0 0 0 0 FF63H 00H R WNote 1 Address After Reset R W SVAM 0 1 SVA Bit to be Used as Slave Address Bits 0 to 7 Bits 1 to 7 SIC 0 INTCSI0 Inter...

Page 301: ...0 SIO0 does not carry out shift operation either and thus it can be used as ordinary 8 bit register In the operation stop mode the P25 SI0 SB0 P26 SO0 SB1 and P27 SCK0 pins can be used as ordinary input output ports 1 Register setting The operation stop mode is set with the serial operating mode register 0 CSIM0 CSIM0 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CS...

Page 302: ...rial interface as is the case with the 75X XL 78K and 17K series Communication is carried out with three lines of serial clock SCK0 serial output SO0 and serial input SI0 1 Register setting The 3 wire serial I O mode is set with the serial operating mode register 0 CSIM0 and serial bus interface control register SBIC a Serial operating mode register 0 CSIM0 CSIM0 is set with a 1 bit or 8 bit memor...

Page 303: ...1 FF60H 00H R WNote 1 Address After Reset R W R W CSIM 03 CSIM 02 PM25 P25 PM26 P26 PM27 P27 Operation Mode Start Bit SIO SB0 P25 Pin Function SO0 SB1 P26 Pin Function SCK0 P27 Pin Function 1 0 WUP 0 1 Wake up Function Control Interrupt request signal generation with each serial transfer in any mode Interrupt request signal generation when the address received after bus release when CMDD RELD 1 ma...

Page 304: ...E0 Bit 7 of serial operating mode register 0 CSIM0 6 5 4 3 2 1 0 7 Symbol SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT RELT When RELT 1 SO0 Iatch is set to 1 After SO0 Iatch setting automatically cleared to 0 Also cleared to 0 when CSIE0 0 R W FF61H 00H R W Address After Reset R W CMDT When CMDT 1 SO0 Iatch is cleared to 0 After SO0 latch clearance automatically cleared to 0 Also cleared to 0 when...

Page 305: ...cally and the interrupt request flag CSIIF0 is set Figure 16 7 3 Wire Serial I O Mode Timings The SO0 pin is a CMOS output pin and outputs current SO0 latch statuses Thus the SO0 pin output status can be manipulated by setting bit 0 RELT and bit 1 CMDT of serial bus interface control register SBIC However do not carry out this manipulation during serial transfer Control the SCK0 pin output level i...

Page 306: ...ta write to SIO0 The SIO0 shift order remains unchanged Thus switching between MSB first and LSB first must be performed before writing data to SIO0 5 Transfer start Serial transfer is started by setting transfer data to the serial I O shift register 0 SIO0 when the following two conditions are satisfied Serial interface channel 0 operation control bit CSIE0 1 Internal serial clock is stopped or S...

Page 307: ...n simplifies the application program to control serial interface channel 0 The SBI function is incorporated into various devices including 75X XL Series and 78K Series Figure 16 10 shows a serial bus configuration example when a CPU having a serial interface compliant with SBI and peripheral ICs are used In SBI the SB0 SB1 serial data bus pin is an open drain output pin and therefore the serial da...

Page 308: ...e SBI functions are described below a Address command data identify function Serial data is distinguished into addresses commands and data b Chip select function by address transmission The master executes slave chip selection by address transmission c Wake up function The slave can easily discriminate address reception chip select with the wake up function which can be set reset by software When ...

Page 309: ...The dotted line indicates READY status The bus release signal and the command signal are output by the master device BUSY is output by the slave signal ACK can be output by either the master or slave device normally the 8 bit data receiver outputs Serial clocks continue to be output by the master device from 8 bit data transfer start to BUSY reset SCK0 SB0 SB1 SCK0 SB0 SB1 SCK0 SB0 SB1 8 9 9 A7 A0...

Page 310: ...he slave device The slave device incorporates hardware to detect the bus release signal b Command signal CMD The command signal is a signal with the SB0 SB1 line which has changed from the high level to the low level when the SCK0 line is at the high level without serial clock output This signal is output by the master device Figure 16 13 Command Signal A command signal indicates that the master i...

Page 311: ...by hardware and whether or not 8 bit data matches the own specification number slave address is checked by hardware If the 8 bit data matches the slave address the slave device has been selected After that communication with the master device continues until a release instruction is received from the master device Figure 16 15 Slave Selection with Address SCK0 A7 A6 A5 A4 A3 A2 A1 A0 1 2 3 4 5 6 7...

Page 312: ... Figure 16 16 Commands Figure 16 17 Data 8 bit data following a command signal is defined as command data 8 bit data without command signal is defined as data Command and data operation procedures are allowed to determine by user according to communications specifications SCK0 C7 C6 C5 C4 C3 C2 C1 C0 1 2 3 4 5 6 7 8 SB0 SB1 Command Command Signal SCK0 D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 SB0 SB...

Page 313: ...ine indicates READY status The acknowledge signal is one shot pulse to be generated at the falling edge of SCK0 after 8 bit data transfer It can be positioned anywhere and can be synchronized with any clock SCK0 After 8 bit data transmission the transmitter checks whether the receiver has returned the acknowledge signal If the acknowledge signal is not returned for the preset period of time after ...

Page 314: ...e low level The BUSY signal output follows the acknowledge signal output from the master or slave device It is set reset at the falling edge of SCK0 When the BUSY signal is reset the master device automatically terminates the output of SCK0 serial clock When the BUSY signal is reset and the READY signal is set the master device can start the next transfer Caution SBI outputs the BUSY signal after ...

Page 315: ...ter 3 TCL3 CSIM 04 0 1 CSIM00 0 1 FF60H 00H R WNote 1 Address After Reset R W R W CSIM 03 CSIM 02 PM25 P25 PM26 P26 PM27 P27 Operation Mode Start Bit SI0 SB0 P25 Pin Function SO0 SB1 P26 Pin Function SCK0 P27 Pin Function 1 0 0 0 0 0 0 0 1 1 Note 2 Note 2 Note 2 Note 2 MSB P25 CMOS input output SB0 N ch open drain input output SB1 N ch open drain input output P26 CMOS input output WUP 0 1 Wake up ...

Page 316: ...instruction is executed If SIO0 and SVA values do not match in address reception only when WUP 1 When CSIE0 0 When RESET input is applied R CMDD Command Detection Clear Conditions CMDD 0 When transfer start instruction is executed When bus release signal REL is detected When CSIE0 0 When RESET input is applied Set Conditions CMDD 1 When command signal CMD is detected Acknowledge signal is output i...

Page 317: ...ased during the transfer start instruction execution When CSIE0 0 When RESET input is applied Set Conditions ACKD 1 When acknowledge signal ACK is detected at the rising edge of SCK0 clock after completion of transfer BSYE Synchronizing Busy Signal Output Control 0 Disables busy signal which is output in synchronization with the falling edge of SCK0 clock just after execution of the instruction to...

Page 318: ... Slave address register CSIIF0 Interrupt request flag corresponding to INTCSI0 CSIE0 Bit 7 of serial operating mode register 0 CSIM0 6 5 4 3 2 1 0 7 Symbol SINT 0 CLD SIC SVAM 0 0 0 0 FF63H 00H R WNote 1 Address After Reset R W SVAM 0 1 SVA Bit to be Used as Slave Address Bits 0 to 7 Bits 1 to 7 SIC 0 INTCSI0 Interrupt Factor SelectionNote 2 CSIIF0 is set upon termination of serial interface chann...

Page 319: ...ure 16 20 RELT CMDT RELD and CMDD Operations Master Figure 16 21 RELT and CMDD Operations Slave SCK0 SB0 SB1 RELT CMDT CMDD RELD SIO0 Slave address write to SIO0 Transfer Start Instruction Write FFH to SIO0 Transfer start instruction SIO0 SCK0 SB0 SB1 RELD CMDD Transfer start instruction A7 A6 A1 A0 1 2 7 8 9 READY A7 A6 A1 A0 ACK Slave address When addresses match When addresses do not match ...

Page 320: ...EL 0 µPD78054 Subseries Figure 16 22 ACKT Operation Caution Do not set ACKT before termination of transfer SCK0 6 SB0 SB1 ACKT 7 8 9 D2 D1 D0 ACK When set during this period ACK signal is output for a period of one clock just after setting ...

Page 321: ... D1 D0 ACK When ACKE 1 at this point ACK signal is output at 9th clock SCK0 SB0 SB1 ACKE 7 8 9 D1 D0 ACK 6 D2 If set during this period and ACKE 1 at the falling edge of the next SCK0 ACK signal is output for a period of one clock just after setting SCK0 SB0 SB1 ACKE 1 2 7 8 9 D7 D6 D2 D1 D0 When ACKE 0 at this point ACK signal is not output SCK0 SB0 SB1 ACKE If set and cleared during this period ...

Page 322: ...tructed in BUSY Figure 16 25 BSYE Operation SCK0 SB0 SB1 ACKD 7 8 9 D1 D0 ACK 6 D2 Transfer Start Instruction SIO0 Transfer Start SB0 SB1 ACKD ACK 9 SIO0 7 8 D1 6 D2 D0 Transfer Start Instruction Transfer Start SCK0 SCK0 SB0 SB1 ACKD ACK 9 Transfer Start Instruction SIO0 7 8 D1 6 D2 D0 D6 D7 BUSY SCK0 SB0 SB1 BSYE 7 8 9 ACK 6 When BSYE 1 at this point BUSY If reset during this period and BSYE 0 at...

Page 323: ...l Low level signal to be output to SB0 SB1 following Acknowledge signal 1 BSYE 0 2 Execution of instruction for data write to SIO0 transfer start instruction Master slave SB0 SB1 rising edge when SCK0 1 Master Bus release signal REL RELT set RELD set CMDD clear CMDD set CMDT set Master Command signal CMD SB0 SB1 falling edge when SCK0 1 Acknowledge signal ACK ACKD set Completion of reception Slave...

Page 324: ...nization with SCK0 after output of REL and CMD signals Master Commands C7 to C0 Instructions and messages to the slave device Master slave Data D7 to D0 8 bit data to be transferred in synchronization with SCK0 without output of REL and CMD signals Table 16 3 Various Signals in SBI Mode 2 2 When CSIE0 1 execution of instruction for data write to SIO0 serial transfer start instruction Note 2 Notes ...

Page 325: ...ut an external pull up resistor is necessary Figure 16 26 Pin Configuration Caution Because the N ch open drain output must be high impedance state at time of data reception write FFH to serial I O shift register 0 SIO0 in advance The N ch open drain can be high impedance state at any time of transfer However when the wake up function specify bit WUP 1 the N ch open drain output always becomes hig...

Page 326: ...ansmitted is fetched into the destination device that is the serial I O shift register 0 SIO0 Thus transmit errors can be detected in the following way a Method of comparing SIO0 data before transmission to that after transmission In this case if two data differ from each other a transmit error is judged to have occurred b Method of using the slave address register SVA Transmit data is set to both...

Page 327: ...ion INTCSI0 Generation ACKD Set SCK0 Stop Hardware Operation WUP 0 ACKT Set Program Processing CMDD Set INTCSI0 Generation ACK Output Hardware Operation CMDT Set RELT Set CMDT Set Write to SIO0 Interrupt Servicing Preparation for the Next Serial Transfer Master Device Processing Transmitter Transfer Line Slave Device Processing Receiver CMDD Clear CMDD Set RELD Set Serial Reception BUSY Output REA...

Page 328: ... Serial Transmission INTCSI0 Generation ACKD Set SCK0 Stop Hardware Operation ACKT Set Program Processing INTCSI0 Generation ACK Output Hardware Operation CMDT Set Write to SIO0 Interrupt Servicing Preparation for the Next Serial Transfer Master Device Processing Transmitter Transfer Line Slave Device Processing Receiver CMDD Set Serial Reception BUSY Output READY Command BUSY Clear BUSY Clear SIO...

Page 329: ...rogram Processing Serial Transmission INTCSI0 Generation ACKD Set SCK0 Stop Hardware Operation ACKT Set Program Processing INTCSI0 Generation ACK Output Hardware Operation Write to SIO0 Interrupt Servicing Preparation for the Next Serial Transfer Master Device Processing Transmitter Transfer Line Slave Device Processing Receiver Serial Reception BUSY Output READY Data BUSY Clear BUSY Clear SIO0 Re...

Page 330: ...Reception INTCSI0 Generation ACK Output Serial Reception Hardware Operation Program Processing INTCSI0 Generation ACKD Set Hardware Operation FFH Write to SIO0 Master Device Processing Receiver Transfer Line Slave Device processing Transmitter Serial Transmission BUSY Output READY Data BUSY Clear Write to SIO0 SCK0 Stop BUSY Clear 1 2 READY BUSY D7 D6 ACKT Set SIO0 Read Receive data processing FFH...

Page 331: ...ver when the wake up function specify bit WUP 1 the N ch open drain output is always high impedance state Thus it is not necessary to write FFH to SIO0 3 If data is written to SIO0 when the slave is busy the data is not lost When the busy state is cleared and SB0 or SB1 input is set to the high level READY state transfer starts Upon termination of 8 bit transfer serial transfer automatically stops...

Page 332: ...command preset by program instead of using the address match detection method c A transition of the SB0 SB1 pin from low to high or high to low while the SCK0 line is high is interpreted as a bus release or command signal Therefore a shift in the change timing of the bus due to the influence of the board capacitance etc may be incorrectly identified as a bus release signal or command signal regard...

Page 333: ... wire serial I O mode can cope with any communication format by program Communication is basically carried out with two lines of serial clock SCK0 and serial data input output SB0 or SB1 Figure 16 31 Serial Bus Configuration Example Using 2 Wire Serial I O Mode Master SCK0 Slave SB0 SB1 SCK0 SB0 SB1 VDD VDD ...

Page 334: ...0 0 1 FF60H 00H R WNote 1 Address After Reset R W R W CSIM 03 CSIM 02 PM25 P25 PM26 P26 PM27 P27 Operation Mode Start Bit SIO SB0 P25 Pin Function SO0 SB1 P26 Pin Function SCK0 P27 Pin Function 1 0 WUP 0 1 Wake up Function Control Interrupt request signal generation with each serial transfer in any mode Interrupt request signal generation when the address received after bus release when CMDD RELD ...

Page 335: ...E0 Bit 7 of serial operating mode register 0 CSIM0 6 5 4 3 2 1 0 7 Symbol SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT RELT When RELT 1 SO0 Iatch is set to 1 After SO0 Iatch setting automatically cleared to 0 Also cleared to 0 when CSIE0 0 R W FF61H 00H R W Address After Reset R W CMDT When CMDT 1 SO0 Iatch is cleared to 0 After SO0 latch clearance automatically cleared to 0 Also cleared to 0 when...

Page 336: ... 0 to 3 to 0 Remark CSIIF0 Interrupt request flag corresponding to INTCSI0 CSIE0 Bit 7 of serial operating mode register 0 CSIM0 6 5 4 3 2 1 0 7 Symbol SINT 0 CLD SIC 0 0 0 0 FF63H 00H R WNote 1 Address After Reset R W SIC 0 INTCSI0 Interrupt Factor Selection CSIIF0 is set upon termination of serial interface channel 0 transfer CSIIF0 is set upon bus release detection or termination of serial inte...

Page 337: ... the interrupt request flag CSIIF0 is set Figure 16 32 2 Wire Serial I O Mode Timings The SB0 or SB1 pin specified for the serial data bus is an N ch open drain input output and thus it must be externally connected to a pull up resistor Because it is necessary to set N ch open drain output to high impedance state for data reception write FFH to SIO0 in advance The SB0 or SB1 pin generates the SO0 ...

Page 338: ...of 8 bit transfer serial transfer automatically stops and the interrupt request flag CSIIF0 is set 5 Error detection In the 2 wire serial I O mode the serial bus SB0 SB1 status being transmitted is fetched into the destination device that is serial I O shift register 0 SIO0 Thus transmit error can be detected in the following way a Method of comparing SIO0 data before transmission to that after tr...

Page 339: ... bits of serial bus interface control register SBIC SCK0 P27 pin output manipulating procedure is described below 1 Set the serial operating mode register 0 CSIM0 SCK0 pin enabled for serial operation in the output mode SCK0 1 with serial transfer suspended 2 Manipulate the P27 output latch with a bit manipulation instruction Figure 16 34 SCK0 P27 Pin Configuration To Internal Circuit SCK0 P27 P27...

Page 340: ...340 MEMO ...

Page 341: ...fXX 23 fXX 24 fXX 25 fXX 26 fXX 27 fXX 28 external clock TO2 output MSB LSB switchable as the start bit Serial transfer end interrupt request flag CSIIF0 Channel 1 fXX 2 fXX 22 fXX 23 fXX 24 fXX 25 fXX 26 fXX 27 fXX 28 external clock TO2 output MSB LSB switchable as the start bit Automatic transmit receive function Serial transfer end interrupt request flag CSIIF1 Channel 2 Baud rate generator out...

Page 342: ... serial input SI0 This mode enables simultaneous transmission reception and therefore reduces the data transfer processing time The start bit of transferred 8 bit data is switchable between MSB and LSB so that devices can be connected regardless of their start bit recognition This mode should be used when connecting with peripheral I O devices or display controllers which incorporate a conventiona...

Page 343: ...ith the I2C bus format In this mode the transmitter can output three kinds of data onto the serial data bus start condition data and stop condition to be actually sent or received The receiver automatically distinguishes the received data into start condition data or stop condition by hardware Figure 17 1 Serial Bus Configuration Example Using I2C Bus Master CPU SCL SDA0 SDA1 SCL SDA0 SDA1 Slave C...

Page 344: ...0 Configuration Item Configuration Serial I O shift register 0 SIO0 Slave address register SVA Timer clock select register 3 TCL3 Serial operating mode register 0 CSIM0 Control register Serial bus interface control register SBIC Interrupt timing specify register SINT Port mode register 2 PM2 Note Note Refer to Figure 6 7 Block Diagram of P20 P21 P23 to P26 and Figure 6 8 Block Diagram of P22 P27 R...

Page 345: ...ut Latch P26 Output Latch CLD P27 Output Latch Internal Bus BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT Internal Bus Stop Condition Start Condition Acknowledge Detector Serial Clock Counter Serial Clock Control Circuit CLR D SET Q Match Acknowledge Output Circuit Interrupt Request Signal Generator ACKD CMDD RELD WUP Selector Selector TCL33 TCL32 TCL31 TCL30 4 Timer Clock Select Register 3 fxx 2 fxx 28...

Page 346: ... the 3 wire serial I O mode The master device outputs a slave address for selection of a particular slave device to the connected slave device These two data the slave address output from the master device and the SVA value are compared with an address comparator If they match the slave device has been selected In that case bit 6 COI of serial operating mode register 0 CSIM0 becomes 1 Address comp...

Page 347: ...n wanting to coordinate receive time and processing systematically using software ACK information is generated by the receiving side thus ACKE should be set to 0 disable 1 1 0 An interrupt request signal is generated each time 9 serial clocks are counted 9 clock wait ACK information is generated by the receiving side thus ACKE should be set to 0 disable Other than above Setting prohibited I2C bus ...

Page 348: ...serial interface channel 0 Timer clock select register 3 TCL3 Serial operating mode register 0 CSIM0 Serial bus interface control register SBIC Interrupt timing specify register SINT 1 Timer clock select register 3 TCL3 This register sets the serial clock of serial interface channel 0 TCL3 is set with an 8 bit memory manipulation instruction RESET input sets TCL3 to 88H ...

Page 349: ... 27 39 1 kHz fX 28 19 5 kHz Other than above Setting prohibited Serial Interface Channel 1 Serial Clock Selection TCL37 TCL36 TCL35 TCL34 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 fXX 2 fXX 22 fXX 23 fXX 24 fXX 25 fXX 26 fXX 27 fXX 28 MCS 1 Setting prohibited fX 22 1 25 MHz fX 23 625 kHz fX 24 313 kHz fX 25 156 kHz fX 26 78 1 kHz fX 27 39 1 kHz fX 28 19 5 kHz MCS 0 fX 22 1 25...

Page 350: ...on enable stop wake up function and displays the address comparator match signal CSIM0 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM0 to 00H Caution Do not switch the operation mode 3 wire serial I O 2 wire serial I O I2C bus while the operation of serial interface channel 0 is enabled Stop the serial operation before switching the operation mode ...

Page 351: ...ote 1 Address After Reset R W R W CSIM 03 CSIM 02 PM25 P25 PM26 P26 PM27 P27 Operation Mode Start Bit SI0 SB0 SDA0 P25 Pin Function SO0 SB1 SDA1 P26 Pin Function SCK0 SCL P27 Pin Function 1 MSB LSB 1 0 0 0 1 Note3 3 wire serial l O mode SI0 Input SO0 CMOS output SCK0 CMOS input output Note3 2 wire serial l O mode or I2 C Bus Mode 0 SCK0 SCL N ch open drain input output 1 1 1 0 0 0 0 0 0 1 1 Note4 ...

Page 352: ...1H 00H R WNote Address After Reset R W CMDT Used for start condition signal output When CMDT 1 SO0 Iatch is cleared to 0 After SO0 latch clearance automatically cleared to 0 Also cleared to 0 when CSIE0 0 R W R RELD Stop Condition Detection Set Conditions RELD 1 Clear Conditions RELD 0 When stop condition signal is detected When transfer start instruction is executed If SIO0 and SVA values do not ...

Page 353: ...ever output with ACKT is enabled Used for reception when 8 clock wait mode is selected or for transmission Note 2 Enables acknowledge signal automatic output Outputs acknowledge signal in synchronization with the falling edge of the 9th SCL clock cycle automatically output when ACKE 1 However not automatically cleared to 0 after acknowledge signal output Used in reception with 9 clock wait mode se...

Page 354: ...when the state is cancelled Used to cancel wait state by means of WAT0 and WAT1 CLC 0 1 Clock Level ControlNote 2 Used in I2 C bus mode Make output level of SCL pin low unless serial transfer is being performed R W 1 Wait Sate Cancellation Control R W WAT1 0 1 Wait and Interrupt Control Generates interrupt service request at rising edge of 8th SCK0 clock cycle keeping clock output in high impedanc...

Page 355: ...terrupt request flag corresponding to INTCSI0 CSIE0 Bit 7 of serial operating mode register 0 CSIM0 SVAM 0 1 SVA Bit to be Used as Slave Address Bits 0 to 7 Bits 1 to 7 SIC 0 INTCSI0 Interrupt Cause SelectionNote1 CSIIF0 is set to 1 upon termination of serial interface channel 0 transfer CSIIF0 is set to 1 upon stop condition detection or termination of serial interface channel 0 transfer CLD 0 1 ...

Page 356: ...0 SIO0 does not carry out shift operation either and thus it can be used as ordinary 8 bit register In the operation stop mode the P25 SI0 SB0 SDA0 P26 SO0 SB1 SDA1 and P27 SCK0 SCL pins can be used as general input output ports 1 Register setting The operation stop mode is set with the serial operating mode register 0 CSIM0 CSIM0 is set with a 1 bit or 8 bit memory manipulation instruction RESET ...

Page 357: ...h 6 5 4 3 2 1 0 7 Symbol CSIM0 CSIE0 COI WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 CSIM01 0 1 Serial Interface Channel 0 Clock Selection Input Clock to SCK0 pin from off chip 8 bit timer register 2 TM2 output 0 2 wire serial I O mode See the section 17 4 3 2 wire serial I O mode operation R W 1 Clock specified with bits 0 to 3 of timer clock select register 3 TCL3 CSIM 04 0 CSIM00 0 1 FF60H 00H R WNo...

Page 358: ...IE0 Bit 7 of serial operating mode register 0 CSIM0 6 5 4 3 2 1 0 7 Symbol SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT RELT When RELT 1 SO0 Iatch is set to 1 After SO0 Iatch setting automatically cleared to 0 Also cleared to 0 when CSIE0 0 R W FF61H 00H R W Address After Reset R W CMDT When CMDT 1 SO0 Iatch is cleared to 0 After SO0 latch clearance automatically cleared to 0 Also cleared to 0 whe...

Page 359: ...ally and the interrupt request flag CSIIF0 is set Figure 17 7 3 Wire Serial I O Mode Timings The SO0 pin is a CMOS output pin and outputs current SO0 latch statuses Thus the SO0 pin output status can be manipulated by setting bit 0 RELT and bit 1 CMDT of serial bus interface control register SBIC However do not carry out this manipulation during serial transfer Control the SCK0 pin output level in...

Page 360: ...ata write to SIO0 The SIO0 shift order remains unchanged Thus switching between MSB first and LSB first must be performed before writing data to SIO0 5 Transfer start Serial transfer is started by setting transfer data to the serial I O shift register 0 SIO0 when the following two conditions are satisfied Serial interface channel 0 operation control bit CSIE0 1 Internal serial clock is stopped or ...

Page 361: ...y carried out with two lines of serial clock SCK0 and serial data input output SB0 or SB1 Figure 17 10 Serial Bus Configuration Example Using 2 Wire Serial I O Mode 1 Register setting The 2 wire serial I O mode is set with the serial operating mode register 0 CSIM0 the serial bus interface control register SBIC and the interrupt timing specify register SINT Master SCK0 Slave SB0 SB1 SCK0 SB0 SB1 V...

Page 362: ...ation Mode Start Bit SIO SB0 SDA0 P25 Pin Function SO0 SB1 SDA1 P26 Pin Function SCK0 SCL P27 Pin Function WUP 0 1 Wake up Function Control Interrupt request signal generation with each serial transfer in any mode Interrupt request signal generation when the address received after detecting start condition when CMDD 1 matches the slave address register SVA data in I C bus mode 2 R W 2 wire serial ...

Page 363: ...IE0 Bit 7 of serial operating mode register 0 CSIM0 6 5 4 3 2 1 0 7 Symbol SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT RELT When RELT 1 SO0 Iatch is set to 1 After SO0 Iatch setting automatically cleared to 0 Also cleared to 0 when CSIE0 0 R W FF61H 00H R W Address After Reset R W CMDT When CMDT 1 SO0 Iatch is cleared to 0 After SO0 latch clearance automatically cleared to 0 Also cleared to 0 whe...

Page 364: ...wire serial I O mode is used Remark CSIIF0 Interrupt request flag corresponding to INTCSI0 CSIE0 Bit 7 of serial operating mode register 0 CSIM0 6 5 4 3 2 1 0 7 Symbol SINT 0 CLD SIC CLC WREL WAT1 WAT0 FF63H 00H R WNote 1 Address After Reset R W SVAM SIC 0 INTCSI0 Interrupt Factor Selection CSIIF0 is set upon termination of serial interface channel 0 transfer CSIIF0 is set upon bus release detecti...

Page 365: ...y and the interrupt request flag CSIIF0 is set Figure 17 11 2 Wire Serial I O Mode Timings The SB0 or SB1 pin specified for the serial data bus is an N ch open drain input output and thus it must be externally connected to a pull up resistor Because it is necessary to set the N ch open drain ouput to high impedance for data reception write FFH to SIO0 in advance The SB0 or SB1 pin generates the SO...

Page 366: ...8 bit transfer serial transfer automatically stops and the interrupt request flag CSIIF0 is set 5 Error detection In the 2 wire serial I O mode the serial bus SB0 SB1 status being transmitted is fetched into the destination device that is serial I O shift register 0 SIO0 Thus transmit error can be detected in the following way a Method of comparing SIO0 data before transmission to that after trans...

Page 367: ...ation the master sends start condition data and stop condition signals to slave devices through the serial data bus while slave devices automatically detect and distinguish the type of signals due to the signal detection function incorporated as hardware This function simplifies the application program to control I2C bus An example of a serial bus configuration is shown in Figure 17 13 This system...

Page 368: ...ol function The master device and a slave device send and receive acknowledge signals to confirm that the serial communication has been executed normally e Wait signal WAIT control function When a slave device is preparing for data transmission or reception and requires more waiting time the slave device outputs a wait signal on the bus to inform the master device of the wait status 2 I2C bus defi...

Page 369: ...evice on the bus line must therefore have a different address Therefore after a slave device detects the start condition it compares the 7 bit address data received and the data of the slave address register SVA After the comparison only the slave device in which the data are a match becomes the communication partner and subsequently performs communication with the master device until the master d...

Page 370: ...which will be sent from the receiving side If the sending side device receives the acknowledge signal which means a successful data transfer it proceeds to the next processing If this signal is not sent back from the slave device this means that the data sent has not been received by the slave device and therefore the master device outputs a stop condition signal to terminate subsequent transmissi...

Page 371: ...g operation of slave devices see section 17 4 5 Cautions on Use of I2C Bus Mode Figure 17 20 Wait Signal a Wait of 8 Clock Cycles b Wait of 9 Clock Cycles SCL of master device D2 D1 D0 ACK D7 Output by manipulating ACKT 6 7 8 9 1 3 2 4 D6 D5 D4 Set low because slave device drives low though master device returns to Hi Z state No wait is inserted after 9th clock cycle and before master device start...

Page 372: ...te 3 serial I O or N ch open CMOS I O N ch open I2C bus mode drain I O drain I O R W WUP Wake up Function ControlNote 4 0 Interrupt request signal generation with each serial transfer in any mode 1 In I2C bus mode interrupt request signal is generated when the address data received after start condition detection when CMDD 1 matches data in slave address register SVA R COI Slave Address Comparison...

Page 373: ...0 0 When RESET input is applied 1 Setting Condition When stop condition is detected R CMDD Start Condition Detection 0 Clear Conditions When transfer start instruction is executed When stop condition is detected When CSIE0 0 When RESET input is applied 1 Setting Condition When start condition is detected R W ACKT SDA0 SDA1 is set to low after the Set instruction execution ACKT 1 before the next SC...

Page 374: ...n transfer start instruction is executed When CSIE0 0 When RESET input is applied 1 Set Conditions When acknowledge signal is detected at the rising edge of SCL clock after completion of transfer R W BSYE Control of N ch Open Drain Output for Transmission in I2C Bus ModeNote 4 Note 3 0 Output enabled transmission 1 Output disabled reception Notes 1 This setting must be performed prior to transfer ...

Page 375: ...Releases the wait state Automatically cleared to 0 after releasing the wait state This bit is used to release the wait state set by means of WAT0 and WAT1 R W CLC Clock level control 0 Used in I2C bus mode In cases other than serial transfer SCL pin output is driven low 1 Used in I2C bus mode In cases other than serial transfer SCL pin output is set to high impedance Clock line is held high Used b...

Page 376: ...CSIIF0 Also see Note 3 below Address A6 to A0 Definition 7 bit data synchronized with SCL immediately after start condition signal Function Indicates address value for specification of slave on serial bus Signaled by Master Signaled when See Note 2 below Affected flag s CSIIF0 Also see Note 3 below Transfer direction R W Definition 1 bit data output in synchronization with SCL after address output...

Page 377: ...unction is used by setting the bit 5 WUP of the serial operating mode register 0 CSIM0 however do not write FFH to SIO0 before reception Even if FFH is not written to SIO0 the N ch open drain output is always in high impedance state 6 Address match detection method In the I2C mode the master can select a specific slave device by sending slave address data CSIIF0 is set if the slave address transmi...

Page 378: ... data to the SO latch in synchronization with the falling edge of the serial clock SCL the SO0 latch outputs the data on an MSB first basis from the SDA0 or SDA1 pin to the receiving device In the receiving device the data input from the SDA0 or SDA1 pin is taken into the SIO0 in synchronization with the rising edge of SCL 9 Start of transfer A serial transfer is started by setting transfer data i...

Page 379: ... L L 1 A5 A4 A3 A2 A1 A0 W ACK A6 2 3 4 5 6 7 8 D7 D6 D5 D4 D3 1 2 3 4 5 9 L L L L L SIO0 Address Master device operation Transfer line Slave device operation SIO0 Data H L L L L L L L H H H H SIO0 FFH Write SIO0 COI ACKD CMDD RELD CLD P27 SCL SDA0 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 Write SIO0 COI ACKD CMDD RELD CLD P27 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 CSIE0 P25 PM25 PM27 ...

Page 380: ...2 D1 D0 ACK D6 D7 2 3 4 5 6 7 8 D7 D6 D5 D4 D3 1 2 3 4 5 9 L L L L L L L SIO0 Address Master device operation Transfer line SIO0 Data H L L L L L L L H H H H SIO0 FFH SIO0 FFH Write SIO0 COI ACKD CMDD RELD CLD P27 SCL SDA0 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 Write SIO0 COI ACKD CMDD RELD CLD P27 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 CSIE0 P25 PM25 PM27 Slave device operation ...

Page 381: ... 1 D5 D4 D3 D2 D1 D0 ACK D6 D7 2 3 4 5 6 7 8 A6 A5 A4 A3 1 2 3 4 9 L L L L SIO0 Data Master device operation Transfer line SIO0 Address H L L L L H H H SIO0 FFH Write SIO0 COI ACKD CMDD RELD CLD P27 SCL SDA0 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 Write SIO0 COI ACKD CMDD RELD CLD P27 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 CSIE0 P25 PM25 PM27 Slave device operation SIO0 FFH ...

Page 382: ...ss L L L 1 A0 A1 A2 A3 A4 A5 A6 R ACK 2 3 4 5 6 7 8 D6 D7 D5 D4 D3 2 1 3 4 5 9 L L L SIO0 Address Master device operation Transfer line SIO0 FFH H L L L L L L L H H Write SIO0 COI ACKD CMDD RELD CLD P27 SCL SDA0 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 Write SIO0 COI ACKD CMDD RELD CLD P27 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 CSIE0 P25 PM25 PM27 Slave device operation SIO0 Data ...

Page 383: ... D0 D2 D3 D4 D5 D6 D7 ACK 2 3 4 5 6 7 8 D6 D7 D5 D4 D3 2 1 3 4 5 9 L L L SIO0 FFH Master device operation Transfer line SIO0 FFH H L L L L L L L L L L H H Write SIO0 COI ACKD CMDD RELD CLD P27 SCL SDA0 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 Write SIO0 COI ACKD CMDD RELD CLD P27 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 CSIE0 P25 PM25 PM27 Slave device operation SIO0 Data SIO0 Data ...

Page 384: ...n L L 1 D1 D0 D2 D3 D4 D5 D6 D7 NAK 2 3 4 5 6 7 8 A6 A5 A4 A3 1 2 3 4 9 L L SIO0 FFH Master device operation Transfer line SIO0 Address H L L L L L L H H Write SIO0 COI ACKD CMDD RELD CLD P27 SCL SDA0 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 Write SIO0 COI ACKD CMDD RELD CLD P27 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 CSIE0 P25 PM25 PM27 Slave device operation SIO0 Data ...

Page 385: ...output a start condition signal Set 1 in CLC of interrupt timing specify register SINT to drive the SCL pin high After setting CLC clear CLC to 0 and return the SCL pin to low If CLC remains 1 no serial clock is output If it is the master device which outputs the start condition and stop condition signals confirm that CLD is set to 1 after setting CLC to 1 a slave device may have set SCL to low wa...

Page 386: ...me control the low level width a in Figure 17 25 of the first serial clock at the timing used for setting the P27 output latch to 1 after execution of an SIO0 write instruction In addition if the acknowledge signal from the master is not output if data transmission from the slave is completed set 1 in the WREL flag of SINT and release the wait For these timings see Figure 17 23 Figure 17 25 Slave ...

Page 387: ... This is because SIO0 does not start operating if the SCL line is in the high impedance state while the instruction that writes data to SIO0 is executed until the next instruction is executed Therefore receive the data by manipulating the output latch of P27 by program as shown in Figure 17 26 For this timing refer to Figure 17 22 Figure 17 26 Slave Wait Release Reception Writing data to SIO0 Sett...

Page 388: ...data Note The serial transfer status is the status since data has been written to the serial I O shift register 0 SIO0 until the interrupt request flag CSIIF0 is set to 1 by completion of the serial transfer Preventive measure The above phenomenon can be avoided by modifying the program Before executing the wake up function execute the following program that clears the serial transfer status When ...

Page 389: ...CL pin in the input mode to protect the SCL line from adverse influence when the port mode is set by instruction 4 The P27 pin is set in the input mode when instruction 3 is executed 4 This instruction changes the mode from I2C bus mode to port mode 5 This instruction restores the I2C bus mode from the port mode 6 This instruction prevents the SDA0 pin from outputting a low level when instruction ...

Page 390: ...put latch by executing the bit manipulation instruction Figure 17 27 SCK0 SCL P27 Pin Configuration 2 In I2C bus mode The output level of the SCK0 SCL P27 pin is manipulated by the CLC bit of the interrupt timing specify register SINT 1 Set the serial operating mode register 0 CSIM0 SCL pin is set in the output mode and serial operation is enabled Set 1 to the P27 output latch SCL 0 while serial t...

Page 391: ...it of SCL Signal Remarks 1 This figure indicates the relation of the signals and does not indicate the internal circuit 2 CLC Bit 3 of interrupt timing specify register SINT CLC manipulated by bit manipulation instruction Wait request signal Serial clock low while transfer is stopped SCL ...

Page 392: ...392 MEMO ...

Page 393: ...nce the start bit of 8 bit data to undergo serial transfer is switchable between MSB and LSB connection is enabled with either start bit device The 3 wire serial I O mode is valid for connection of peripheral I O units and display controllers which incorporate a conventional synchronous serial interface such as the 75X XL 78K and 17K series 3 3 wire serial I O mode with automatic transmit receive ...

Page 394: ...Serial I O shift register 1 SIO1 Automatic data transmit receive address pointer ADTP Control register Timer clock select register 3 TCL3 Serial operating mode register 1 CSIM1 Automatic data transmit receive control register ADTC Automatic data transmit receive interval specify register ADTI Port mode register 2 PM2 Note Note Refer to Figure 6 5 6 7 Block Diagram of P20 P21 P23 to P26 and Figure ...

Page 395: ...ft Register 1 SIO1 Hand shake Serial Clock Counter Selector Selector SO1 P21 PM21 P21 Output Latch DIR DIR Buffer RAM Automatic Data Transmit Receive Address Pointer ADTP SCK1 P22 PM22 Internal Bus TRF P22 Output Latch Match ADTI0 ADTI4 Selector TO2 INTCSI1 Clear SIOI write Q R S Selector TCL 37 TCL 36 TCL 35 TCL 34 4 Timer Clock Select Register 3 fxx 2 fxx 28 Internal Bus ARLD CSIE1 DIR ATE CSIM ...

Page 396: ...RESET input makes SIO1 undefined Caution Do not write data to SIO1 while the automatic transmit receive function is activated 2 Automatic data transmit receive address pointer ADTP This register stores value of the number of transmit data bytes 1 while the automatic transmit receive function is activated As data is transferred received it is automatically decremented ADTP is set with an 8 bit memo...

Page 397: ...r 1 CSIM1 Automatic data transmit receive control register ADTC Automatic data transmit receive interval specify register ADTI 1 Timer clock select register 3 TCL3 This register sets the serial clock of serial interface channel 1 TCL3 is set with an 8 bit memory manipulation instruction RESET input sets TCL3 to 88H Remark Besides setting the serial clock of serial interface channel 1 TCL3 sets the...

Page 398: ...z Serial Interface Channel 1 Serial Clock Selection TCL37 TCL36 TCL35 TCL34 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 fXX 2 fXX 22 fXX 23 fXX 24 fXX 25 fXX 26 fXX 27 fXX 28 MCS 1 Setting prohibited fX 22 1 25 MHz fX 23 625 kHz fX 24 313 kHz fX 25 156 kHz fX 26 78 1 kHz fX 27 39 1 kHz fX 28 19 5 kHz MCS 0 fX 22 1 25 MHz fX 23 625 kHz fX 24 313 kHz fX 25 156 kHz fX 26 78 1 kHz ...

Page 399: ...ble 6 5 4 3 2 1 0 7 Symbol CSIM1 CSIE1 DIR ATE 0 0 0 CSIM11 CSIM10 CSIM11 0 1 Serial Interface Channel 1 Clock Selection Clock externally input to SCK1 pinNote 1 8 bit timer register 2 TM2 output SCK1 Input 1 Clock specified with bits 4 to 7 of timer clock select register 3 TCL3 CSIE1 0 CSIM10 0 1 FF68H 00H R W Address After Reset R W CSIM11 P20 PM21 P21 PM22 Note 3 Shift Register 1 Operation Seri...

Page 400: ...t care 6 5 4 3 2 1 0 7 Symbol ADTC RE ARLD ERCE ERR TRF STRB BUSY1 BUSY0 FF69H 00H R WNote 1 Address After Reset R W BUSY1 0 1 1 Busy Input Control Not using busy input Busy input enable active high Busy input enable active low BUSY0 0 1 STRB 0 1 Strobe Output Control Strobe output disable Strobe output enable TRF 1 Status of Automatic Transmit Receive FunctionNote 2 Detection of termination of au...

Page 401: ...ystem clock frequency fX or fX 2 2 fX Main system clock oscillation frequency 3 fSCK Serial clock frequency 26 36 26 28 0 5 fXX fXX fSCK 1 5 fSCK fXX fXX Data Transfer Interval Specification fXX 5 0 MHz Operation ADTI4 ADTI3 ADTI2 ADTI1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MinimumNote 2 18 4 s 0 5 fSCK 31 2 ...

Page 402: ...l clock frequency 0 5 fSCK 1 5 fSCK 26 28 fXX fXX 26 36 fXX fXX Data Transfer Interval Specification fXX 5 0 MHz Operation ADTI4 ADTI3 ADTI2 ADTI1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MinimumNote 223 2 s 0 5 fSCK 236 0 s 0 5 fSCK 248 8 s 0 5 fSCK 261 6 s 0 5 fSCK 274 4 s 0 5 fSCK 287 2 s 0 5 fSCK 300 0 s 0 5...

Page 403: ... 5 fSCK 1 5 fSCK 26 fXX 26 fXX Data Transfer Interval Specification fXX 2 5 MHz Operation ADTI4 ADTI3 ADTI2 ADTI1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MinimumNote 2 36 8 s 0 5 fSCK 62 4 s 0 5 fSCK 88 0 s 0 5 fSCK 113 6 s 0 5 fSCK 139 2 s 0 5 fSCK 164 8 s 0 5 fSCK 190 4 s 0 5 fSCK 216 0 s 0 5 fSCK 241 6 s 0 5...

Page 404: ...l clock frequency 26 fXX 26 fXX 28 fXX 36 fXX 0 5 fSCK 1 5 fSCK Data Transfer Interval Specification fXX 2 5 MHz Operation ADTI4 ADTI3 ADTI2 ADTI1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MinimumNote 446 4 s 0 5 fSCK 472 0 s 0 5 fSCK 497 6 s 0 5 fSCK 523 2 s 0 5 fSCK 548 8 s 0 5 fSCK 574 4 s 0 5 fSCK 600 0 s 0 5...

Page 405: ...e serial operating mode register 1 CSIM1 CSIM1 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM1 to 00H Notes 1 Can be used freely as port function 2 Can be used as P20 CMOS input output when only transmitter is used clear bit 7 RE of the automatic data transmit receive control register ADTC to 0 Remark Don t care PM Port mode register P Port output latch Operatio...

Page 406: ...tter is used clear bit 7 RE of ADTC to 0 Remark Don t care PM Port mode register P Port output latch 6 5 4 3 2 1 0 7 Symbol CSIM1 CSIE1 DIR ATE 0 0 0 CSIM11 CSIM10 CSIM11 0 1 Serial Interface Channel 1 Clock Selection Clock externally input to SCK1 pinNote 8 bit timer register 2 TM2 output 1 Clock specified with bits 4 to 7 of timer clock select register 3 TCL3 CSIM10 0 1 FF68H 00H R W Address Aft...

Page 407: ...clock SCK1 The transmit data is held in the SO1 latch and is output from the SO1 pin The receive data input to the SI1 pin is latched into SIO1 at the rising edge of SCK1 Upon termination of 8 bit transfer the SIO1 operation stops automatically and the interrupt request flag CSIIF1 is set Figure 18 6 3 Wire Serial I O Mode Timings Caution SO1 pin becomes low level by SIO1 write SI1 SCK1 1 2 3 4 5 ...

Page 408: ...SIO1 The SIO1 shift order remains unchanged Thus switching between MSB first and LSB first must be performed before writing data to the SIO1 4 Transfer start Serial transfer is started by setting transfer data to the serial I O shift register 1 SIO1 when the following two conditions are satisfied Serial interface channel 1 operation control bit CSIE1 1 Internal serial clock is stopped or SCK1 is a...

Page 409: ...s Handshake signals STB and BUSY are supported by hardware to transmit receive data continuously OSD On Screen Display LSI and peripheral LSI including LCD controller driver can be connected without difficulty 1 Register setting The 3 wire serial I O mode with automatic transmit receive function is set with the serial operating mode register 1 CSIM1 the automatic data transmit receive control regi...

Page 410: ...imer register 2 TM2 output SCK1 Input 1 Clock specified with bits 4 to 7 of timer clock select register 3 TCL3 CSIE1 0 CSIM10 0 1 FF68H 00H R W Address After Reset R W CSIM11 P20 PM21 P21 PM22 Note 3 Shift Register 1 Operation Serial Clock Counter Operation Control SI1 P20 Pin Function SCK1 P22 Pin Function 1 0 1 0 0 0 1 1 Note 2 Note 2 Note 2 Note 2 Count operation SI1 Input Operation stop Clear ...

Page 411: ... using busy input Busy input enable active high Busy input enable active low BUSY0 0 1 STRB 0 1 Strobe Output Control Strobe output disable Strobe output enable TRF 1 Status of Automatic Transmit Receive FunctionNote 2 Detection of termination of automatic transmission reception This bit is set to 0 upon suspension of automatic transmission reception or when ARLD 0 During automatic transmission re...

Page 412: ...X Main system clock oscillation frequency 3 fSCK Serial clock frequency fXX fXX 26 fXX fSCK 28 0 5 26 fXX 36 1 5 fSCK Data Transfer Interval Specification fXX 5 0 MHz Operation ADTI4 ADTI3 ADTI2 ADTI1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MinimumNote 2 18 4 s 0 5 fSCK 31 2 s 0 5 fSCK 44 0 s 0 5 fSCK 56 8 s 0 ...

Page 413: ...X fSCK 36 1 5 fXX fSCK Data Transfer Interval Specification fXX 5 0 MHz Operation ADTI4 ADTI3 ADTI2 ADTI1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MinimumNote 223 2 s 0 5 fSCK 236 0 s 0 5 fSCK 248 8 s 0 5 fSCK 261 6 s 0 5 fSCK 274 4 s 0 5 fSCK 287 2 s 0 5 fSCK 300 0 s 0 5 fSCK 312 8 s 0 5 fSCK 325 6 s 0 5 fSCK 3...

Page 414: ...sfer Interval Specification fXX 2 5 MHz Operation ADTI4 ADTI3 ADTI2 ADTI1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MinimumNote 2 36 8 s 0 5 fSCK 62 4 s 0 5 fSCK 88 0 s 0 5 fSCK 113 6 s 0 5 fSCK 139 2 s 0 5 fSCK 164 8 s 0 5 fSCK 190 4 s 0 5 fSCK 216 0 s 0 5 fSCK 241 6 s 0 5 fSCK 267 2 s 0 5 fSCK 292 8 s 0 5 fSCK ...

Page 415: ...X fSCK 36 1 5 fXX fSCK Data Transfer Interval Specification fXX 2 5 MHz Operation ADTI4 ADTI3 ADTI2 ADTI1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MinimumNote 446 4 s 0 5 fSCK 472 0 s 0 5 fSCK 497 6 s 0 5 fSCK 523 2 s 0 5 fSCK 548 8 s 0 5 fSCK 574 4 s 0 5 fSCK 600 0 s 0 5 fSCK 625 6 s 0 5 fSCK 651 2 s 0 5 fSCK 6...

Page 416: ... the automatic data transmit receive interval specify register ADTI 4 Write any value to the serial I O shift register 1 SIO1 transfer start trigger Caution Writing any value to SIO1 orders the start of automatic transmit receive operation and the written value has no meaning The following operations are automatically carried out when a and b are carried out After the buffer RAM data specified wit...

Page 417: ...sion reception mode operation timings and Figure 18 9 shows the operation flowchart Figure 18 10 shows the operation of the buffer RAM when 6 bytes of data are transmitted or received Figure 18 8 Basic Transmission Reception Mode Operation Timings Cautions 1 Because in the basic transmission reception mode the automatic transmit receive function writes reads data to from the buffer RAM after 1 byt...

Page 418: ...ol register ADTC Start Write transmit data in buffer RAM Set ADTP to the value pointer value obtained by subtracting 1 from the number of transmit data bytes Set the transmission reception operation interval time in ADTI Write any data to SIO1 Start trigger Write transmit data from buffer RAM to SIO1 Transmission reception operation Write receive data from SIO1 to buffer RAM Pointer value 0 No TRF...

Page 419: ...sion reception point Refer to Figure 18 10 b Transmission reception of the third byte is completed and transmit data 4 T4 is transferred from the buffer RAM to SIO1 When transmission of the fourth byte is completed the receive data 4 R4 is transferred from SIO1 to the buffer RAM and ADTP is decremented iii Completion of transmission reception Refer to Figure 18 10 c When transmission of the sixth ...

Page 420: ...n reception c Completion of transmission reception Receive data 1 R1 Receive data 2 R2 Receive data 3 R3 Transmit data 4 T4 Transmit data 5 T5 Transmit data 6 T6 FADFH FAC5H FAC0H Receive data 4 R4 SIO1 0 CSIIF1 2 ADTP 1 Receive data 1 R1 Receive data 2 R2 Receive data 3 R3 Receive data 4 R4 Receive data 5 R5 Receive data 6 R6 FADFH FAC5H FAC0H SIO1 1 CSIIF1 0 ADTP ...

Page 421: ...c transmission mode operation timings and Figure 18 12 shows the operation flowchart Figure 18 13 shows the operation of the buffer RAM when 6 bytes of data are transmitted or received Figure 18 11 Basic Transmission Mode Operation Timings Cautions 1 Because in the basic transmission mode the automatic transmit receive function reads data from the buffer RAM after 1 byte transmission an interval i...

Page 422: ...transmit receive control register ADTC Start Write transmit data in buffer RAM Set ADTP to the value pointer value obtained by subtracting 1 from the number of transmit data bytes Set the transmission reception operation interval time in ADTI Write any data to SIO1 Start trigger Write transmit data from buffer RAM to SIO1 Transmission operation Pointer value 0 No TRF 0 No End Yes Yes Decrement poi...

Page 423: ...ansferred from the buffer RAM to SIO1 ii 4th byte transmission point Refer to Figure 18 13 b Transmission of the third byte is completed and transmit data 4 T4 is transferred from the buffer RAM to SIO1 When transmission of the fourth byte is completed ADTP is decremented iii Completion of transmission Refer to Figure 18 13 c When transmission of the sixth byte is completed the interrupt request f...

Page 424: ...sion point c Completion of transmission Transmit data 1 T1 Transmit data 2 T2 Transmit data 3 T3 Transmit data 4 T4 Transmit data 5 T5 Transmit data 6 T6 FADFH FAC5H FAC0H SIO1 0 CSIIF1 2 ADTP 1 Transmit data 1 T1 Transmit data 2 T2 Transmit data 3 T3 Transmit data 4 T4 Transmit data 5 T5 Transmit data 6 T6 FADFH FAC5H FAC0H SIO1 1 CSIIF1 0 ADTP ...

Page 425: ...he P20 SI1 P23 STB and P24 BUSY pins can be used as ordinary input output ports The repeat transmission mode operation timing is shown in Figure 18 14 and the operation flowchart in Figure 18 15 Figure 18 16 shows the operation of the buffer RAM when 6 bytes of data are transmitted in the repeat transmission mode Figure 18 14 Repeat Transmission Mode Operation Timing Caution Since in the repeat tr...

Page 426: ...O shift register 1 Start Write transmit data in buffer RAM Set ADTP to the value pointer value obtained by subtracting 1 from the number of transmit data bytes Set the transmission reception operation interval time in ADTI Write any data to SIO1 Start trigger Write transmit data from buffer RAM to SIO1 Transmission operation Pointer value 0 No Yes Decrement pointer value Software Execution Hardwar...

Page 427: ...O1 ii Upon completion of transmission of 6 bytes Refer to Figure 18 16 b When transmission of the sixth byte is completed the interrupt request flag CSIIF1 is not set The first pointer value is set to ADTP again iii 7th byte transmission point Refer to Figure 18 16 c Transmit data 1 T1 is transferred from the buffer RAM to SIO1 again When transmission of the first byte is completed ADTP is decreme...

Page 428: ...ission of 6 bytes c 7th byte transmission point Transmit data 1 T1 Transmit data 2 T2 Transmit data 3 T3 Transmit data 4 T4 Transmit data 5 T5 Transmit data 6 T6 FADFH FAC5H FAC0H SIO1 0 CSIIF1 0 ADTP Transmit data 1 T1 Transmit data 2 T2 Transmit data 3 T3 Transmit data 4 T4 Transmit data 5 T5 Transmit data 6 T6 FADFH FAC5H FAC0H SIO1 0 CSIIF1 5 ADTP 1 ...

Page 429: ...t mode During restart of transmission reception remaining data can be transferred by setting CSIE1 to 1 and writing any data to the serial I O shift register 1 SIO1 Cautions 1 If the HALT instruction is executed during automatic transmission reception transfer is suspended and the HALT mode is set if during 8 bit data transfer When the HALT mode is cleared automatic transmission reception is resta...

Page 430: ...at 1 The system configuration between the master device and slave device in cases where the busy control option is used is shown in Figure 18 18 Figure 18 18 System Configuration When the Busy Control Option is Used The master device inputs the busy signal output by the slave device to pin BUSY P24 In sync with the fall of the serial clock the master device samples the input busy signal Even if th...

Page 431: ...busy signal becomes inactive the wait is canceled If the sampled busy signal is inactive sending or receiving of the next 8 bit data begins from the fall of the next serial clock cycle Furthermore the busy signal is asynchronous with the serial clock so even if the slave side inactivates the busy signal it takes nearly 1 clock cycle at the most until it is sampled again Also it takes another 0 5 c...

Page 432: ...l operation mode register 1 CSIM1 at 1 Set bit 2 STRB of the auto data send and receive control register ADTC at 1 Normally busy control and strobe control are used simultaneously as handshake signals In this case together with output of the strobe signal from pin STB P23 pin BUSY P24 can be sampled and sending or receiving can wait while the busy signal is being input If strobe control is not car...

Page 433: ...ution When TRF is cleared the SO1 pin becomes low level Remarks CSIIF1 Interrupt request flag TRF Bit 3 of the auto data send and receive control register ADTC SCK1 SO1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 STB BUSY SI1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 TRF Busy Input Valid Busy Input Clear CSIIF1 ...

Page 434: ... 2 clock cycles The master device side samples the busy signal in sync with the fall of the serial clock s front side If no bit slippage is occurring the busy signal will be inactive in sampling for 8 clock cycles If the busy signal is found to be active in sampling it is regarded as an occurrence of bit slippage error processing is executed bit 4 ERR of the auto data send and receive control regi...

Page 435: ...eive interval specification register ADTI and the CPU processing at the rising edge of the eighth serial clock Whether it depends on the ADTI or not can be selected by the setting of its bit 7 ADTI7 When it is set to 0 the interval depends only on the CPU processing When it is set to 1 the interval depends on the contents of the ADTI or CPU processing whichever is greater When the automatic transm...

Page 436: ...ocessing when the internal clock is operating CPU Processing Interval Time When using multiplication instruction Max 2 5TSCK 13TCPU When using division instruction Max 2 5TSCK 20TCPU External access 1 wait mode Max 2 5TSCK 9TCPU Other than above Max 2 5TSCK 7TCPU Remark TSCK 1 fSCK fSCK Serial clock frequency TCPU 1 fCPU fCPU CPU clock set by bits 0 to 2 PCC0 to PCC2 of the processor clock control...

Page 437: ...e selected so that the interval may be longer than the values shown as follows Table 18 3 Interval Timing Through CPU Processing when the external clock is operating CPU Processing Interval Time When using multiplication instruction 13TCPU When using division instruction 20TCPU External access 1 wait mode 9TCPU Other than above 7TCPU Remark TCPU 1 fCPU fCPU CPU clock set by the bits 0 to 2 PCC0 to...

Page 438: ...438 MEMO ...

Page 439: ...used by employing the dedicated UART baud rate generator 3 3 wire serial I O mode MSB LSB first switchable In this mode 8 bit data transfer is performed using three lines the serial clock SCK2 and serial data lines SI2 SO2 In the 3 wire serial I O mode simultaneous transmission and reception is possible increasing the data transfer processing speed Either the MSB or LSB can be specified as the sta...

Page 440: ... Item Configuration Register Transmit shift register TXS Receive shift register RXS Receive buffer register RXB Control register Serial operating mode register 2 CSIM2 Asynchronous serial interface mode register ASIM Asynchronous serial interface status register ASIS Baud rate generator control register BRGC Note Note Refer to Figure 6 15 Block Diagram of P70 and Figure 6 16 Block Diagram of P71 P...

Page 441: ...Control Circuit Receive Shift Register RXS Reception Control Circuit RxD SI2 P70 TxD SO2 P71 INTSR INTCSI2 CSIE2 CSIM 22 CSCK INTSER SCK Output Control Circuit Baud Rate Generator fxx fxx 210 Internal Bus SCK INTST Baud Rate Generator Control Register Note Serial Operating Mode Register 2 PE FE OVE Transmission Control Circuit PM71 ISRM ASCK SCK2 P72 PM72 Direction Control Circuit Transmit Shift R...

Page 442: ...ternal Bus MDL3 MDL2 MDL1 MDL0 Baud Rate Generator Control Register 4 TXE CSIE2 5 Bit Counter Selector Selector Decoder 1 2 Selector Transmit Clock 1 2 Selector Receive Clock Match Match MDL0 MDL3 5 Bit Counter RXE Start Bit Detection Selector fxx fxx 210 TPS0 TPS3 SCK ASCK SCK2 P72 4 4 Start Bit Sampling Clock ...

Page 443: ...Each time one byte of data is received new receive data is transferred from the receive shift register RXS If the data length is specified as 7 bits the receive data is transferred to bits 0 to 6 of RXB and the MSB of RXB is always set to 0 RXB is read with an 8 bit memory manipulation instruction It cannot be written to RXB value is FFH after RESET input Caution Since RXB and the transmit shift r...

Page 444: ...interface channel 2 is used in the 3 wire serial I O mode CSIM2 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM2 to 00H Figure 19 3 Serial Operating Mode Register 2 Format Cautions 1 Ensure that bits 0 and 3 to 6 are set to 0 2 When UART mode is selected CSIM2 should be set to 00H 6 5 4 3 2 1 0 7 Symbol CSIM2 CSIE2 0 0 0 0 CSIM 22 CSCK 0 FF72H 00H R W Address Aft...

Page 445: ... ISRM SCK FF70H 00H R W Address After Reset R W SCK 0 1 Clock Selection in Asynchronous Serial Interface Mode Input clock from off chip to ASCK pin Dedicated baud rate generator outputNote ISRM 0 1 Control of Reception Completion Interrupt Request in Case of Error Generation Reception completion interrupt request generated in case of error generation Reception completion interrupt request not gene...

Page 446: ...ASCK Pin Functions P71 SO2 TxD Pin Functions P70 SI2 RxD Pin Functions Shift Clock Start Bit TXE RXE SCK CSIE2 CSIM22 CSCK PM70 P70 PM71 P71 PM72 P72 ASIM CSIM2 0 0 0 1 1 0 1 1 1 1 Note2 Note2 0 1 0 1 MSB LSB Internal clock SI2 SI2 SO2 CMOS output SCK2 output Other than above Setting prohibited Note2 Note2 SO2 CMOS output P72 SCK2 ASCK Pin Functions P71 SO2 TxD Pin Functions P70 SI2 RxD Pin Functi...

Page 447: ...nous serial interface mode ASIS is read with a 8 bit memory manipulation instruction In 3 wire serial I O mode the contents of the ASIS are undefined RESET input sets ASIS to 00H Figure 19 5 Asynchronous Serial Interface Status Register Format PE 6 5 4 3 2 1 0 7 Symbol ASIS 0 0 0 0 0 FE OVE FF71H 00H R Address After Reset R W OVE 0 1 Overrun Error Flag Overrun error not generated Overrun error gen...

Page 448: ...mode Remarks 1 fSCK 5 bit counter source clock 2 k Value set in MDL0 to MDL3 0 k 14 Baud Rate Generator Input Clock Selection MDL3 MDL2 MDL1 MDL0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 fSCK 16 fSCK 17 fSCK 18 fSCK 19 fSCK 20 fSCK 21 fSCK 22 fSCK 23 fSCK 24 fSCK 25 fSCK 26 fSCK 27 fSCK 28 fSCK 29 fSCK 30 fSCKNo...

Page 449: ... fXX 26 fX 26 78 1 kHz fX 27 39 1 kHz 7 1 1 0 0 fXX 27 fX 27 39 1 kHz fX 28 19 5 kHz 8 1 1 0 1 fXX 28 fX 28 19 5 kHz fX 29 9 8 kHz 9 1 1 1 0 fXX 29 fX 29 9 8 kHz fX 210 4 9 kHz 10 Other than above Setting prohibited Caution When data is written to BRGC during a communication operation baud rate generator output is disrupted and communication cannot be performed normally Therefore data must not be ...

Page 450: ...MDL0 to MDL3 0 k 14 Table 19 3 Relation between Main System Clock and Baud Rate fx 5 0 MHz fx 4 19 MHz MCS 1 MCS 0 MCS 1 MCS 0 BRGC Set Value Error BRGC Set Value Error BRGC Set Value Error BRGC Set Value Error 75 00H 1 73 0BH 1 14 EBH 1 14 110 06H 0 88 E6H 0 88 03H 2 01 E3H 2 01 150 00H 1 73 E0H 1 73 EBH 1 14 DBH 1 14 300 E0H 1 73 D0H 1 73 DBH 1 14 CBH 1 14 600 D0H 1 73 C0H 1 73 CBH 1 14 BBH 1 14...

Page 451: ... from the ASCK pin is obtained with the following expression Baud rate Hz fASCK Frequency of clock input to ASCK pin k Value set in MDL0 to MDL3 0 k 14 Table 19 4 Relation between ASCK Pin Input Frequency and Baud Rate When BRGC is set to 00H Baud Rate bps ASCK Pin Input Frequency 75 2 4 kHz 110 3 52 kHz 150 4 8 kHz 300 9 6 kHz 600 19 2 kHz 1200 38 4 kHz 2400 76 8 kHz 4800 153 6 kHz 9600 307 2 kHz...

Page 452: ...2 TxD and P72 SCK2 ASCK pins can be used as normal input output ports 1 Register setting Operation stop mode settings are performed using serial operating mode register 2 CSIM2 and the asynchronous serial interface mode register ASIM a Serial operating mode register 2 CSIM2 CSIM2 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM2 to 00H Caution Ensure that bits 0 a...

Page 453: ...mory manipulation instruction RESET input sets ASIM to 00H SL 6 5 4 3 2 1 0 7 Symbol ASIM TXE RXE PS1 PS0 CL ISRM SCK FF70H 00H R W Address After Reset R W RXE 0 1 Receive Operation Control Receive operation stopped Receive operation enabled TXE 0 1 Transmit Operation Control Transmit operation stopped Transmit operation enabled ...

Page 454: ...med using serial operating mode register 2 CSIM2 the asynchronous serial interface mode register ASIM the asynchronous serial interface status register ASIS and the baud rate generator control register BRGC a Serial operating mode register 2 CSIM2 CSIM2 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM2 to 00H When the UART mode is selected 00H should be set in CSI...

Page 455: ... from off chip to ASCK pin Dedicated baud rate generator outputNote ISRM 0 1 Control of Reception Completion Interrupt Request in Case of Error Generation Reception completion interrupt request generated in case of error generation Reception completion interrupt request not generated in case of error generation SL Transmit Data Stop Bit Length Specification CL 1 Character Length Specification 7 bi...

Page 456: ... of the asynchronous serial interface mode register ASIM only single stop bit detection is performed during reception PE 6 5 4 3 2 1 0 7 Symbol ASIS 0 0 0 0 0 FE OVE FF71H 00H R Address After Reset R W OVE 0 1 Overrun Error Flag Overrun error not generated Overrun error generatedNote 1 When next receive operation is completed before data from receive buffer register is read FE 0 1 Framing Error Fl...

Page 457: ...tinued Baud Rate Generator Input Clock Selection MDL3 MDL2 MDL1 MDL0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 fSCK 16 fSCK 17 fSCK 18 fSCK 19 fSCK 20 fSCK 21 fSCK 22 fSCK 23 fSCK 24 fSCK 25 fSCK 26 fSCK 27 fSCK 28 fSCK 29 fSCK 30 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 6 5 4 3 2 1 0 7 Symbol BRGC TPS3 TPS2 TPS1 TPS0 MDL3 MDL...

Page 458: ...1 kHz 7 1 1 0 0 fXX 27 fX 27 39 1 kHz fX 28 19 5 kHz 8 1 1 0 1 fXX 28 fX 28 19 5 kHz fX 29 9 8 kHz 9 1 1 1 0 fXX 29 fX 29 9 8 kHz fX 210 4 9 kHz 10 Other than above Setting prohibited Caution When a data is written to BRGC during a communication operation baud rate generator output is disrupted and communication cannot be performed normally Therefore data must not be written to BRGC during a commu...

Page 459: ...in MDL0 to MDL3 0 k 14 Table 19 5 Relation between Main System Clock and Baud Rate fx 5 0 MHz fx 4 19 MHz MCS 1 MCS 0 MCS 1 MCS 0 BRGC Set Value Error BRGC Set Value Error BRGC Set Value Error BRGC Set Value Error 75 00H 1 73 0BH 1 14 EBH 1 14 110 06H 0 88 E6H 0 88 03H 2 01 E3H 2 01 150 00H 1 73 E0H 1 73 EBH 1 14 DBH 1 14 300 E0H 1 73 D0H 1 73 DBH 1 14 CBH 1 14 600 D0H 1 73 C0H 1 73 CBH 1 14 BBH 1...

Page 460: ...om the ASCK pin is obtained with the following expression Baud rate Hz where fASCK Frequency of clock input to ASCK pin k Value set in MDL0 to MDL3 0 k 14 Table 19 6 Relation between ASCK Pin Input Frequency and Baud Rate When BRGC is set to 00H Baud Rate bps ASCK Pin Input Frequency 75 2 4 kHz 110 3 52 kHz 150 4 8 kHz 300 9 6 kHz 600 19 2 kHz 1200 38 4 kHz 2400 76 8 kHz 4800 153 6 kHz 9600 307 2 ...

Page 461: ... data frame are specified with asynchronous serial interfaece mode register ASIM When 7 bits are selected as the number of character bits only the lower 7 bits bits 0 to 6 are valid in transmission the most significant bit bit 7 is ignored and in reception the most significant bit bit 7 is always 0 The serial transfer rate is set with ASIM and the baud rate generator control register BRGC If a ser...

Page 462: ...a is counted If it is odd a parity error occurs ii Odd parity Transmission Conversely to the situation with even parity the number of bits with a value of 1 including the parity bit in the transmit data is controlled to be odd The value of the parity bit is as follows Number of bits with a value of 1 in transmit data is odd 0 Number of bits with a value of 1 in transmit data is even 1 Reception Th...

Page 463: ...al Interface Transmission Completion Interrupt Request Generation Timing a Stop bit length 1 b Stop bit length 2 Caution Do not rewrite the asynchronous serial interface mode register ASIM during a transmit operation If rewriting of the ASIM register is performed during transmission subsequent transmit operations may not be possible the normal state is restored by RESET input Whether transmission ...

Page 464: ... of one frame of data ends When one frame of data has been received the receive data in the shift register is transferred to the receive buffer register RXB and a reception completion interrupt request INTSR is generated Even if an error is generated the receive data in which the error was generated is transferred to RXB If bit 1 ISRM of ASIM is cleared 0 when the error is generated INTSR will be ...

Page 465: ...ceive Error Causes Receive Errors Cause Parity error Transmission time parity specification and reception data parity do not match Framing error Stop bit not detected Overrun error Reception of next data is completed before data is read from receive register buffer Figure 19 10 Receive Error Timing Note If a reception error is generated while bit 1 ISRM of asynchronous serial interface mode regist...

Page 466: ...he state of the receive buffer register RXB and whether the receive completion interrupt request INTSR is generated depend on the timing of clearing Figure 19 11 shows the timing Figure 19 11 The State of Receive Buffer Register RXB and Whether the Receive Completion Interrupt Request INTSR is Generated When RXE is set to 0 at a time indicated by 1 RXB holds the previous data and does not generate...

Page 467: ...e performed using serial operating mode register 2 CSIM2 the asynchronous serial interface mode register ASIM and the baud rate generator control register BRGC a Serial operating mode register 2 CSIM2 CSIM2 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM2 to 00H Caution Ensure that bits 0 and 3 to 6 are set to 0 6 5 4 3 2 1 0 7 Symbol CSIM2 CSIE2 0 0 0 0 CSIM 22 ...

Page 468: ... Control of Reception Completion Interrupt Request in Case of Error Generation Reception completion interrupt request generated in case of error generation Reception completion interrupt request not generated in case of error generation SL Transmit Data Stop Bit Length Specification CL 1 Character Length Specification 7 bits 8 bits RXE 0 1 Receive Operation Control Receive operation stopped Receiv...

Page 469: ... Rate Generator Input Clock Selection MDL3 MDL2 MDL1 MDL0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 fSCK 16 fSCK 17 fSCK 18 fSCK 19 fSCK 20 fSCK 21 fSCK 22 fSCK 23 fSCK 24 fSCK 25 fSCK 26 fSCK 27 fSCK 28 fSCK 29 fSCK 30 fSCK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 6 5 4 3 2 1 0 7 Symbol BRGC TPS3 TPS2 TPS1 TPS0 MDL3 M...

Page 470: ...1 kHz 7 1 1 0 0 fXX 27 fX 27 39 1 kHz fX 28 19 5 kHz 8 1 1 0 1 fXX 28 fX 28 19 5 kHz fX 29 9 8 kHz 9 1 1 1 0 fXX 29 fX 29 9 8 kHz fX 210 4 9 kHz 10 Other than above Setting prohibited Caution When a Data is written to BRGC during a communication operation baud rate generator output is disrupted and communication cannot be performed normally Therefore data must not be written to BRGC during a commu...

Page 471: ...becomes 1 2 of the source clock frequency for the 5 bit counter ii When the baud rate generator is used Select a serial clock frequency with TPS0 to TPS3 Be sure then to set MDL0 to MDL3 to 1 1 1 1 The serial clock frequency is calculated by the following formula Serial clock frequency Hz Remarks 1 fX Main system clock oscillation frequency 2 fXX Main system clock frequency fX or fX 2 3 n Value se...

Page 472: ...ith the fall of the serial clock SCK2 Then transmit data is held in the SO2 latch and output from the SO2 pin Also receive data input to the SI2 pin is latched in the receive buffer register RXB SIO2 on the rise of SCK2 At the end of an 8 bit transfer the operation of the TXS SIO2 or RXS stops automatically and the interrupt request flag SRIF is set Figure 19 12 3 Wire Serial I O Mode Timing SI2 S...

Page 473: ...2 The TXS SIO2 shift order remains unchanged Thus switching between MSB first and LSB first must be performed before writing data to the TXS SIO2 4 Transfer start Serial transfer is started by setting transfer data to the transmission shift register TXS SIO2 when the following two conditions are satisfied Serial interface channel 2 operation control bit CSIE2 1 Internal serial clock is stopped or ...

Page 474: ...ed to 0 As a result it is judged that no reception error has occurred and INTSR which must not occur occurs Figure 19 14 illustrates this operation Figure 19 14 Reception Completion Interrupt Request Generation Timing when ISRM 1 Remark ISRM Bit 1 of asynchronous serial interface mode register ASIM fSCK Source clock of 5 bit counter of baud rate generator RXB Receive buffer register To avoid this ...

Page 475: ...C 1 baud rate T2 Time of 2 clocks of source clock fSCK of 5 bit counter selected by BRGC Example of preventive measures Here is an example of the above preventive measures Condition fX 5 0 MHz Processor clock control register PCC 00H Oscillation mode select register OSMS 01H Baud rate generator control register BRGC B0H 2400 bps selected as baud rate TCY 0 4 µs tCY 0 2 µs T1 1 416 7 µs 2400 T2 12 ...

Page 476: ... 2 Example Occurrence of INTSER EI Main processing 7 clocks of CPU clock MIN time from interrupt request to servicing Instructions equivalent to 2205 CPU clocks MIN are necessary MOV A RXB RETI UART reception error interrupt INTSER servicing ...

Page 477: ...timer interrupt requests or external interrupt request generation then output externally This is called the real time output function The pins that output data externally are called real time output ports By using a real time output a signal which has no jitter can be output This port is therefore suitable for control of stepping motors etc Port mode real time output port mode can be specified bit...

Page 478: ...ster Port mode register 12 PM12 Real time output port mode register RTPM Real time output port control register RTPC Figure 20 1 Real time Output Port Block Diagram Internal Bus Real time Output Port Control Register EXTR BYTE Output Trigger Control Circuit Real time Output Buffer Register Higher 4 Bits RTBH Real time Output Buffer Register Lower 4 Bits RTBL Output Latch P120 P127 Real time Output...

Page 479: ...r RTBH Table 20 2 shows operations during manipulation of RTBL and RTBH Figure 20 2 Real time Output Buffer Register Configuration Table 20 2 Operation in Real time Output Buffer Register Manipulation In Read Note1 In Write Note2 Higher 4 Bits Lower 4 Bits Higher 4 Bits Lower 4 Bits RTBL RTBH RTBL Invalid RTBL RTBH RTBH RTBL RTBH Invalid RTBL RTBH RTBL RTBH RTBL RTBH RTBH RTBL RTBH RTBL Notes 1 On...

Page 480: ...mode port mode bit wise RTPM is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets this register to 00H Figure 20 4 Real time Output Port Mode Register Format Cautions 1 When using these bits as a real time output port set the ports to which real time output is performed to the output mode clear the corresponding bit of the port mode register 12 PM12 to 0 2 In the port spec...

Page 481: ...igure 20 5 Real time Output Port Control Register Format Table 20 3 Real time Output Port Operating Mode and Output Trigger BYTE EXTR Operating Mode RTBH Port Output RTBL Port Output 0 INTTM2 INTTM1 1 INTTM1 INTP2 0 INTTM1 1 INTP2 7 0 Symbol RTPC 6 0 5 0 4 0 3 0 2 0 1 BYTE 0 EXTR Address FF36H 00H After Reset R W R W EXTR 0 1 Real time Output Control by INTP2 INTP2 not specified as real time outpu...

Page 482: ...482 CHAPTER 20 REAL TIME OUTPUT PORT MEMO ...

Page 483: ...kable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specify flag register PR0L PR0H PR1L Multiple high priority interrupts can be applied to low priority interrupts If two or more interrupts with the same priority are simultaneously generated each interrupts has a predetermined priority see Table 21 1 A standby release sig...

Page 484: ...r End of serial interface channel 1 transfer Serial interface channel 2 UART reception error generation End of serial interface channel 2 UART reception End of serial interface channel 2 3 wire transfer End of serial interface channel 2 UART transfer 0 INTWDT B 8 INTCSI0 0014H 9 INTCSI1 0016H 10 INTSER 0018H 11 001AH INTSR INTCSI2 12 INTST 001CH Interrupt Type Default Priority Internal External Ve...

Page 485: ...of 8 bit timer event counter 2 match signal 18 INTAD End of A D converter conversion 0028H Software BRK BRK instruction execution 003EH E Interrupt Type Default Priority Internal External Vector Table Address Basic Configuration Type Note 1 Note 2 14 INTTM00 0020H 15 INTTM01 0022H 17 INTTM2 0026H 13 INTTM3 001EH Notes 1 Default priorities are intended for two or more simultaneously generated maska...

Page 486: ...S External Interrupt Mode Register INTM0 Internal Bus IE PR ISP MK IF Interrupt Request Priority Control Circuit Vector Table Address Generator Standby Release Signal Internal Bus Priority Control Circuit Vector Table Address Generator Standby Release Signal Interrupt Request Figure 21 1 Basic Configuration of Interrupt Function 1 2 A Internal non maskable interrupt B Internal maskable interrupt C...

Page 487: ...ctor Interrupt Request IE PR ISP MK IF Priority Control Circuit Vector Table Address Generator Standby Release Signal Internal Bus Figure 21 1 Basic Configuration of Interrupt Function 2 2 D External maskable interrupt except INTP0 E Software interrupt Remark IF Interrupt request flag IE Interrupt enable flag ISP Inservice priority flag MK Interrupt mask flag PR Priority specify flag ...

Page 488: ...ponding to interrupt request sources Table 21 2 Various Flags Corresponding to Interrupt Request Sources Interrupt Source Interrupt Request Flag Interrupt Mask Flag Priority Specify Flag Register Register Register INTWDT TMIF4 IF0L TMMK4 MK0L TMPR4 PR0L INTP0 PIF0 PMK0 PPR0 INTP1 PIF1 PMK1 PPR1 INTP2 PIF2 PMK2 PPR2 INTP3 PIF3 PMK3 PPR3 INTP4 PIF4 PMK4 PPR4 INTP5 PIF5 PMK5 PPR5 INTP6 PIF6 PMK6 PPR6...

Page 489: ... request is generated or an instruction is executed It is cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon application of RESET input IF0L IF0H and IF1L are set with a 1 bit or 8 bit memory manipulation instruction If IF0L and IF0H are used as a 16 bit register IF0 use a 16 bit memory manipulation instruction for the setting RESET input sets these re...

Page 490: ...e becomes undefined 2 Because port 0 has a dual function as the external interrupt request input when the output level is changed by specifying the output mode of the port function an interrupt request flag is set Therefore 1 should be set in the interrupt mask flag before using the output mode 3 Set always 1 in MK1L bits 3 through 6 2 Interrupt mask flag registers MK0L MK0H MK1L The interrupt mas...

Page 491: ...H R W PR Cautions 1 If a watchdog timer is used in watchdog timer mode 1 set TMPR4 flag to 1 2 Set always 1 in PR1L bits 3 through 7 3 Priority specify flag registers PR0L PR0H and PR1L The priority specify flag is used to set the corresponding maskable interrupt priority orders PR0L PR0H and PR1L are set with a 1 bit or 8 bit memory manipulation instruction If PR0L and PR0H are used as a 16 bit r...

Page 492: ... 0 1 ES20 0 0 1 1 INTP2 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES31 0 1 0 1 ES30 4 External interrupt mode register INTM0 INTM1 These registers set the valid edge for INTP0 to INTP6 INTM0 and INTM1 are set by 8 bit memory manipulation instructions RESET input sets these registers to 00H Figure 21 5 External Interrupt Mode Register 0 Format Ca...

Page 493: ...41 0 ES40 0 1 0 1 ES40 0 0 1 1 INTP4 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES51 0 1 0 1 ES50 0 0 1 1 INTP5 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES61 0 1 0 1 ES60 0 0 1 1 INTP6 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES71 0 1 0 1 E...

Page 494: ...the HALT mode Remarks 1 N Value N 0 to 4 at bits 0 to 2 PCC0 to PCC2 of processor clock control register PCC 2 fXX Main system clock frequency fX or fX 2 3 fX Main system clock oscillation frequency 4 MCS Oscillation mode selection register OSMS bit 0 5 Values in parentheses when operated with fX 5 0 MHz 5 Sampling clock select register SCS This register is used to set the valid edge clock samplin...

Page 495: ...al to or twice the sampling cycle tSMP When the sampled INTP0 input level is active twice in succession the noise eliminator sets interrupt request flag PIF0 to 1 Figure 21 8 shows the noise eliminator input output timing Figure 21 8 Noise Eliminator Input Output Timing during rising edge detection a When input is less than the sampling cycle tSMP tSMP Sampling Clock INTP0 PIF0 When INTP0 level be...

Page 496: ...ck and the IE flag is reset to 0 If a maskable interrupt request is acknowledged contents of the priority specify flag of the acknowledged interrupt are transferred to the ISP flag Contents of the PSW is also saved into the stack with the PUSH PSW instruction It is reset from the stack with the RETI RETB and POP PSW instructions RESET input sets PSW to 02H Figure 21 9 Program Status Word Configura...

Page 497: ...branched A new non maskable interrupt request generated during execution of a non maskable interrupt servicing program is acknowledged after the current execution of the non maskable interrupt servicing program is terminated following RETI instruction execution and one main routine instruction is executed If a new non maskable interrupt request is generated twice or more during non maskable interr...

Page 498: ...ssing Interval timer Start No Yes Yes No Yes No Yes No Yes No Figure 21 10 Flowchart of Generation from Non Maskable Interrupt Request to Acknowledgment WDTM Watchdog timer mode register WDT Watchdog timer Figure 21 11 Non Maskable Interrupt Request Acknowledge Timing TMIF4 Watchdog timer interrupt request flag Instruction Instruction CPU Instruction TMIF4 PSW and PC Save Jump to Interrupt Servici...

Page 499: ... interrupt servicing program execution Main Routine NMI Request 1 1 Instruction Execution NMI Request 1 is executed NMI Request 2 is reserved Reserved NMI Request 2 is processed NMI Request 2 Main Routine NMI Request 1 1 Instruction Execution NMI Request 2 NMI Request 1 is executed NMI Request 2 is reserved NMI Request 3 is reserved NMI Request 2 is processed NMI Request 3 NMI requests 3 is not ac...

Page 500: ... is generated just before a divide instruction the wait time is maximized Remark 1 clock fCPU CPU clock If two or more maskable interrupt requests are generated simultaneously the request specified for higher priority with the priority specify flag is acknowledged first If two or more requests are specified for the same priority with priority specify flag the interrupt request with higher default ...

Page 501: ... interrupt of low priority Start IF 1 MK 0 PR 0 Any Simultaneously generated PR 0 interrupt requests Any Simultaneously generated high priority interrupt requests IE 1 ISP 1 Vectored interrupt servicing Interrupt request reserve Interrupt request reserve Interrupt request reserve Interrupt request reserve Interrupt request reserve Interrupt request reserve Interrupt request reserve Vectored interr...

Page 502: ...ng Maximum Time fCPU 1 Instruction Divide Instruction PSW and PC Save Jump to Interrupt Servicing 6 Clocks Interrupt Servicing Program 33 Clocks 32 Clocks CPU Processing IF PR 1 IF PR 0 25 Clocks fCPU 1 Remark 1 clock fCPU CPU clock Instruction Instruction PSW and PC Save Jump to Interrupt Servicing 6 Clocks Interrupt Servicing Program 8 Clocks 7 Clocks CPU Processing IF PR 1 IF PR 0 ...

Page 503: ...y If an interrupt request of the same priority as or a higher priority than the interrupt currently being serviced is generated it is acknowledged as a multiple interrupt If an interrupt request of the priority lower than the interrupt currently being serviced is generated it is not acknowledged as a multiple interrupt An interrupt request that is not acknowledged due to interrupt disable or low p...

Page 504: ...terrupt request acknowledgment is enabled PR 0 High priority level PR 1 Low priority level IE 0 Interrupt request acknowledgment disabled Example 2 A multiple interrupt is not generated with priority control Interrupt request INTyy generated while servicing interrupt INTxx is not acknowledged because it has a lower priority than INTxx and a multiple interrupt is not generated The INTyy request is ...

Page 505: ...3 A multiple interrupt is not generated because interrupt is disabled Because interrupts are disabled during interrupt INTxx servicing EI instruction is not issued interrupt request INTyy is not acknowledged and a multiple interrupt is not generated INTyy request is reserved and acknowledged after execution of one main processing instruction PR 0 High priority level IE 0 Interrupt request acknowle...

Page 506: ... PR1L INTM0 INTM1 registers Caution The BRK instruction is not an interrupt request reserve instruction shown above However in the case of software interrupt that is started up with the execution of the BRK instruction the IE flag is cleared to 0 Therefore interrupts are not acknowledged even when a maskable interrupt request is issued during the execution of the BRK instruction However non maskab...

Page 507: ...actors Test Input Factors Name Trigger INTWT Watch timer overflow Internal INTPT4 Falling edge detection at port 4 External Figure 21 18 Basic Configuration of Test Function Remark IF test input flag MK test mask flag 21 5 1 Registers controlling the test function The test function is controlled by the following three registers Interrupt request flag register 1L IF1L Interrupt mask flag register 1...

Page 508: ...able at the time the standby mode is released by the watch timer It is set by a 1 bit memory manipulation instruction and 8 bit memory manipulation instruction It is set to FFH by the RESET signal input Figure 21 20 Format of Interrupt Mask Flag Register 1L Caution Be sure to set bits 3 through 6 to 1 7 WTMK Symbol MK1L 6 1 5 1 4 0 3 0 2 ADMK 1 TMMK2 0 TMMK1 Address FFE6H FFH When Reset R W R W 0 ...

Page 509: ...ection is used be sure to clear KRIF to 0 not cleared to 0 automatically 21 5 2 Test input signal acknowledge operation 1 Internal test signal The internal test input signal INTWT is generated with watch timer overflow and the WTIF flag is set If not masked with bit 7 WTMK of interrupt mask flag register 1L MK1L at this time a standby release signal is generated The watch function is available by ...

Page 510: ...510 MEMO ...

Page 511: ...ata bus P40 to P47 A8 to A15 Address bus P50 to P57 RD Read strobe signal P64 WR Write strobe signal P65 WAIT Wait signal P66 ASTB Address strobe signal P67 Table 22 2 State of Ports 4 to 6 Pins in External Memory Expansion Mode Ports and bits Port 4 Port 5 Port 6 Modes 0 7 0 1 2 3 4 5 6 7 0 3 4 7 Single chip mode Port Port Port Port 256 byte expansion mode Address data Port Port RD WR WAIT ASTB 4...

Page 512: ...0H FADFH FAC0H FABFH FA80H FA7FH 8000H 7FFFH 0000H Reserved Internal Buffer RAM Reserved Full Address Mode when MM2 MM0 111 Single chip Mode 16 Kbyte Expansion Mode when MM2 MM0 101 5000H 4FFFH 4100H 40FFH 4000H 3FFFH 4 Kbyte Expansion Mode when MM2 MM0 100 256 byte Expansion Mode when MM2 MM0 011 FFFFH SFR Internal High Speed RAM FF00H FEFFH FB00H FAFFH FAE0H FADFH FAC0H FABFH FA80H FA7FH A000H 9...

Page 513: ...FH 0000H Reserved Internal Buffer RAM Reserved Full Address Mode when MM2 MM0 111 Single chip Mode 16 Kbyte Expansion Mode when MM2 MM0 101 9000H 8FFFH 8100H 80FFH 8000H 7FFFH 4 Kbyte Expansion Mode when MM2 MM0 100 256 byte Expansion Mode when MM2 MM0 011 FFFFH SFR Internal High Speed RAM FF00H FEFFH FB00H FAFFH FAE0H FADFH FAC0H FABFH FA80H FA7FH E000H DFFFH 0000H Reserved Internal Buffer RAM Re...

Page 514: ... and internal PROM are 48 Kbytes FFFFH SFR Internal High Speed RAM FF00H FEFFH FB00H FAFFH FAE0H FADFH FAC0H FABFH FA80H FA7FH D000H CFFFH C100H C0FFH C000H BFFFH 0000H Reserved Internal Buffer RAM Reserved Full Address Mode when MM2 MM0 111 or 16 Kbyte Expansion Mode when MM2 MM0 101 4 Kbyte Expansion Mode when MM2 MM0 100 Single chip Mode 256 byte Expansion Mode when MM2 MM0 011 ...

Page 515: ...M size to less than 56 Kbytes by the memory size switching register IMS SFR Internal High Speed RAM FF00H FEFFH FB00H FAFFH FAE0H FADFH FAC0H FABFH F800H F7FFH F400H F3FFH F000H EFFFH E100H F0FFH E000H DFFFH 0000H Reserved Internal Buffer RAM Reserved Internal Expansion RAM Full Address Mode when MM2 MM0 111 or 16 Kbyte Expansion Mode when MM2 MM0 101 4 Kbyte Expansion Mode when MM2 MM0 100 256 by...

Page 516: ...one wait state insertion Setting prohibited Wait control by external wait pin 22 2 External Device Expansion Function Control Register The external device expansion function is controlled by the memory expansion mode register MM and memory size switching register IMS 1 Memory expansion mode register MM MM sets the wait count and external expansion area and also sets the input output of port 4 MM i...

Page 517: ...witching register IMS This register specifies the internal memory size In principle use IMS in a default status However when using the external device expansion function with the µPD78058 set IMS so that the internal ROM capacity is 56 Kbytes or lower IMS is set with an 8 bit memory manipulation instruction RESET input sets this register to the value indicated in Table 22 3 Figure 22 3 Memory Size...

Page 518: ... not output maintains high level 3 WAIT pin Alternate function P66 External wait signal input pin When the external wait is not used the WAIT pin can be used as an input output port During internal memory access the external wait signal is ignored 4 ASTB pin Alternate function P67 Address strobe signal output pin Timing signal is output without regard to the data accesses and instruction fetches f...

Page 519: ...W0 0 0 setting b Wait PW1 PW0 0 1 setting c External wait PW1 PW0 1 1 setting ASTB RD Lower Address Operation Code AD0 AD7 A8 A15 Higher Address WAIT ASTB RD AD0 AD7 A8 A15 Lower Address Operation Code Higher Address Internal Wait Signal 1 clock wait ASTB RD AD0 AD7 A8 A15 Lower Address Operation Code Higher Address ...

Page 520: ... PW0 0 0 setting b Wait PW1 PW0 0 1 setting c External wait PW1 PW0 1 1 setting ASTB RD Lower Address Read Data AD0 AD7 A8 A15 Higher Address WAIT ASTB RD AD0 AD7 A8 A15 Lower Address Read Data Higher Address Internal Wait Signal 1 clock wait Higher Address ASTB RD AD0 AD7 A8 A15 Lower Address Read Data ...

Page 521: ... setting b Wait PW1 PW0 0 1 setting c External wait PW1 PW0 1 1 setting ASTB WR Higher Address AD0 AD7 A8 A15 WAIT Hi Z Lower Address Write Data ASTB WR AD0 AD7 A8 A15 Lower Address Write Data Higher Address Internal Wait Signal 1 clock wait Hi Z ASTB WR AD0 AD7 A8 A15 Lower Address Write Data Hi Z Higher Address ...

Page 522: ...t PW1 PW0 0 1 setting c External wait PW1 PW0 1 1 setting ASTB RD WR Higher Address AD0 AD7 A8 A15 WAIT Hi Z Lower Address Write Data Read Data Lower Address Higher Address Internal Wait Signal 1 clock wait Hi Z ASTB RD WR AD0 AD7 A8 A15 Write Data Read Data ASTB RD WR AD0 AD7 A8 A15 Lower Address Write Data Higher Address Hi Z Read Data ...

Page 523: ...with Memory This section provides µPD78054 and external memory connection examples in Figure 22 8 SRAMs are used as the external memory in these diagrams In addition the external device expansion function is used in the full address mode and the address from 0000H to 7FFFH 32 Kbytes are allocated for internal ROM and the addresses after 8000H for SRAM Figure 22 8 Connection Example of µPD78054 and...

Page 524: ...524 MEMO ...

Page 525: ...onsumption Because this mode can be cleared upon interrupt request it enables intermittent operations to be carried out However because a wait time is necessary to secure an oscillation stabilization time after the STOP mode is cleared select the HALT mode if it is necessary to start processing immediately upon interrupt request In any mode all the contents of the register flag and data memory jus...

Page 526: ...ode is cleared upon interrupt request till the oscillation stabilizes is controlled with the oscillation stabilization time select register OSTS OSTS is set with an 8 bit memory manipulation instruction RESET input sets OSTS to 04H However it takes 217 fX not 218 fX until the STOP mode is cleared by RESET input Figure 23 1 Oscillation Stabilization Time Select Register Format Caution The wait time...

Page 527: ... Operable when watch timer output is selected as count clock fXT is selected as count clock of watch timer or when TI00 is selected 8 bit timer event counter Operable Operable when TI1 or TI2 is selected as count clock Watch timer Operable when fXX 27 is Operable Operable when fXT is selected as count clock selected as count clock Watchdog timer Operable Operation stops A D converter Operable Oper...

Page 528: ...LT Mode Clear upon Interrupt Request Generation Remarks 1 The broken line indicates the case when the interrupt request which has cleared the standby status is acknowledged 2 Wait time will be as follows When vectored interrupt service is carried out 8 to 9 clocks When vectored interrupt service is not carried out 2 to 3 clocks b Clear upon non maskable interrupt request When a non maskable interr...

Page 529: ...rce MK PR IE ISP Operation Maskable interrupt 0 0 0 Next address instruction execution request 0 0 1 Interrupt service execution 0 1 0 1 Next address instruction execution 0 1 0 0 1 1 1 Interrupt service execution 1 HALT mode hold Non maskable interrupt Interrupt service execution request Test input 0 Next address instruction execution 1 HALT mode hold RESET input Reset processing Remark x Don t c...

Page 530: ...erating Status Setting of STOP Mode With subsystem clock Without subsystem clock Item Clock generator Only main system clock stops oscillation CPU Operation stops Port output latch Status before STOP mode setting is held 16 bit timer event counter Operable when watch timer output is Operation stops selected as count clock fXT is selected as count clock of watch timer 8 bit timer event counter Oper...

Page 531: ...cleared If interrupt request acknowledge is enabled after the lapse of oscillation stabilization time vectored interrupt service is carried out If interrupt request acknowledge is disabled the next address instruction is executed Figure 23 4 STOP Mode Release by Interrupt Request Generation Remark The broken line indicates the case when the interrupt request which has cleared the standby status is...

Page 532: ...on time reset operation is carried out Figure 23 5 Release by STOP Mode RESET Input Remarks 1 fX main system clock oscillation frequency 2 fX 5 0 MHz Table 23 4 Operation after STOP Mode Release Release Source MK PR IE ISP Operation Maskable interrupt request 0 0 0 Next address instruction execution 0 0 1 Interrupt service execution 0 1 0 1 Next address instruction execution 0 1 0 0 1 1 1 Interrup...

Page 533: ...ach pin has high impedance during reset input or during oscillation stabilization time just after reset clear When a high level is input to the RESET input the reset is cleared and program execution starts after the lapse of oscillation stabilization time 217 fX The reset applied by watchdog timer overflow is automatically cleared after a reset and program execution starts after the lapse of oscil...

Page 534: ...mer Overflow Internal Reset Signal Port Pin Reset Period Oscillation Stop Oscillation Stabilization Time Wait Normal Operation Reset Processing Hi Z Figure 24 2 Timing of Reset Input by RESET Input Figure 24 3 Timing of Reset due to Watchdog Timer Overflow Figure 24 4 Timing of Reset Input in STOP Mode by RESET Input RESET Internal Reset Signal Port Pin Delay Delay Hi Z X1 Normal Operation Reset P...

Page 535: ...r register TM0 0000H Capture compare register CR00 CR01 Undefined Clock selection register TCL0 00H Mode control register TMC0 00H Capture compare control register 0 CRC0 04H Output control register TOC0 00H Timer register TM1 TM2 00H Compare registers CR10 CR20 Undefined Clock select register TCL1 00H Mode control registers TMC1 00H Output control register TOC1 00H 16 bit timer event counter 8 bi...

Page 536: ...enerator control register BRGC 00H Transmit shift register TXS Receive buffer register RXB Interrupt timing specify register SINT 00H A D converter Mode register ADM 01H Conversion result register ADCR Undefined Input select register ADIS 00H D A converter Mode register DAM 00H Conversion value setting register DACS0 DACS1 00H Real time output port Mode register RTPM 00H Control register RTPC 00H ...

Page 537: ...flow can be changed by using the ROM correction The ROM correction can correct two places max of the internal ROM program Caution The ROM correction cannot be emulated by the in circuit emulator IE 78000 R IE 78000 R A IE 78K0 NS IE 78001 R A 25 2 ROM Correction Configuration The ROM correction is executed by the following hardware Table 25 1 ROM Correction Configuration Item Configuration Registe...

Page 538: ...s Registers 0 and 1 Format Cautions 1 Set the CORAD0 and CORAD1 when bit 1 COREN0 and bit 3 COREN1 of the correction control register CORCN see Figure 25 3 are 0 2 Only addresses where operation codes are stored can be set in CORAD0 and CORAD1 3 Do not set the following addresses to CORAD0 and CORAD1 Address value in table area of table reference instruction CALLT instruction 0040H to 007FH Addres...

Page 539: ...Control Registers The ROM correction is controlled with the correction control register CORCN 1 Correction control register CORCN This register controls whether or not the correction branch request signal is generated when the fetch address matches the correction address set in correction address registers 0 and 1 The correction control register consists of correction enable flags COREN0 COREN1 an...

Page 540: ...stination judgment program as well The branch destination judgment program checks which one of the addresses set to CORAD0 or CORAD1 generates the correction branch Figure 25 4 Storing Example to EEPROM when one place is corrected Figure 25 5 Connecting Example with EEPROM using 2 wire serial I O mode VDD VDD VDD PD78058 78058Y EEPROM SCK0 SB1 P32 SCL SDA CS CE µ RA78K 0 EEPROM Source program 00 1...

Page 541: ...on to be corrected to CORAD0 and CORAD1 and set bits 1 and 3 COREN0 COREN1 of the correction control register CORCN to 1 4 Set the entire space branch instruction BR addr16 to the specified address F7FDH of the internal expansion RAM with the main program 5 After the main program is started the fetch address value and the values set in CORAD0 and CORAD1 are always compared by the comparator in the...

Page 542: ...No Yes Internal ROM program start Does fetch address match with correction address Set correction status flag Correction branch branch to address F7FDH Correction program execution ROM correction Figure 25 7 ROM Correction Operation ...

Page 543: ...H ADD A 1 is changed to ADD A 2 is as follows Figure 25 8 ROM Correction Example 1 Branches to address F7FDH when the preset value 1000H in the correction address register matches the fetch address value after the main program is started 2 Branches to any address address F702H in this example by setting the entire space branch instruction BR addr16 to address F7FDH with the main program 3 Returns ...

Page 544: ...nd 25 10 show the program transition diagrams when the ROM correction is used Figure 25 9 Program Transition Diagram when one place is corrected 1 Branches to address F7FDH when fetch address matches correction address 2 Branches to correction program 3 Returns to internal ROM program Remark Area filled with diagonal lines Internal expansion RAM JUMP Correction program start address ...

Page 545: ...atches correction address 2 Branches to branch destination judgment program 3 Branches to correction program 1 by branch destination judgment program BTCLR CORST0 xxxxH 4 Returns to internal ROM program 5 Branches to address F7FDH when fetch address matches correction address 6 Branches to branch destination judgment program 7 Branches to correction program 2 by branch destination judgment program...

Page 546: ...set address value 3 Do not set the address value of instruction immediately after the instruction that sets the correction enable flag COREN0 COREN1 to 1 to correction address register 0 or 1 CORAD0 CORAD1 the correction branch may not start 4 Do not set the address value in table area of table reference instruction CALLT instruction 0040H to 007FH and the address value in vector table area 0000H ...

Page 547: ...One time PROM EPROM Mask ROM Internal ROM capacity µPD78P054 32 Kbytes µPD78052 16 Kbytes µPD78P058 60 Kbytes µPD78053 24 Kbytes µPD78054 32 Kbytes µPD78055 40 Kbytes µPD78056 48 Kbytes µPD78058 60 Kbytes Internal high speed RAM capacity 1024 bytes µPD78052 512 bytes µPD78053 1024 bytes µPD78054 1024 bytes µPD78055 1024 bytes µPD78056 1024 bytes µPD78058 1024 bytes Internal expansion RAM capacity ...

Page 548: ...k ROM versions in the stage between test production and mass production evaluate thoroughly with CS products not ES products of the mask ROM versions Remarks 1 The µPD78P054 is a PROM model corresponding to the µPD78052 78053 and 78054 The µPD78P058 is a PROM model corresponding to the µPD78055 78056 and 78058 2 Only the µPD78058 and 78P058 are provided with an internal expansion RAM size switchin...

Page 549: ...ter Format µPD78P054 The IMS settings to give the same memory map as mask ROM versions are shown in Table 26 3 Table 26 3 Examples of Memory Size Switching Register Settings µPD78P054 Relevant Mask ROM Version IMS Setting µPD78052 44H µPD78053 C6H µPD78054 C8H 26 1 Memory Size Switching Register µPD78P054 The µPD78P054 allows users to define its internal ROM and high speed RAM sizes using the memo...

Page 550: ...58 The µPD78P058 allows users to define its internal ROM and high speed RAM sizes using the memory size switching register IMS so that the same memory mapping as that of a mask ROM version with a different size internal ROM and high speed RAM is possible IMS is set with an 8 bit memory manipulation instruction RESET input sets IMS to CFH Figure 26 2 Memory Size Switching Register Format µPD78P058 ...

Page 551: ... different size internal expansion RAM is possible The IXS is set by an 8 bit memory manipulation instruction RESET signal input sets IXS to 0AH Figure 26 3 Internal Expansion RAM Size Switching Register Format The value in the IXS that has the identical memory map to the mask ROM versions is given in Table 26 5 Table 26 5 Value Set to the Internal Expansion RAM Size Switching Register Pertinent m...

Page 552: ...modes When 5 V or 12 5 V is applied to the VPP pin and a low level signal is applied to the RESET pin the µPD78P054 and µPD78P058 are set to the PROM programming mode This is one of the operating modes shown in Table 26 6 below according to the setting of the CE OE and PGM pins The PROM contents can be read by setting the read mode Table 26 6 PROM Programming Operating Modes Pin Operating mode Pag...

Page 553: ...rite and verify operations are executed X times X 10 6 Byte write mode A byte write is executed by applying a 0 1 ms program pulse active low to the PGM pin while CE L and OE H After this program verification can be performed by setting OE to L If programming is not performed by one program pulse repeated write and verify operations are executed X times X 10 7 Program verify mode Setting CE to L P...

Page 554: ...dress Address 1 Latch X X 1 0 1 ms program pulse Verify 4 Bytes Pass Address N No Pass VDD 4 5 to 5 5 V VPP VDD All bytes verified End of write Address Address 1 No Yes X 10 Fail Fail Yes All Pass Defective product Remark G Start address N Last address of program 26 4 2 PROM write procedure Figure 26 4 Page Program Mode Flowchart ...

Page 555: ...R 26 µPD78P054 78P058 Figure 26 5 Page Program Mode Timing Page Data Latch Page Program Program Verify Data Input Data Output A2 A16 A0 A1 D0 D7 VPP VDD VPP VDD 1 5 VDD VDD VIH CE PGM OE VIL VIH VIL VIH VIL Hi Z ...

Page 556: ... X X 1 0 1 ms program pulse Verify Address N VDD 4 5 to 5 5 V VPP VDD All bytes verified End of write Fail Fail Pass Yes All Pass No Pass Defective product No Yes X 10 Address Address 1 Remark G Start address N Last address of program Figure 26 6 Byte Program Mode Flowchart ...

Page 557: ...ng VPP 2 VPP must not exceed 13 5 V including overshoot voltage 3 Disconnecting inserting the device from to the on board socket while 12 5 V is being applied to the VPP pin may have an adverse affect on device reliability A0 A16 D0 D7 Program Hi Z Program Verify Data Input Data Output VPP VDD VDD 1 5 VDD VIH VIL VIH VIL VIH VIL VPP VDD CE PGM OE ...

Page 558: ... Fix the RESET pin low and supply 5 V to the VPP pin Unused pins are handled as shown in paragraph 2 PROM programming mode in section 1 5 or 2 5 Pin Configuration Top View 2 Supply 5 V to the VDD and VPP pins 3 Input the address of data to be read to pins A0 through A16 4 Read mode is entered 5 Data is output to pins D0 through D7 The timing for steps 2 through 5 above is shown in Figure 26 8 Figu...

Page 559: ... unintentional erasure of the EPROM contents by light and to prevent internal circuits from mulfunction due to light coming in through the erasure window mask the window with opaque film after writing the EPROM 26 7 Screening of One Time PROM Versions One time PROM versions µPD78P054GC 3B9 78P054GC 8BT 78P054GK BE9 78P058GC 8BT and 78P058YGC 8BT cannot be fully tested by NEC before shipment due to...

Page 560: ...560 MEMO ...

Page 561: ...N SET This chapter describes each instruction set of the µPD78054 and 78054Y subseries as list table For details of its operation and operation code refer to the separate document 78K 0 Series User s Manual Instruction U12326E ...

Page 562: ...unction names X A C etc or absolute names names in parentheses in the table below R0 R1 R2 etc can be used for description Table 27 1 Operand Identifiers and Description Methods Identifier Description Method r X R0 A R1 C R2 B R3 E R4 D R5 L R6 H R7 rp AX RP0 BC RP1 DE RP2 HL RP3 sfr Special function register symbolNote sfrp Special function register symbol 16 bit manipulatable register even addre...

Page 563: ...arry flag Z Zero flag RBS Register bank select flag IE Interrupt request enable flag NMIS Non maskable interrupt servicing flag Memory contents indicated by address or register contents in parentheses H L Higher 8 bits and lower 8 bits of 16 bit register Logical product AND Logical sum OR Exclusive logical sum exclusive OR Inverted data addr16 16 bit immediate data or label jdisp8 Signed 8 bit dat...

Page 564: ... A r Note 3 1 2 A r A saddr 2 4 6 A saddr A sfr 2 6 A sfr A addr16 3 8 10 n m A addr16 XCH A DE 1 4 6 n m A DE A HL 1 4 6 n m A HL A HL byte 2 8 10 n m A HL byte A HL B 2 8 10 n m A HL B A HL C 2 8 10 n m A HL C Notes 1 When the internal high speed RAM area is accessed or instruction with no data access 2 When an area except the internal high speed RAM area is accessed 3 Except r A Remarks 1 One i...

Page 565: ...8 saddr CY saddr byte CY A r Note 4 2 4 A CY A r CY r A 2 4 r CY r A CY A saddr 2 4 5 A CY A saddr CY A addr16 3 8 9 n A CY A addr16 CY A HL 1 4 5 n A CY A HL CY A HL byte 2 8 9 n A CY A HL byte CY A HL B 2 8 9 n A CY A HL B CY A HL C 2 8 9 n A CY A HL C CY Notes 1 When the internal high speed RAM area is accessed or instruction with no data access 2 When an area except the internal high speed RAM...

Page 566: ...A CY A HL B CY A HL C 2 8 9 n A CY A HL C CY A byte 2 4 A A byte saddr byte 3 6 8 saddr saddr byte A r Note 3 2 4 A A r r A 2 4 r r A A saddr 2 4 5 A A saddr A addr16 3 8 9 n A A addr16 A HL 1 4 5 n A A HL A HL byte 2 8 9 n A A HL byte A HL B 2 8 9 n A A HL B A HL C 2 8 9 n A A HL C Notes 1 When the internal high speed RAM area is accessed or instruction with no data access 2 When an area except t...

Page 567: ...9 n A A HL C A byte 2 4 A byte saddr byte 3 6 8 saddr byte A r Note 3 2 4 A r r A 2 4 r A A saddr 2 4 5 A saddr A addr16 3 8 9 n A addr16 A HL 1 4 5 n A HL A HL byte 2 8 9 n A HL byte A HL B 2 8 9 n A HL B A HL C 2 8 9 n A HL C Notes 1 When the internal high speed RAM area is accessed or instruction with no data access 2 When an area except the internal high speed RAM area is accessed 3 Except r A...

Page 568: ...it 2 4 CY A bit CY PSW bit 3 7 CY PSW bit CY HL bit 2 6 7 n CY HL bit saddr bit CY 3 6 8 saddr bit CY sfr bit CY 3 8 sfr bit CY A bit CY 2 4 A bit CY PSW bit CY 3 8 PSW bit CY HL bit CY 2 6 8 n m HL bit CY Notes 1 When the internal high speed RAM area is accessed or instruction with no data access 2 When an area except the internal high speed RAM area is accessed Remarks 1 One instruction clock cy...

Page 569: ...4 A bit 1 PSW bit 2 6 PSW bit 1 HL bit 2 6 8 n m HL bit 1 saddr bit 2 4 6 saddr bit 0 sfr bit 3 8 sfr bit 0 CLR1 A bit 2 4 A bit 0 PSW bit 2 6 PSW bit 0 HL bit 2 6 8 n m HL bit 0 SET1 CY 1 2 CY 1 1 CLR1 CY 1 2 CY 0 0 NOT1 CY 1 2 CY CY Notes 1 When the internal high speed RAM area is accessed or instruction with no data access 2 When an area except the internal high speed RAM area is accessed Remar...

Page 570: ...2 8 SP AX AX SP 2 8 AX SP addr16 3 6 PC addr16 BR addr16 2 6 PC PC 2 jdisp8 AX 2 8 PCH A PCL X BC addr16 2 6 PC PC 2 jdisp8 if CY 1 BNC addr16 2 6 PC PC 2 jdisp8 if CY 0 BZ addr16 2 6 PC PC 2 jdisp8 if Z 1 BNZ addr16 2 6 PC PC 2 jdisp8 if Z 0 Notes 1 When the internal high speed RAM area is accessed or instruction with no data access 2 When an area except the internal high speed RAM area is access...

Page 571: ...t 1 then reset sfr bit BTCLR PC PC 3 jdisp8 if A bit 1 then reset A bit PC PC 4 jdisp8 if PSW bit 1 then reset PSW bit PC PC 3 jdisp8 if HL bit 1 then reset HL bit B B 1 then PC PC 2 jdisp8 if B 0 C C 1 then PC PC 2 jdisp8 if C 0 saddr saddr 1 then PC PC 3 jdisp8 if saddr 0 SEL RBn 2 4 RBS1 0 n NOP 1 2 No Operation EI 2 6 IE 1 Enable Interrupt DI 2 6 IE 0 Disable Interrupt HALT 2 6 Set HALT Mode S...

Page 572: ...572 CHAPTER 27 INSTRUCTION SET 27 3 Instructions Listed by Addressing Type 1 8 bit instructions MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MULU DIVUW INC DEC ROR ROL RORC ROLC ROR4 ROL4 PUSH POP DBNZ ...

Page 573: ...DD ADD ADD RORC SUBC ADDC ADDC ADDC ADDC ADDC ROLC AND SUB SUB SUB SUB SUB OR SUBC SUBC SUBC SUBC SUBC XOR AND AND AND AND AND CMP OR OR OR OR OR XOR XOR XOR XOR XOR CMP CMP CMP CMP CMP r MOV MOV INC ADD DEC ADDC SUB SUBC AND OR XOR CMP B C DBNZ sfr MOV MOV saddr MOV MOV DBNZ INC ADD DEC ADDC SUB SUBC AND OR XOR CMP addr16 MOV PSW MOV MOV PUSH POP DE MOV HL MOV ROR4 ROL4 HL byte MOV HL B HL C X MU...

Page 574: ...L 3 Bit manipulation instructions MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 BT BF BTCLR Second Operand First Operand A bit MOV1 BT SET1 BF CLR1 BTCLR sfr bit MOV1 BT SET1 BF CLR1 BTCLR saddr bit MOV1 BT SET1 BF CLR1 BTCLR PSW bit MOV1 BT SET1 BF CLR1 BTCLR HL bit MOV1 BT SET1 BF CLR1 BTCLR CY MOV1 MOV1 MOV1 MOV1 MOV1 SET1 AND1 AND1 AND1 AND1 AND1 CLR1 OR1 OR1 OR1 OR1 OR1 NOT1 XOR1 XOR1 XOR1 XOR1 XOR1 word...

Page 575: ...tions branch instructions CALL CALLF CALLT BR BC BNC BZ BNZ BT BF BTCLR DBNZ Second Operand First Operand Basic instruction BR CALL CALLF CALLT BR BR BC BNC BZ BNZ Compound BT instruction BF BTCLR DBNZ 5 Other instructions ADJBA ADJBS BRK RET RETI RETB SEL NOP EI DI HALT STOP ...

Page 576: ...576 MEMO ...

Page 577: ...577 APPENDIX A DIFFERENCES BETWEEN µPD78054 78054Y SUBSERIES AND µPD78058F 78058FY SUBSERIES Table A 1 shows the major differences between the µPD78054 78054Y Subseries and µPD78058F 78058FY Subseries ...

Page 578: ...PD78056 1024 bytes µPD78058 1024 bytes µPD78P058 1024 bytes Internal expansion RAM capacity µPD78058 1024 bytes µPD78058F 1024 bytes µPD78P058 1024 bytes VDD pin Positive power supply including ports Positive power supply excluding ports VSS pin Ground potential including ports Ground potential excluding ports AVDD pin Analog power supply for A D converter Analog power supply for A D converter D A...

Page 579: ...ENDIX B DEVELOPMENT TOOLS The following development tools are available for the development of systems which employ the µPD78054 and 78054Y subseries Figure B 1 shows the configuration of the development tools ...

Page 580: ...compiler package C library source file Device file Debugging tool System simulator Integrated debugger Device file Embedded software Real time OS OS Host machine PC Interface adapter PC card interface etc PROM programming environment PROM programmer Programmer adapter PROM contained version In circuit emulator Emulation board Emulation probe Power supply unit Conversion socket or conversion adapte...

Page 581: ...rocessing software Assembler package C compiler package C library source file Device file Debugging tool System simulator Integrated debugger Device file Embedded software Real time OS OS Host machine PC or EWS Interface board PROM programming environment PROM programmer Programmer adapter PROM contained version In circuit emulator Emulation board Emulation probe Conversion socket or conversion ad...

Page 582: ...rately available Assembler Package and Device File Precautions for the use in PC environment Although C Compiler Package is a DOS based application it can be used in Windows environment through the use of Project Manager included in Assembler Package on Windows Part number µSxxxxCC78K0 DF78054Note A file which contains information peculiar to the device Device File Usedincombinationwithseparatelya...

Page 583: ...Media AA13 PC 9800 series Japanese WindowsNotes 1 2 3 5 inch 2HD FD AB13 IBM PC AT and Japanese WindowsNotes 1 2 3 5 inch 2HC FD BB13 compatibles English WindowsNotes 1 2 3P16 HP9000 series 700 HP UX rel 9 05 DAT DDS 3K13 SPARCstation SunOS rel 4 1 4 3 5 inch 2HC FD 3K15 1 4 inch CGMT 3R13 NEWS RISC NEWS OS rel 6 1 3 5 inch 2HC FD Notes 1 Operates also in DOS environment 2 Does not support Windows...

Page 584: ...C 8BT type PA 78P054GK 80 pin plastic QFP GK BE9 type PA 78P054KK T 80 pin ceramic WQFN KK T type B 2 PROM Writing Tools B 2 1 Hardware B 2 2 Software PG 1500 Controller Connects PG 1500 and the host machine with serial and parallel interface and controls the PG 1500 on the host machine The PG 1500 controller is a DOS based application Use it with the DOS prompt on Windows Part number µSxxxxPG1500...

Page 585: ...machine for the IE 78K0 NS An adapter required when using an IBM PC AT and compatible as the host machine for the IE 78K0 NS A board to emulate peripheral hardware peculiar to the device Used in combination with an in circuit emulator A probe to connect an in circuit emulator and a target system For 80 pin plastic QFP GC 3B9 GC 8BT type A conversion socket to connect the board of a target system t...

Page 586: ...plastic QFP GC 3B9 GC 8BT type A conversion socket to connect the board of a target system designed to mount80 pin plasticQFP GC 3B9 GC 8BTtype and theEP 78230GC R The µPD78P054KK T 78P058KK T or 78P058YKK T ceramic WQFN can be mounted instead of connecting the EP 78230GC R A probe to connect an in circuit emulator and the target system For 80 pin plastic TQFP GK BE9 type A conversion adapter to c...

Page 587: ...ly from hardware development without using in circuit emulator and improves the development efficiency and the software quality Used in combination with separately available Device File DF78054 Part number µSxxxxSM78K0 Remark xxxx in the part number differs depending on the host machine and OS used µSxxxx SM78K0 xxxx Host Machine OS Supply Media AA13 PC 9800 series Japanese WindowsNotes 1 2 3 5 in...

Page 588: ...WindowsNote 3P16 HP9000 series 700 HP UX Rel 9 05 DAT DDS 3K13 SPARCstation SunOS Rel 4 1 4 3 5 inch 2HC FD 3K15 1 4 inch CGMT 3R13 NEWS RISC NEWS OS Rel 6 1 3 5 inch 2HC FD Note Does not support WindowsNT A control program to debug the 78K 0 Series Adopting Windows on personal computers and OSF Motif on EWS as graphical user interface presents the appearance and the operability conforming to them...

Page 589: ...e B 5 Upgrading Former In circuit Emulators for 78K 0 Series to IE 78001 R A If you have a former in circuit emulator for the 78K 0 Series IE 78000 R or IE 78000 R A your in circuit emulator can be upgraded to be equivalent to the IE 78001 R A in circuit emulator by simply replacing the break board with the IE 78001 R BK under development Table B 2 Upgrading Former In circuit Emulators for 78K 0 S...

Page 590: ...No 1 pin index E EV 9200GC 80 B C M N O L K S R Q P I H J G EV 9200GC 80 G0 ITEM MILLIMETERS INCHES A B C D E F G H I J K L M O N P Q R S 18 0 14 4 14 4 18 0 4 C 2 0 0 8 6 0 16 0 18 7 6 0 16 0 18 7 8 2 8 0 2 5 2 0 0 35 2 3 1 5 0 709 0 567 0 567 0 709 4 C 0 079 0 031 0 236 0 63 0 736 0 236 0 63 0 736 0 323 0 315 0 098 0 079 0 014 0 091 0 059 φ φ φ φ ...

Page 591: ...776 0 591 0 591 0 776 0 236 0 236 0 014 0 093 0 091 0 062 0 65 0 02 19 12 35 0 05 0 65 0 02 19 12 35 0 05 φ φ 0 001 0 002 0 003 0 002 0 001 0 002 0 003 0 002 0 003 0 002 0 003 0 002 0 001 0 001 0 001 0 002 φ 0 001 0 002 φ φ Based on EV 9200GC 80 2 Pad drawing in mm Dimensions of mount pad for EV 9200 and that for target device QFP may be different in some parts For the recommended mount pad dimens...

Page 592: ... 58 0 062 S 3 55 0 140 N 1 58 0 062 O 1 2 P 7 64 0 301 0 047 W 6 8 0 268 X 8 24 0 324 Y 14 8 0 583 T C 2 0 C 0 079 U 12 31 V 10 17 0 400 0 485 Z 1 4 0 2 0 055 0 008 0 5 1 58 0 020 0 062 G 18 0 0 709 k 3 0 0 118 n 1 4 0 2 0 055 0 008 o 1 4 0 2 0 055 0 008 p h 1 8 1 3 h 0 071 0 051 l 0 25 m 14 0 0 551 0 010 q 0 to 5 0 000 to 0 197 φ φ 11 77 0 5 φ 0 463 0 020 φ TGK 080SDW G1E t 2 4 0 094 u 2 7 0 106 ...

Page 593: ...e purchase application form in advance and sign the License Agreement Remark xxxx and in the part number differs depending on the host machine and OS used µSxxxxRX78013 Product Outline Max No for Use in Mass Production 001 Evaluation object Do not use for mass production 100K Mass production object 100 000 001M 1 000 000 010M 10 000 000 S01 Source program Source program for mass production object ...

Page 594: ...on the host machine and OS used µSxxxxMX78K0 Product outline Max No for Use in Mass Production 001 Evaluation object Use for preproduction xx Mass production object Use for mass production S01 Source program Can be purchased only when purchasing mass produced object xxxx Host Machine OS Supply Media AA13 PC 9800 series Japanese Windows Notes1 2 3 5 inch 2HD FD AB13 IBM PC AT and Japanese Windows N...

Page 595: ...chronous serial interface mode register 445 453 455 478 ASIS Asynchronous serial interface status register 447 456 B BRGC Baud rate generator control register 448 457 469 C CORAD0 Correction address register 0 538 CORAD1 Correction address register 1 538 CORCN Correction control register 539 CR00 Capture compare register 00 181 CR01 Capture compare register 01 181 CR10 Compare registers 10 223 CR2...

Page 596: ...509 M MK0H Interrupt mask flag register 0H 490 MK0L Interrupt mask flag register 0L 490 MK1L Interrupt mask flag register 1L 490 508 MM Memory expansion mode register 154 516 Memory size switching register IMS 517 549 550 O OSMS Oscillation mode selection register 164 OSTS Oscillation stabilization time select register 516 P P0 Port0 134 P1 Port1 136 P2 Port2 137 139 P3 Port3 141 P4 Port4 142 P5 P...

Page 597: ...ister 300 318 336 354 364 375 SIO0 Serial I O shift register 0 292 346 SIO1 Serial I O shift register 1 396 SVA Slave address register 292 346 Serial operating mode register 0 CSIM0 296 302 315 334 350 357 362 372 Serial operating mode register 1 CSIM1 396 399 409 Serial operating mode register 2 CSIM2 444 452 454 467 T TCL0 Timer clock select register 0 182 257 TCL1 Timer clock select register 1 ...

Page 598: ...598 MEMO ...

Page 599: ...4 Subseries Caution on oscillation mode switching was added CHAPTER 7 Clock Generator Parts of list of maximum required time for switching CPU clock types were corrected Available frequencies for 16 bit timer register count clock were CHAPTER 8 16 bit Timer Event Counter changed Caution on pulse width measurement operations was added Timing chart for one shot pulse output operation was corrected S...

Page 600: ...sion from Master to Slave Both Master and Slave Selected 9 Clock Wait Correction of Figure 17 23 Data Transmission from Slave to Master Both Master and Slave Selected 9 Clock Wait Addition of 3 Slave wait release slave reception to 17 4 5 Cautions on use of I2C bus mode Addition of 17 4 6 Restrictions in I2C bus mode Addition of Caution to Figure 18 5 Automatic Data Transmit CHAPTER 18 SERIAL INTE...

Page 601: ...e CHAPTER 18 SERIAL INTERFACE Interval time were added to 18 4 3 3 wire serial I O mode CHANNEL 1 operation with automatic transmit receive function Precaution was added to 19 1 3 3 wire serial I O mode CHAPTER 19 SERIAL INTERFACE MSB LSB first switchable CHANNEL 2 Figure 19 3 Serial Operating Mode Register 2 Format was changed Table 19 2 Serial Interface Channel 2 Operating Mode Settings was chan...

Page 602: ...602 MEMO ...

Page 603: ...x 02 719 5951 Address North America NEC Electronics Inc Corporate Communications Dept Fax 1 800 729 9288 1 408 588 6130 Europe NEC Electronics Europe GmbH Technical Documentation Dept Fax 49 211 6503 274 South America NEC do Brasil S A Fax 55 11 6465 6829 Asian Nations except Philippines NEC Electronics Singapore Pte Ltd Fax 65 250 3583 Japan NEC Semiconductor Technical Hotline Fax 044 548 7900 I ...

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