NEC mPD780973 Series Preliminary User'S Manual Download Page 193

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CHAPTER 16 LCD CONTROLLER/DRIVER

(2) LCD display control register (LCDC)

This register sets cutoff of the current flowing to split resistors for LCD drive voltage generation and switchover

between segment output and input/output port functions.

LCDC is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears LCDC to 00H.

Figure 16-4. LCD Display Control Register (LCDC) Format

Address: FFB2H After Reset: 00H R/W

Symbol

LCDC

LCDC7

LCDC6

LCDC5

LCDC4

LIPS

LCDC7

LCDC6

LCDC5

LCDC4

P81/S19 to P97/S5 Pin Functions

Port Pins

Segment Pins

P81 to P97

None

P81 to P95

S5 to S6

P81 to P93

S5 to S8

P81 to P91

S5 to S10

P81 to P87

S5 to S12

P81 to P85

S5 to S14

P81 to P83

S5 to S16

P81

S5 to S18

None

S5 to S19

Other than above

Setting prohibited

LIPS

LCD Driving Power Supply Selection

Does not supply power to LCD.

Supplies power to LCD from V

pin.

Cautions 1. Pins which perform segment output cannot be used as output port pins even if 0 is

set in the port mode register.

2. If a pin which performs segment output is read as a port, its value will be 0.

Summary of Contents for mPD780973 Series

Page 1: ...µPD780973 Subseries 8 Bit Single Chip Microcontrollers µPD780973 A µPD78F0974 Document No U12406EJ2V0UM00 2nd edition Date Published May 1998 N CP K 1997 Preliminary User s Manual Printed in Japan ...

Page 2: ...2 MEMO ...

Page 3: ...ve material All test and measurement tools including work bench and floor should be grounded The operator should be grounded using wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with semiconductor devices on it 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note No connection for CMOS device inputs can be cause of malfunction If n...

Page 4: ...g it in a particular application Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots Special Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical...

Page 5: ...e Netherlands Tel 040 2445845 Fax 040 2444580 NEC Electronics France S A Velizy Villacoublay France Tel 01 30 67 58 00 Fax 01 30 67 58 99 NEC Electronics France S A Spain Office Madrid Spain Tel 01 504 2787 Fax 01 504 2860 NEC Electronics Germany GmbH Scandinavia Office Taeby Sweden Tel 08 63 80 820 Fax 08 63 80 388 Regional Information Some information contained in this document may vary from cou...

Page 6: ...es of P20 to P27 and P30 to P37 from 0 to Change of Note 2 p 86 Addition of Note in Figure 5 13 Port Mode Register PM2 PM3 Format p 89 CHAPTER 6 CLOCK GENERATOR Addition of oscillator mode register to Table 6 1 Clock Generator Configuration Change of Figure 6 1 Clock Generator Block Diagram Addition of 2 Oscillator mode register OSCM to 6 3 Clock Generator Control Register Addition of explanation ...

Page 7: ...OLS Support of in circuit emulator IE 78K0 NS Change in supported OS Addition of A 4 Upgrading Former In circuit Emulator for 78K 0 Series to IE 78001 R A Deletion of OS for IBM PC from previous edition Deletion of Development Environment when Using IE 78000 R A from previous edition p 291 APPENDIX B EMBEDDED SOFTWARE Change in supported OS Deletion of Fuzzy Inference Development Support System fr...

Page 8: ...ns of the µPD780973 A and 78F0974 in general Read this manual in the order of the CONTENTS How to read register formats The name of a bit whose number is enclosed in square is reserved for the RA78K 0 and is defined for the CC78K 0 by the header file sfrbit h To learn the detailed functions of a register whose register name is known Refer to APPENDIX C REGISTER INDEX The application examples in th...

Page 9: ...ssembly Language U11801J U11801E Structured Assembly Language U11789J U11789E RA78K Series Structured Assembler Preprocessor EEU 817 EEU 1402 CC78K0 C Compiler Operation U11517J U11517E Language U11518J U11518E CC78K 0 C Compiler Application Note Programming Know how U13034J EEA 1208 CC78K Series Library Source File U12322J IE 78K0 NS To be prepared To be prepared IE 78001 R A To be prepared To be...

Page 10: ...r Device Mounting Technology Manual C10535J C10535E Quality Grades on NEC Semiconductor Devices C11531J C11531E NEC Semiconductor Device Reliability Quality Control System C10983J C10983E Guide to Prevent Damage for Semiconductor Devices by Electro Static Discharge ESD C11892J C11892E Guide to Quality Assurance for Semiconductor Devices MEI 1202 Microcomputer Product Series Guide U11416J Caution T...

Page 11: ... P50 to P54 Port 5 34 2 2 7 P60 P61 Port 6 35 2 2 8 P81 to P87 Port 8 35 2 2 9 P90 to P97 Port 9 36 2 2 10 COM0 to COM3 36 2 2 11 VLCD 36 2 2 12 AVREF 36 2 2 13 AVSS 36 2 2 14 RESET 36 2 2 15 X1 and X2 36 2 2 16 SMVDD 36 2 2 17 SMVSS 36 2 2 18 VDD 36 2 2 19 VSS 36 2 2 20 VPP µPD78F0974 37 2 2 21 IC µPD780973 A 37 2 3 Input output Circuits and Recommended Connection of Unused Pins 38 CHAPTER 3 CPU ...

Page 12: ...1 EEPROM Functions 67 4 2 EEPROM Configuration 68 4 3 EEPROM Control Register 69 4 4 EEPROM Reading 70 4 5 EEPROM Writing 71 4 6 EEPROM Control Related Interrupt 71 4 7 Cautions regarding EEPROM Writing 72 CHAPTER 5 PORT FUNCTIONS 73 5 1 Port Functions 73 5 2 Port Configuration 75 5 2 1 Port 0 75 5 2 2 Port 1 76 5 2 3 Port 2 77 5 2 4 Port 3 78 5 2 5 Port 4 79 5 2 6 Port 5 80 5 2 7 Port 6 81 5 2 8 ...

Page 13: ...interval timer operation 115 8 5 8 Bit Timer 1 Cautions 118 CHAPTER 9 8 BIT TIMER EVENT COUNTERS 2 3 TM2 TM3 119 9 1 8 Bit Timer Event Counters 2 and 3 Functions 119 9 2 8 Bit Timer Event Counters 2 and 3 Configurations 121 9 3 8 Bit Timer Event Counters 2 and 3 Control Registers 122 9 4 8 Bit Timer Event Counters 2 and 3 Operations 125 9 4 1 8 bit interval timer operation 125 9 4 2 External event...

Page 14: ...D Converter Cautions 160 13 6 Cautions on Emulation 163 CHAPTER 14 SERIAL INTERFACE UART 165 14 1 UART Functions 165 14 2 UART Configuration 166 14 3 UART Control Registers 167 14 4 UART Operations 171 14 4 1 Operation stop mode 171 14 4 2 Asynchronous serial interface UART mode 171 CHAPTER 15 SERIAL INTERFACE SIO3 183 15 1 SIO3 Functions 183 15 2 SIO3 Configuration 184 15 3 SIO3 Control Register ...

Page 15: ...HAPTER 19 INTERRUPT FUNCTIONS 223 19 1 Interrupt Function Types 223 19 2 Interrupt Sources and Configuration 223 19 3 Interrupt Function Control Registers 227 19 4 Interrupt Servicing Operations 234 19 4 1 Non maskable interrupt request acknowledge operation 234 19 4 2 Maskable interrupt request acknowledge operation 237 19 4 3 Software interrupt request acknowledge operation 239 19 4 4 Multiple i...

Page 16: ...PPENDIX A DEVELOPMENT TOOLS 279 A 1 Language Processing Software 282 A 2 Flash Memory Writing Tools 283 A 3 Debugging Tools 284 A 3 1 Hardware 284 A 3 2 Software 286 A 4 Upgrading Former In circuit Emulator for 78K 0 Series to IE 78001 R A 288 APPENDIX B EMBEDDED SOFTWARE 291 APPENDIX C REGISTER INDEX 293 C 1 Register Index In Alphabetical Order with Respect to Register Name 293 C 2 Register Index...

Page 17: ...0 5 8 P60 and P61 Block Diagram 81 5 9 P81 Block Diagram 82 5 10 P82 to P87 Block Diagram 82 5 11 P90 to P97 Block Diagram 83 5 12 Port Mode Register PM0 PM4 to PM6 PM8 PM9 Format 86 5 13 Port Mode Register PM2 PM3 Format 86 5 14 Pull Up Resistor Option Register PU0 Format 87 6 1 Clock Generator Block Diagram 89 6 2 Processor Clock Control Register PCC Format 90 6 3 Oscillator Mode Register OSCM F...

Page 18: ...ings with Rising Edge Specified 128 9 8 PWM Output Operation Timing 130 9 9 Timing of Operation by Change of CRn 131 9 10 Timer n Start Timing 132 9 11 Timing after Compare Register Change during Timer Count Operation 132 10 1 Watch Timer Block Diagram 133 10 2 Watch Timer Mode Control Register WTM Format 135 10 3 Operation Timing of Watch Timer Interval Timer 137 11 1 Watchdog Timer Block Diagram...

Page 19: ...ode Register CSIM Format 186 15 4 Serial Operation Mode Register CSIM Format 187 15 5 Three Wire Serial I O Mode Timing 188 16 1 LCD Controller Driver Block Diagram 190 16 2 LCD Clock Select Circuit Block Diagram 191 16 3 LCD Display Mode Register LCDM Format 192 16 4 LCD Display Control Register LCDC Format 193 16 5 Relationship between LCD Display Data Memory Contents and Segment Common Outputs ...

Page 20: ... 9 Non Maskable Interrupt Request Acknowledge Timing 235 19 10 Non Maskable Interrupt Request Acknowledge Operation 236 19 11 Interrupt Request Acknowledge Processing Algorithm 238 19 12 Interrupt Request Acknowledge Timing Minimum Time 239 19 13 Interrupt Request Acknowledge Timing Maximum Time 239 19 14 Multiple Interrupt Examples 241 19 15 Interrupt Request Hold 243 20 1 Oscillation Stabilizati...

Page 21: ... 1 Timer Event Counter Operations 100 7 2 Timer 0 Configuration 102 8 1 Timer 1 Configuration 112 9 1 Timers 2 and 3 Configurations 121 10 1 Interval Timer Interval Time 134 10 2 Watch Timer Configuration 134 10 3 Interval Timer Interval Time 136 11 1 Watchdog Timer Runaway Detection Time 140 11 2 Interval Time 140 11 3 Watchdog Timer Configuration 141 11 4 Watchdog Timer Runaway Detection Time 14...

Page 22: ...eneration of Maskable Interrupt Request until Servicing 237 19 4 Interrupt Request Enabled for Multiple Interrupt during Interrupt Servicing 240 20 1 HALT Mode Operating Status 247 20 2 Operation after HALT Mode Clear 249 20 3 STOP Mode Operating Status 250 20 4 Operation after STOP Mode Clear 252 21 1 Hardware Status after Reset 255 22 1 Differences between µPD78F0974 and µPD780973 A 257 22 2 Mem...

Page 23: ...e function as segment signal output LCD controller driver Segment signal output 20 max Common signal output 4 max Bias 1 3 bias Power supply voltage VLCD 3 0 V to VDD 8 bit resolution A D converter 5 channels Serial interface 2 channels 3 wire serial I O mode 1 channel UART mode 1 channel Timer Six channels 16 bit timer 1 channel 8 bit timer 1 channel 8 bit timer event counter 2 channels Watch tim...

Page 24: ... 1 4 Quality Grade Part Number Package Quality Grade µPD78F0974GF 3B9 80 pin plastic QFP 14 20 mm Standard µPD780973GF A 3B9 80 pin plastic QFP 14 20 mm Special Remark indicates ROM code suffix Please refer to Quality Grades on NEC Semiconductor Devices Document No C11531E published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications ...

Page 25: ...S18 TPO P81 S19 IC VPP X1 X2 VSS VDD RESET P07 P06 P05 P04 P03 INTP2 P02 INTP1 P01 INTP0 P00 AVREF P14 ANI4 P13 ANI3 ANI2 P12 ANI1 P11 ANI0 P10 AV SS SCK P50 SO P51 SI P52 V DD V SS RxD P53 TxD P54 TI00 P40 TI01 P41 TI02 P42 TIO2 P43 TIO3 P44 S12 P90 S11 P91 S10 P92 S9 P93 S8 P94 S7 P95 S6 P96 S5 P97 S4 S3 S2 S1 S0 COM3 COM2 COM1 Cautions 1 Connect IC Internally Connected pin to VSS directly 2 Con...

Page 26: ...1 to SM34 SM41 to SM44 P00 to P07 Port0 Meter Output P10 to P14 Port1 SMVDD Meter Controller Power Supply P20 to P27 Port2 SMVSS Meter Controller Ground P30 to P37 Port3 SO Serial Output P40 to P44 Port4 TI00 to TI02 Timer Input P50 to P54 Port5 TIO2 TIO3 Timer Output Event Counter Input P60 P61 Port6 TPO Prescaler Output P81 to P87 Port8 TxD Transmit Data P90 to P97 Port9 VDD Power Supply PCL Clo...

Page 27: ... several ROM and RAM capacities available A D converter of the PD780024 was enhanced EMI noise reduced version of the PD78018F On chip inverter control circuit and UART EMI noise reduced version Serial I O of the PD78018F was enhanced Serial I O of the PD78054 was enhanced EMI noise reduced version PD780058 80 pin µ µ µ PD780034 PD780024 PD78014H PD780034Y PD780024Y 64 pin 64 pin 64 pin µ µ µ µ µ ...

Page 28: ...0001 8 K 1 ch 39 µPD78002 8 K to 16 K 1 ch 53 Available µPD78083 8 ch 1 ch UART 1 ch 33 1 8 V Inverter µPD780988 32 K to 60 K 3 ch Note 1 1 ch 8 ch 3 ch UART 2 ch 47 4 0 V Available control µPD780964 8 K to 32 K Note 2 2 ch UART 2 ch 2 7 V µPD780924 8 ch FIP µPD780208 32 K to 60 K 2 ch 1 ch 1 ch 1 ch 8 ch 2 ch 74 2 7 V drive µPD780228 48 K to 60 K 3 ch 1 ch 72 4 5 V µPD78044H 32 K to 48 K 2 ch 1 c...

Page 29: ...LLER DRIVER SYSTEM CONTROL 8 bit TIMER1 8 bit TIMER EVENT COUNTER2 8 bit TIMER EVENT COUNTER3 WATCHDOG TIMER SERIAL INTERFACE A D CONVERTER INTERRUPT CONTROL STANDBY CONTROL SOUND GENERATOR OUTPUT VDD VSS IC VPP CLOCK OUTPUT CONTROL POWER FAIL DETECTOR UART RAM 78K 0 CPU CORE ROM FLASH MEMORY EEPROM WATCH TIMER TIO2 P43 TIO3 P44 SCK P50 SO P51 SI P52 ANI0 P10 to ANI4 P14 AVSS AVREF RxD P53 TxD P54...

Page 30: ...onverter 8 bit resolution 5 channels Power fail detection function LCD controller driver Segment signal outputs 20 max Common signal outputs 4 max Bias 1 3 bias only Serial interface 3 wire serial I O mode 1 channel UART mode 1 channel Timer 16 bit timer 1 channel 8 bit timer 1 channel 8 bit timer event counter 2 channels Watch timer 1 channel Watchdog timer 1 channel Meter control PWM output 8 bi...

Page 31: ... TxD P60 Input Output Input PCL SGOA P61 SGO SGOF P81 Input Output Input S19 TPO P82 to P87 S18 to S13 P90 to P97 Input Output Port 9 Input S12 to S5 8 bit input output port Input output mode can be specified bit wise Can be set in I O port mode or segment output mode in 2 bit units by using LCD display control register LCDC Port 0 8 bit input output port Input output mode can be specified bit wis...

Page 32: ...ng Input SGOA P60 SGOA Output Sound generator signal output Input PCL P60 SGOF SGO P61 SGO SGOF P61 TPO Output Prescaler output of 16 bit timer TM0 Input P81 S19 S0 to S4 Output Segment signal output of LCD controller driver Output S5 to S12 Input P97 to P90 S13 to S18 P87 to P82 S19 P81 TPO COM0 to COM3 Output Common signal output of LCD controller driver Output VLCD LCD driving power supply SM11...

Page 33: ...s with specifiable valid edges rising edge falling edge both rising and falling edges 2 2 2 P10 to P14 Port 1 These pins constitute a 5 bit input only port In addition they are also used to input A D converter analog signals The following operating modes can be specified bit wise 1 Port mode In this mode P10 to P14 function as a 5 bit input only port 2 Control mode In this mode P10 to P14 function...

Page 34: ...tion as a 5 bit input output port They can be set bit wise in the input or output mode by using port mode register 4 PM4 2 Control mode In this mode P40 to P44 function as timer input output pins a TIO2 TIO3 Timer output pins b TI00 to TI02 These pins input a capture trigger signal to the 16 bit timer capture registers CR00 to CR02 2 2 6 P50 to P54 Port 5 These pins constitute a 5 bit input output...

Page 35: ...hout amplitude signal output pin c SGO Sound generator with amplitude signal output pin d SGOA Sound generator amplitude signal output pin 2 2 8 P81 to P87 Port 8 These pins constitute a 7 bit input output port In addition they also function as output pins for segment signals from the internal LCD controller driver and one of them as a prescaler signal output pin The following operating modes can ...

Page 36: ...uts 2 2 11 VLCD This pin supplies a voltage to drive an LCD 2 2 12 AVREF This is an A D converter reference voltage input pin This pin also functions as an analog power supply pin Supply power to this pin when the A D converter is used When A D converter is not used connect this pin to VSS 2 2 13 AVSS This is a ground voltage pin of A D converter Always use the same voltage as that of the VSS pin ...

Page 37: ...nternally Connected pin is provided to set the test mode to check the µPD780973 A before shipment In the normal operating mode directly connect this pin to the VSS pin with as short a wiring length as possible When a potential difference is generated between the IC pin and VSS pin because the wiring between those two pins is too long or external noise is input to the IC pin the user s program may ...

Page 38: ...y connect to VSS via a resistor P01 INTP1 P02 INTP2 P03 to P07 P10 ANI0 to P14 ANI4 9 Input Independently connect to VDD or VSS via a resistor P20 SM11 to P23 SM14 4 Output Leave open P24 SM21 to P27 SM24 P30 SM31 to P33 SM34 P34 SM41 to P37 SM44 P40 TI00 to P42 TI02 8 Input output Independently connect to VDD or VSS via a resistor P43 TIO2 P44 TIO3 P50 SCK P51 SO 5 P52 SI 8 P53 RxD P54 TxD 5 P60 ...

Page 39: ... ch IN OUT VDD N ch P ch VDD pullup enable Type 4 data output disable P ch OUT VDD N ch Type 8 A Type 8 Type 9 data output disable P ch IN OUT VDD N ch data output disable input enable P ch IN OUT VDD N ch input enable Comparator P ch N ch VREF Threshold voltage IN Push pull output whose output can go into a high impedance state both P ch and N ch are off ...

Page 40: ...2 Type 17 Type 18 Type 17 G VLC0 VLC1 SEG data VLC2 P ch N ch P ch N ch P ch N ch OUT VLC0 VLC1 COM data VLC2 P ch N ch P ch N ch P ch N ch OUT N ch P ch VLC0 VLC1 SEG data VLC2 P ch N ch P ch N ch P ch N ch P ch N ch input enable output disable data IN OUT VDD ...

Page 41: ... 32 8 bits Internal ROM 24576 8 bits 5FFFH 1000H 0FFFH 0800H 07FFH 0080H 007FH 0040H 003FH 0000H CALLF Entry Area CALLT Table Area Vector Table Area Program Area Program Area LCD Display RAM 20 4 bits Reserved Program memory space 6000H 5FFFH FA59H FA58H FA6DH FA6CH FEE0H FEDFH FF00H FEFFH FFFFH Internal High speed RAM 768 8 bits Special Function Registers SFRs 256 8 bits Reserved FC00H FBFFH Rese...

Page 42: ...H 007FH 0040H 003FH 0000H CALLF Entry Area CALLT Table Area Vector Table Area Program Area Program Area LCD Display RAM 20 4 bits Reserved Program memory space 8000H 7FFFH FA59H FA58H FA6DH FA6CH FEE0H FEDFH FF00H FEFFH FFFFH Internal High speed RAM 1024 8 bits Special Function Registers SFRs 256 8 bits Reserved FB00H FAFFH Reserved EEPROM 256 8 bits FA00H F9FFH F900H F8FFH ...

Page 43: ...emory space 1 Vector table area The 64 byte area 0000H to 003FH is reserved as a vector table area This area stores program start addresses to which execution branches when the RESET signal is input or when an interrupt request is generated Of a 16 bit address the lower 8 bits are stored at an even address and the higher 8 bits are stored at an odd address Table 3 2 Vector Table Vector Table Addre...

Page 44: ...3 A 768 8 bits FC00H to FEFFH µPD78F0974 1024 8 bits FB00H to FEFFH The 32 byte area FEE0H to FEFFH is allocated with four general purpose register banks composed of eight 8 bit registers The internal high speed RAM can be used as stack memory 2 LCD display RAM An LCD display RAM is allocated to a 20 4 bits area consisting of FA59H to FA6CH The LCD display RAM can also be used as a normal RAM 3 1 ...

Page 45: ...r special addressing methods designed for the functions of special function registers SFR and general purpose registers are available for use Data memory addressing is illustrated in Figures 3 3 and 3 4 For the details of each addressing mode see 3 4 Operand Address Addressing Figure 3 3 Data Memory Addressing µPD780973 A 0000H General Registers 32 8 bits Internal ROM 24576 8 bits LCD Display RAM ...

Page 46: ... FA58H FA6DH FA6CH FEE0H FEDFH FF00H FEFFH FFFFH Internal High speed RAM 1024 8 bits Reserved FB00H FAFFH FF20H FF1FH FE20H FE1FH Special Function Registers SFRs 256 8 bits SFR Addressing Register Addressing Short Direct Addressing Direct Addressing Register Indirect Addressing Based Addressing Based Indexed Addressing FA00H F9FFH Reserved F900H F8FFH Reserved EEPROM 256 8 bits ...

Page 47: ...tched When a branch instruction is executed immediate data and register contents are set RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter Figure 3 5 Program Counter Configuration PC 15 0 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 2 Program status word PSW The program status word is an 8 bit register consisting of various ...

Page 48: ...liary carry flag AC If the operation result has a carry from bit 3 or a borrow at bit 3 this flag is set to 1 It is reset to 0 in all other cases e In service priority flag ISP This flag manages the priority of acknowledgeable maskable vectored interrupts When this flag is 0 low level vectored interrupts specified with a priority specify flag register PR0L PR0H PR1L refer to 19 3 3 Priority specif...

Page 49: ...nstruction execution Figure 3 8 Data to be Saved to Stack Memory SP 15 0 SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 Interrupt and BRK Instruction PSW PC15 to PC8 PC15 to PC8 PC7 to PC0 Register Pair Low SP SP _ 2 SP _ 2 Register Pair High CALL CALLF and CALLT Instructions PUSH rp Instruction SP _ 1 SP SP SP _ 2 SP _ 2 SP _ 1 SP PC7 to PC0 SP _ 3 SP _ 2 SP _ 1 SP SP SP _ ...

Page 50: ...bsolute names R0 to R7 and RP0 to RP3 Register banks to be used for instruction execution are set with the CPU control instruction SEL RBn Because of the 4 register bank configuration an efficient program can be created by switching between a register for normal processing and a register for interrupt processing for each bank Figure 3 10 General Register Configuration a Absolute Name BANK0 BANK1 B...

Page 51: ...ruction operand sfr This manipulation can also be specified with an address 16 bit manipulation Describe the symbol reserved with assembler for the 16 bit manipulation instruction operand sfrp When addressing an address describe an even address Table 3 5 gives a list of special function registers The meaning of items in the table is as follows Symbol Symbol indicating the address of a special func...

Page 52: ...ter 3 CR3 FF0DH 8 bit counter 1 TM1 R FF0EH 8 bit counter 2 TM2 FF0FH 8 bit counter 3 TM3 FF10H Capture register 00 CR00 0000H FF11H FF12H Capture register 01 CR01 FF13H FF14H Capture register 02 CR02 FF15H FF16H 16 bit timer register TM0 FF17H FF18H Serial I O shift register SIO R W 00H FF19H Transmit shift register TXS W FFH Receive buffer register RXB R FFH FF1BH A D conversion result register ...

Page 53: ... EGN FF4AH LCD timer control register LCDTM W FF61H Compare register sin side MCMP10 R W FF62H Compare register cos side MCMP11 FF63H Compare register sin side MCMP20 FF64H Compare register cos side MCMP21 FF65H Compare register sin side MCMP30 FF66H Compare register cos side MCMP31 FF67H Compare register sin side MCMP40 FF68H Compare register cos side MCMP41 FF69H Timer mode control register MCNT...

Page 54: ...r control register SGBR FF96H Sound generator amplitude register SGAM FFA0H Oscillator mode register Note 1 OSCM FFB0H LCD display mode register LCDM FFB2H LCD display control register LCDC FFE0H Interrupt request flag register 0L IF0 IF0L FFE1H Interrupt request flag register 0H IF0H FFE2H Interrupt request flag register 1L IF1L FFE4H Interrupt mask flag register 0L MK0 MK0L FFH FFE5H Interrupt m...

Page 55: ...ction The value obtained by adding 8 bit immediate data displacement value jdisp8 of an instruction code to the start address of the following instruction is transferred to the program counter PC and branched The displacement value is treated as signed two s complement data 128 to 127 and bit 7 becomes a sign bit In other words relative addressing consists in relative branching from the start addr...

Page 56: ... or BR addr16 or CALLF addr11 instruction is executed CALL addr16 and BR addr16 instructions can be branched to the entire memory space The CALLF addr11 instruction is branched to the 0800H to 0FFFH area Operation In the case of CALL addr16 and BR addr16 instructions In the case of CALLF addr11 instruction 15 0 PC 8 7 7 0 CALL or BR Low Addr High Addr 15 0 PC 8 7 7 0 fa10 8 11 10 0 0 0 0 1 6 4 3 C...

Page 57: ...ruction references the address stored in the memory table from 40H to 7FH and allows branching to the entire memory space Operation 3 3 4 Register addressing Function Register pair AX contents to be specified with an instruction word are transferred to the program counter PC and branched This function is carried out when the BR AX instruction is executed Operation 15 1 15 0 PC 7 0 Low Addr High Ad...

Page 58: ...ter to be Specified by Implied Addressing MULU Register A for multiplicand and register AX for product storage DIVUW Register AX for dividend and quotient storage ADJBA ADJBS Register A for storage of numeric values subject to decimal adjustment ROR4 ROL4 Register A for storage of digit data subject to digit rotation Operand format Because implied addressing can be automatically employed with an i...

Page 59: ...t is executed When an 8 bit register is specified one of the eight registers is specified with 3 bits in the operation code Operand format Identifier Description r X A C B E D L H rp AX BC DE HL r and rp can be described with function names X A C B E D L H AX BC DE and HL as well as absolute names R0 to R7 and RP0 to RP3 Description example MOV A C when selecting C register as r Operation code 0 1...

Page 60: ...a in an instruction word becoming an operand address Operand format Identifier Description addr16 Label or 16 bit immediate data Description example MOV A 0FE00H when setting addr16 to FE00H Operation code 1 0 0 0 1 1 1 0 OP code 0 0 0 0 0 0 0 0 00H 1 1 1 1 1 1 1 0 FEH Operation Memory 0 7 addr16 lower addr16 upper OP code ...

Page 61: ...nt counter are mapped and these SFRs can be manipulated with a small number of bytes and clocks When 8 bit immediate data is at 20H to FFH bit 8 of an effective address is set to 0 When it is at 00H to 1FH bit 8 is set to 1 Refer to Operation below Operand format Identifier Description saddr Label or FE20H to FF1FH immediate data saddrp Label or FE20H to FF1FH immediate data even address only Desc...

Page 62: ...nd FFE0H to FFFFH However the SFR mapped at FF00H to FF1FH can be accessed with short direct addressing Operand format Identifier Description sfr Special function register name sfrp 16 bit manipulatable special function register name even address only Description example MOV PM0 A when selecting PM0 FF20H as sfr Operation code 1 1 1 1 0 1 1 0 OP code 0 0 1 0 0 0 0 0 20H sfr offset Operation 15 0 S...

Page 63: ...ct flags RBS0 and RBS1 and the register pair specification code in the operation code This addressing can be carried out for all the memory spaces Operand format Identifier Description DE HL Description example MOV A DE when selecting DE as register pair Operation code 1 0 0 0 0 1 0 1 Operation 16 0 8 D 7 E 0 7 7 0 A DE The contents of the memory addressed are transferred Memory The memory address...

Page 64: ...Description example MOV A HL 10H when setting byte to 10H Operation code 1 0 1 0 1 1 1 0 0 0 0 1 0 0 0 0 3 4 8 Based indexed addressing Function The B or C register contents specified in an instruction word are added to the contents of the base register that is the HL register pair in an instruction word of the register bank specified with the register bank select flags RBS0 and RBS1 and the sum i...

Page 65: ...This addressing method is automatically employed when the PUSH POP subroutine call and RETURN instructions are executed or the register is saved reset upon generation of an interrupt request Stack addressing enables to address the internal high speed RAM area only Description example In the case of PUSH DE Operation code 1 0 1 1 0 1 0 1 ...

Page 66: ...66 MEMO ...

Page 67: ...even when the power is cut off 2 Can be manipulated with 8 bit memory manipulation instructions in the same way as ordinary RAM 3 Erasure and writing is performed in the time set with EWCS0 and EWCS1 EEPROM write control register EEWC bits 4 and 5 see Figure 4 2 Therefore the write time control software load is reduced Moreover during writing instructions other than instructions related to EEPROM ...

Page 68: ...egister EEWC that controls EEPROM writing and an area that generates an interrupt request signal INTWE upon detecting write termination Figure 4 1 EEPROM Block Diagram INTWE EWCS1 EWCS0 EWCC EWE EWST EEPROM 256 8 bits Prescaler Read write controller EEPROM timer Data latch fX Internal bus EEPROM write control register EEWC Address latch Write termination ...

Page 69: ...0 write is disabled 1 Currently writing to EEPROM EEPROM write read is disabled EWE EEPROM Write Operation Control 0 EEPROM write disabled 1 EEPROM write enabled Notes 1 Set the main system clock frequency fX in the range of 4 to 5 120 MHz 2 Set the main system clock frequency fX in the range of 5 364 to 8 38 MHz Cautions 1 If the main system clock frequency is set in the range of 5 120 fX 5 364 M...

Page 70: ...WST is 0 If an EEPROM read instruction is executed during EEPROM write read values are undefined 2 If reading EEPROM contents immediately after changing EWCC EEPROM write control register EEWC bit 2 from 1 to 0 set a wait time of at least 20 µs by software If no wait time is set the correct values cannot be read Example Insertion of NOP instructions to set wait time of 20 µs or more CLR1 EWCC NOP ...

Page 71: ...ting 1 data wait for generation of write termination interrupt request while processing other than write is performed When write termination interrupt request is generated start next write operation 2 Method using write status flag EWST Poll EWST EEPROM write control register EEWC bit 1 and wait for EWST to become 0 When EWST becomes 0 start the next write operation 4 6 EEPROM Control Related Inte...

Page 72: ...ven if the mode changes to HALT mode during EEPROM writing writing is continued 5 If the mode changes to STOP mode during EEPROM writing the data being written becomes undefined If this STOP mode is cancelled by interrupt request a write termination interrupt request INTWE is generated after the STOP mode has been cancelled If you want to set the STOP mode after normally terminating write processi...

Page 73: ...t port pins Figure 5 1 shows the port configuration Every port can be manipulated in 1 bit or 8 bit units controlled in various ways Moreover the port pins can also serve as I O pins of the internal hardware Figure 5 1 Port Types P00 Port 0 P10 Port 1 P14 P20 Port 2 P27 P30 Port 4 Port 5 Port 6 Port 9 P40 P44 P50 P54 P60 P61 Port 8 P81 P87 P90 P97 Port 3 P37 P07 ...

Page 74: ... PCL SGOA P61 SGO SGOF P81 Input Output S19 TPO P82 to P87 S18 to S13 P90 to P97 Input Output Port 9 S12 to S5 8 bit input output port Input output mode can be specified bit wise Can be set in input output port or segment output mode in 2 bit units by using LCD display control register LCDC Port 0 8 bit input output port Input output mode can be specified bit wise If used as an input port an on ch...

Page 75: ...pecify the input mode output mode in 1 bit units with the port mode register 0 PM0 When P00 to P07 pins are used as input ports an on chip pull up resistor can be used to them in 1 bit units with a pull up resistor option register PU0 Alternate functions include external interrupt request input RESET input sets port 0 to input mode Figure 5 2 shows a block diagram of port 0 Caution Because port 0 ...

Page 76: ...7 Selector VDD Internal bus PU Pull up resistor option register PM Port mode register RD Port 0 read signal WR Port 0 write signal 5 2 2 Port 1 Port 1 is a 5 bit input only port Alternate functions include an A D converter analog input Figure 5 3 shows a block diagram of port 1 Figure 5 3 P10 to P14 Block Diagram RD P10 ANI0 P14 ANI4 Internal bus RD Port 1 read signal ...

Page 77: ... PWM output RESET input sets port 2 to high impedance state Figure 5 4 shows a block diagram of port 2 Figure 5 4 P20 to P27 Block Diagram PM Port mode register RD Port 2 read signal WR Port 2 write signal Caution When PM2 is set to 0 read operation is enabled When PM2 is set to 1 read operation is disabled Remark n 1 2 P20 SM11 to P23 SM14 P24 SM21 to P27 SM24 WRPORT WRPM Output latch P20 to P27 ...

Page 78: ... PWM output RESET input sets port 3 to high impedance state Figure 5 5 shows a block diagram of port 3 Figure 5 5 P30 to P37 Block Diagram PM Port mode register RD Port 3 read signal WR Port 3 write signal Caution When PM3 is set to 0 read operation is enabled When PM3 is set to 1 read operation is disabled Remark n 3 4 P30 SM31 to P33 SM34 P34 SM41 to P37 SM44 WRPORT WRPM Output latch P30 to P37 ...

Page 79: ... register 4 PM4 Alternate functions also include timer input output RESET input sets port 4 to input mode Figure 5 6 shows a block diagram of port 4 Figure 5 6 P40 to P44 Block Diagram PM Port mode register RD Port 4 read signal WR Port 4 write signal RD P40 TI00 to P42 TI02 P43 TIO2 P44 TIO3 WRPORT WRPM Output latch P40 to P44 PM40 to PM44 Alternate functions Selector Internal bus ...

Page 80: ...Alternate functions include serial interface data input output and clock input output RESET input sets port 5 to input mode Figure 5 7 shows a block diagram of port 5 Figure 5 7 P50 to P54 Block Diagram PM Port mode register RD Port 5 read signal WR Port 5 write signal RD P50 SCK P51 SO P52 SI P53 RxD P54 TxD WRPORT WRPM Output latch P50 to P54 PM50 to PM54 Alternate functions Selector Internal bu...

Page 81: ...de register 6 PM6 Alternate functions include clock output and sound generator output RESET input sets port 6 to input mode Figure 5 8 shows a block diagram of port 6 Figure 5 8 P60 and P61 Block Diagram PM Port mode register RD Port 6 read signal WR Port 6 write signal RD P60 PCL SGOA P61 SGO SGOF WRPORT WRPM Output latch P60 P61 PM60 PM61 Alternate functions Selector Internal bus ...

Page 82: ...put output port can be switched by setting the LCD display control register LCDC RESET input sets port 8 to input mode Figures 5 9 and 5 10 show block diagrams of port 8 Figure 5 9 P81 Block Diagram Figure 5 10 P82 to P87 Block Diagram PM Port mode register RD Port 8 read signal WR Port 8 write signal RD P81 S19 TPO WRPORT WRPM PM81 Selector Output latch P81 Internal bus Segment output function Al...

Page 83: ...gnal output of the LCD controller driver Segment output and input output port can be switched by setting the LCD display control register LCDC RESET input sets port 9 to input mode Figure 5 11 shows a block diagram of port 9 Figure 5 11 P90 to P97 Block Diagram PM Port mode register RD Port 9 read signal WR Port 9 write signal RD P90 S12 to P97 S5 WRPORT WRPM PM90 to PM97 Selector Output latch P90...

Page 84: ...anipulation instruction RESET input sets registers to FFH Cautions 1 Pins P10 and P14 are input only pins and pins P20 to P27 and P30 to P37 are output only pins 2 Port 0 has an alternate function as external interrupt request input when the port function output mode is specified and the output level is changed the interrupt request flag is set When the output mode is used therefore the interrupt ...

Page 85: ...ith the LCD display control register LCDC Caution When port 5 is used for serial interface the I O latch or output latch must be set according to their function For the setting methods see Figure 14 2 Asynchronous Serial Interface Mode Register ASIM Format and Figure 15 2 Serial Operation Mode Register CSIM Format Remark don t care PM port mode register P port output latch P00 INTP0 Input 1 P01 IN...

Page 86: ...2 1 0 PM8 PM87 PM86 PM85 PM84 PM83 PM82 PM81 1 Address FF29H After Reset FFH R W Symbol 7 6 5 4 3 2 1 0 PM9 PM97 PM96 PM95 PM94 PM93 PM92 PM91 PM90 PMmn Pmn Pin Input Output Mode Select m 0 4 to 6 8 9 n 0 to 7 0 Output Mode Output buffer on 1 Input Mode Output buffer off Figure 5 13 Port Mode Register PM2 PM3 Format Address FF22H After Reset FFH R W Symbol 7 6 5 4 3 2 1 0 PM2 PM27 PM26 PM25 PM24 P...

Page 87: ...ed with PU0 No pull up resistors can be used to the bits set to the output mode irrespective of PU0 setting PU0 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets this register to 00H Figure 5 14 Pull Up Resistor Option Register PU0 Format Address FF30H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 PU0 PU07 PU06 PU05 PU04 PU03 PU02 PU01 PU00 PU0m P0m Pin Internal Pull Up Re...

Page 88: ...ontents for pins specified as input are undefined even for bits other than the manipulated bit 5 4 2 Reading from input output port 1 Output mode The output latch contents are read by a transfer instruction The output latch contents do not change 2 Input mode The pin status is read by a transfer instruction The output latch contents do not change 5 4 3 Operations on input output port 1 Output mode...

Page 89: ...figuration The clock generator consists of the following hardware Table 6 1 Clock Generator Configuration Item Configuration Control register Processor clock control register PCC Oscillator mode register OSCM Note Oscillator Main system clock oscillator Note µPD780973 A only Figure 6 1 Clock Generator Block Diagram X1 X2 Main system clock oscillator HALFOSC fX Prescaler fX 2 fX 22 fX 23 fX 24 Pres...

Page 90: ...PCC1 PCC0 PCC2 PCC1 PCC0 CPU Clock fCPU Select 0 0 0 fX 0 0 1 fX 2 0 1 0 fX 22 0 1 1 fX 23 1 0 0 fX 24 Other than above Setting prohibited Caution Bits 3 to 7 must be set to 0 Remark fX Main system clock oscillation frequency The fastest instructions of the µPD780973 Subseries are executed in two CPU clocks Therefore the relation between the CPU clock fCPU and the minimum instruction execution tim...

Page 91: ...ator Mode Register OSCM Format Address FFA0H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 OSCM HALFOSC 0 0 0 0 0 0 0 HALFOSC Oscillator Mode Selection 0 Normal operation mode 1 Reduced current consumption mode only when operated at fX 4 to 4 19 MHz Cautions 1 This function is available only when the device is operated at fX 4 to 4 19 MHz In other cases be sure not to set 1 to bit 7 2 When using in n...

Page 92: ...1 pin and an inverted clock signal to the X2 pin Figure 6 4 shows an external circuit of the main system clock oscillator Figure 6 4 External Circuit of Main System Clock Oscillator a Crystal and ceramic oscillation b External clock Crystal resonator or ceramic resonator X2 X1 PD74HCU04 External clock X2 X1 IC µ Caution Do not execute the STOP instruction while an external clock is input This is b...

Page 93: ...the wiring in the vicinity of a line through which a high alternating current flows Always keep the ground of the capacitor of the oscillator at the same potential as VSS Do not ground the capacitor to a ground pattern through which a high current flows Do not fetch signals from the oscillator Figure 6 5 shows examples of resonator having bad connection Figure 6 5 Incorrect Examples of Resonator C...

Page 94: ...rent d Current flowing through ground line of oscillator potential at points A B and C fluctuates IC X2 X1 IC X2 X1 A B C Pmn VDD High current High current e Signals are fetched IC X2 X1 6 4 2 Divider circuit The divider circuit divides the output of the main system clock oscillation circuit fX to generate various clocks ...

Page 95: ...es of CPU clocks 0 24 µs 0 48 µs 0 95 µs 1 91 µs and 3 81 µs at 8 38 MHz operation can be selected by the PCC setting c Two standby modes STOP and HALT can be used d The clock to the peripheral hardware is supplied by dividing the main system clock The other peripheral hardware is stopped when the main system clock is stopped except however the external clock input operation e The µPD780973 A can ...

Page 96: ... Required for Switching CPU Clock Set Value after Switching PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 0 0 0 16 instructions 16 instructions 16 instructions 16 instructions 0 0 1 8 instructions 8 instructions 8 instructions 8 instructions 0 1 0 4 instructions 4 instructions 4 instructions 4 instructions 0 1 1 2 instructio...

Page 97: ...ication The effect of resetting is released when the RESET pin is later made high and the main system clock starts oscillating At this time the time during which oscillation stabilizes 217 fX is automatically secured After that the CPU starts instruction execution at the slowest speed of the main system clock 3 81 µs at 8 38 MHz operation 2 After the time during which the VDD voltage rises to the ...

Page 98: ...98 MEMO ...

Page 99: ... used to serve as an interval timer and an external event counter and to output square waves with any selected frequency PWM output See CHAPTER 9 8 BIT TIMER EVENT COUNTERS 2 3 TM2 TM3 4 Watch timer This timer can set a flag every 0 5 sec and simultaneously generates interrupt request at the preset time intervals See CHAPTER 10 WATCH TIMER 5 Watchdog timer This timer can perform the watchdog timer...

Page 100: ...on Timer output PWM output Pulse width measurement Square wave output Divided output Interrupt request Notes 1 Watch timer can perform both watch timer and interval timer functions at the same time 2 Watchdog timer can perform either the watchdog timer function or the interval timer function as selected 7 2 16 Bit Timer 0 Functions The 16 bit timer 0 TM0 has the following functions Pulse width mea...

Page 101: ...register CR02 Edge detection circuit Edge detection circuit Edge detection circuit ES01 ES00 TPOE ES11 ES10 ES21 ES20 16 bit capture register CR01 16 bit capture register CR00 INTOVF INTTM02 INTTM01 INTTM00 ES21 ES20 ES11 fX 8 fX 16 fX 32 fX 64 ES10 ES01 CRC01 TMC02 TPOE CRC00 ES00 PRM01 PRM00 Prescaler mode register PRM0 Capture pulse control register CRC0 16 bit timer mode control register TMC0 ...

Page 102: ...e trigger Setting of the TI00 valid edge is performed by setting of the prescaler mode register PRM0 When the valid edge of the TI00 is detected an interrupt request INTTM00 is generated CR00 is read by a 16 bit memory manipulation instruction After RESET input the value of CR00 is undefined 3 Capture register 01 CR01 The valid edge of the TI01 pin can be selected as the capture trigger Setting of...

Page 103: ...TMC0 is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears TMC0 value to 00H Figure 7 2 16 Bit Timer Mode Control Register TMC0 Format Address FF72H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 TMC0 0 0 0 0 0 TMC02 0 TPOE TMC02 Timer 0 Operating Mode Selection 0 Operation stop TM0 cleared to 0 1 Operation enabled TPOE Timer 0 Prescaler Output Control 0 Prescaler signal outp...

Page 104: ...lation instruction RESET input sets CRC0 value to 04H Figure 7 3 Capture Pulse Control Register CRC0 Format Address FF71H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 CRC0 0 0 0 0 0 0 CRC01 CRC00 CRC01 CRC00 Capture Pulse Selection 0 0 Does not divide capture pulse 0 1 Divides capture pulse by 2 1 0 Divides capture pulse by 4 1 1 Divides capture pulse by 8 Cautions 1 Timer operation must be stopped ...

Page 105: ...PRM0 ES21 ES20 ES11 ES10 ES01 ES00 PRM01 PRM00 ES21 ES20 TI02 Valid Edge Selection 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both falling and rising edges ES11 ES10 TI01 Valid Edge Selection 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both falling and rising edges ES01 ES00 TI00 Valid Edge Selection 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both ...

Page 106: ...e selected rising falling or both edges by means of bits 2 and 3 ES00 and ES01 of PRM0 For valid edge detection sampling is performed at the count clock selected by PRM0 and a capture operation is only performed when a valid level is detected twice thus eliminating noise with a short pulse width Figure 7 5 Configuration Diagram for Pulse Width Measurement by Free Running Counter fX 23 fX 24 fX 25 ...

Page 107: ...its 6 and 7 ES20 and ES21 of PRM0 is input to the TI02 P42 pin the value of TM0 is taken into 16 bit capture register 02 CR02 and external interrupt request signal INTTM02 is set Any of three edge specifications can be selected rising falling or both edges as the valid edges for the TI00 P40 to TI02 P42 pins by means of bits 2 and 3 ES00 and ES01 bits 4 and 5 ES10 and ES11 and bits 6 and 7 ES06 an...

Page 108: ...Free Running Counter with Both Edges Specified Count clock TM0 count value TI0m pin input Value loaded to CR0m INTTM0m TI0n pin input Value loaded to CR0n INTTM0n INTOVF D1 D0 t 10000H D0 D2 t 10000H D1 D2 1 t D3 D2 t t 0000H 0001H D0 D1 FFFFH 0000H D2 D3 D3 D1 D0 D1 D2 Remark m 0 to 2 n 1 2 ...

Page 109: ...t capture register 0m CR0m read CR0m performs capture operation but the capture value is not guaranteed However the interrupt request flag INTTM0m is set upon detection of the valid edge Figure 7 10 Capture Register Data Retention Timing Count pulse TM0 count value Edge input Interrupt request flag Capture read signal CR0m interrupt value N N 1 N 2 M M 1 M 2 X N 1 Capture operation Remark m 0 to 2...

Page 110: ...n has been started TMC02 of TMC0 has been set to 1 with a high level applied to input pins TI00 to TI02 of 16 bit timer 0 and with the rising edge with ESn1 and ESn0 of PRM0 set to 0 1 or both the rising and falling edges with ESn1 and ESn0 of PRM0 set to 1 1 selected However INTTM0n does not occur if a low level is applied to TI00 to TI02 ...

Page 111: ...r Figure 8 1 shows timer 1 block diagram Figure 8 1 Timer 1 TM1 Block Diagram Internal bus Internal bus 8 bit compare register 1 CR1 8 bit counter TM1 Clear Coincidence INTTM1 3 Timer mode control register TMC1 Timer clock select register 1 TCL1 TCE1 TCL12 TCL11 TCL10 fX 23 fX 24 fX 25 fX 27 fX 29 fX 211 Selector ...

Page 112: ... counts the count pulses The counter is incremented in synchronization with the rising edge of the count clock When count value is read during operation count clock input is temporary stopped and then the count value is read In the following situations the count value is set to 00H 1 RESET input 2 Clear TCE1 3 Match between TM1 and CR1 2 8 bit compare register 1 CR1 The value set in the CR1 is con...

Page 113: ...Figure 8 2 Timer Clock Select Register 1 TCL1 Format Address FF73H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 TCL1 0 0 0 0 0 TCL12 TCL11 TCL10 TCL12 TCL11 TCL10 Count Clock Selection 0 0 0 Setting prohibited 0 0 1 Setting prohibited 0 1 0 fX 23 1 04 MHz 0 1 1 fX 24 523 kHz 1 0 0 fX 25 261 kHz 1 0 1 fX 27 65 4 kHz 1 1 0 fX 29 16 3 kHz 1 1 1 fX 211 4 09 kHz Cautions 1 When rewriting TCL1 to other da...

Page 114: ...pulation instruction RESET input sets to 04H Figure 8 3 shows TMC1 format Figure 8 3 8 Bit Timer Mode Control Register 1 TMC1 Format Address FF76H After Reset 04H R W Symbol 7 6 5 4 3 2 1 0 TMC1 TCE1 0 0 0 0 1 0 0 TCE1 Timer 1 Count Operation Control 0 After clearing counter to 0 count operation disabled 1 Count operation start Caution Be sure to set 0 to bit 0 bit 1 and bits 3 to 6 and set 1 to b...

Page 115: ...d with bits 0 to 2 TCL10 to TCL12 of the timer clock select register 1 TCL1 Setting 1 Set the registers TCL1 Select count clock CR1 Compare value 2 After TCE1 1 is set count operation starts 3 If the values of TM1 and CR1 match the INTTM1 is generated and TM1 is cleared to 00H 4 INTTM1 generates repeatedly at the same interval Set TCE1 to 0 to stop count operation Figure 8 4 Interval Timer Operati...

Page 116: ...ion Timings 2 3 b When CR1 00H t Count clock TM1 CR1 TCE1 INTTM1 TM1 interval time Interval time 00H 00H 00H 00H 00H c When CR1 FFH t Count clock TM1 CR1 TCE1 INTTM1 TM1 interval time 01 FE FF 00 FE FF 00 FF FF FF Interval time Interrupt received Interrupt received ...

Page 117: ...d Operated by CR1 transition M N Count clock TM1 CR1 TCE1 INTTM1 TM1 interval time 00H N N M N FFH 00H M 00H M CR1 transition TM1 overflows since M N e Operated by CR1 transition M N Count clock TM1 CR1 TCE1 INTTM1 TM1 interval time N 1 N N 00H 01H N M 1 M 00H 01H M CR1 transition ...

Page 118: ...8 bit compare register 1 CR1 is changed are smaller than the value of 8 bit timer register 1 TM1 TM1 continues counting overflows and then restarts counting from 0 Thus if the value M after CR1 change is smaller than value N before the change it is necessary to restart the timer after changing CR1 Figure 8 6 Timing after Compare Register Change during Timer Count Operation Count pulse CR1 TM1 coun...

Page 119: ... 2 block diagram and Figure 9 2 shows timer 3 block diagram Figure 9 1 Timer 2 TM2 Block Diagram Note Bit 3 of port mode register PM4 Internal bus 8 bit compare register 2 CR2 8 bit counter 2 TM2 TIO2 P43 fX 211 fX 25 Selector Selector Coincidence Mask circuit OVF Clear 3 Selector TCL22 TCL21 TCL20 Timer clock select register 2 TCL2 Internal bus TCE2 TMC26 LVS2 LVR2 TMC21 TOE2 Invert level Timer m...

Page 120: ...register 3 CR3 8 bit counter 3 TM3 TIO3 P44 fX 212 fX 24 fX 26 Selector Coincidence Mask circuit OVF Clear 3 Selector TCL32 TCL31 TCL30 Timer clock select register 3 TCL3 Internal bus TCE3 TMC36 LVS3 LVR3 TMC31 TOE3 Invert level Timer mode control register 3 TMC3 S R Q R INV Selector INTTM3 S TIO3 P44 P44 output latch PM44 Note fX 27 fX 28 fX 210 Selector ...

Page 121: ...e count pulses The counter is incremented in synchronization with the rising edge of the count clock When count value is read during operation count clock input is temporary stopped and then the count value is read In the following situations the count value is set to 00H 1 RESET input 2 Clear TCEn 3 Match between TMn and CRn in clear and start made with match between TMn and CRn Remark n 2 3 2 8 ...

Page 122: ...struction RESET input sets to 00H Figure 9 3 Timer Clock Select Register 2 TCL2 Format Address FF74H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 TCL2 0 0 0 0 0 TCL22 TCL21 TCL20 TCL22 TCL21 TCL20 Count Clock Selection 0 0 0 TIO2 Falling edge 0 0 1 TIO2 Rising edge 0 1 0 fX 23 1 04 MHz 0 1 1 fX 25 261 kHz 1 0 0 fX 27 65 4 kHz 1 0 1 fX 28 32 7 kHz 1 1 0 fX 29 16 3 kHz 1 1 1 fX 211 4 09 kHz Cautions 1...

Page 123: ...o other data stop the timer operation beforehand 2 Set bits 3 to 7 to 0 Remarks 1 fX Main system clock oscillation frequency 2 Figures in parentheses apply to operation with fX 8 38 MHz 2 8 bit timer mode control register n TMCn n 2 3 TMCn is a register which sets up the following five types 1 8 bit counter n TMn count operation control 2 8 bit counter n TMn operating mode selection 3 Timer output...

Page 124: ... between TMn and CRn 1 PWM Free running mode LVSn LVRn Timer Output F F Status Setting 0 0 No change 0 1 Timer output F F reset to 0 1 0 Timer output F F set to 1 1 1 Setting prohibited TMCn1 In Other Modes TMCn6 0 In PWM Mode TMCn6 1 Timer F F Control Active Level Selection 0 Inversion operation disabled Active high 1 Inversion operation enabled Active low TOEn Timer Output Control 0 Output disab...

Page 125: ... TCLn0 to TCLn2 of the timer clock select register n TCLn Setting 1 Set the registers TCLn Select count clock CRn Compare value TMCn Select clear and start mode by match of TMn and CRn TMCn 0000 0B don t care 2 After TCEn 1 is set count operation starts 3 If the values of TMn and CRn match the INTTMn is generated and TMn is cleared to 00H 4 INTTMn generates repeatedly at the same interval Set TCEn...

Page 126: ...Interval Timer Operation Timings 2 3 b When CRn 00H t Count clock TMn CRn TCEn INTTMn TIOn Interval time 00H 00H 00H 00H 00H c When CRn FFH t Count clock TMn CRn TCEn INTTMn TIOn 01 FE FF 00 FE FF 00 FF FF FF Interval time Interrupt received Interrupt received n 2 3 ...

Page 127: ... CRn transition n 2 3 9 4 2 External event counter operation The external event counter counts the number of external clock pulses to be input to the TIOn TMn is incremented each time the valid edge specified with the timer clock select register n TCLn is input Either the rising or falling edge can be selected When the TMn counted values match the values of 8 bit compare register n CRn TMn is clea...

Page 128: ...t 0 TOEn of 8 bit timer mode control register n TMCn to 1 This enables a square wave with any selected frequency to be output duty 50 Setting 1 Set each register Set port latch and port mode register to 0 TCLn Select count clock CRn compare value TMCn Clear and start mode by match of TMn and CRn LVSn LVRn Timer Output F F Status Setting 1 0 High level output 0 1 Low level output Timer output F F i...

Page 129: ... Set port latch P43 P44 and port mode register 4 PM43 PM44 to 0 2 Set active level width with 8 bit compare register CRn 3 Select count clock with timer clock select register n TCLn 4 Set active level with bit 1 TMCn1 of TMCn 5 Count operation starts when bit 7 TCEn of TMCn is set to 1 Set TCEn to 0 to stop count operation PWM output operation 1 PWM output output from TIOn outputs inactive level a...

Page 130: ...H FFH 00H 01H 02H N N 1 FFH 00H 01H 02H M 00H N Active level Active level Inactive level ii CRn 0 Count clock TMn CRn TCEn INTTMn TIOn Inactive level Inactive level 01H 00H FFH 00H 01H 02H N N 1 FFH 00H 01H 02H M 00H 00H N 2 iii CRn FFH TMn CRn TCEn INTTMn TIOn 01H 00H FFH 00H 01H 02H N N 1 FFH 00H 01H 02H M 00H FFH N 2 Inactive level Active level Inactive level Active level Inactive level n 2 3 ...

Page 131: ...00H 01H M M 1 M 2 FFH 00H 01H 02H M M 1 M 2 N 02H M H ii Change of CRn value to N to M after overflow of TMn Count clock TMn CRn TCEn INTTMn TIOn N N 1 N 2 FFH 00H 01H N N 1 N 2 FFH 00H 01H 02H N 02H N H 03H M M M 1 M 2 CRn transition N M iii Change of CRn value to N to M between two clocks 00H and 01H after overflow of TMn Count clock TMn CRn TCEn INTTMn TIOn N N 1 N 2 FFH 00H 01H N N 1 N 2 FFH 0...

Page 132: ...re register n CRn is changed are smaller than the value of 8 bit timer register n TMn TMn continues counting overflows and then restarts counting from 0 Thus if the value M after CRn change is smaller than value N before the change it is necessary to restart the timer after changing CRn Figure 9 11 Timing after Compare Register Change during Timer Count Operation Count pulse CRn TMn count value N ...

Page 133: ...the interval timer can be used simultaneously Figure 10 1 shows watch timer block diagram Figure 10 1 Watch Timer Block Diagram 9 bit prescaler 5 bit counter Selector Selector Selector WTM7 fX 27 fX 211 WTM6 WTM5 WTM4 Internal bus WTM3 WTM1 WTM0 Watch timer mode control register WTM Clear Clear INTWT INTWTI fW 24 fW 25 fW 26 fW 27 fW 28 fW 29 fW ...

Page 134: ...10 1 Interval Timer Interval Time Interval Time When Operated at fX 8 38 MHz 212 1 fX 489 µs 213 1 fX 978 µs 214 1 fX 1 96 ms 215 1 fX 3 91 ms 216 1 fX 7 82 ms 217 1 fX 15 65 ms Remark fX Main system clock oscillation frequency 10 2 Watch Timer Configuration The watch timer consists of the following hardware Table 10 2 Watch Timer Configuration Item Configuration Counter 5 bits 1 Prescaler 9 bits ...

Page 135: ...WTM7 Watch Timer Count Clock Selection 0 fX 27 65 4 kHz 1 fX 211 4 09 kHz WTM6 WTM5 WTM4 Prescaler Interval Time Selection 0 0 0 24 fW 3 91 ms 0 0 1 25 fW 7 82 ms 0 1 0 26 fW 15 6 ms 0 1 1 27 fW 31 2 ms 1 0 0 28 fW 62 5 ms 1 0 1 29 fW 125 ms Other than above Setting prohibited WTM3 Watch Flag Set Time Selection 0 Normal operating mode flag set at fW 214 1 Fast feed operating mode flag set at fW 25...

Page 136: ... the 9 bit prescaler is not cleared the first overflow of the watch timer INTWT after zero second start may include an error of up to 29 1 fW 10 4 2 Interval timer operation The watch timer operates as interval timer which generates interrupt request repeatedly at an interval of the preset count value The interval time can be selected with bits 4 to 6 WTM4 to WTM6 of the watch timer mode control r...

Page 137: ...mer 0H Start Overflow Overflow 5 bit counter Count clock fW or fW 29 Watch timer interrupt INTWT Interval timer interrupt INTWTI Interrupt time of watch timer 0 25 s Interval timer T T Interrupt time of watch timer 0 25 s Remark fW Watch timer clock frequency fW 4 09 kHz fX 8 38 MHz ...

Page 138: ...138 MEMO ...

Page 139: ... register WDTM Figure 11 1 shows the watchdog timer block diagram Figure 11 1 Watchdog Timer Block Diagram Prescaler INTWDT Maskable interrupt request INTWDT Non maskable interrupt request RESET WDTIF WDTMK RUN Selector Control circuit fX 27 fX 212 fX 213 fX 214 fX 215 fX 216 fX 217 fX 218 fX 220 3 Internal bus Internal bus WDCS2WDCS1WDCS0 RUN WDTM4WDTM3 Watchdog timer mode register WDTM Watchdog ...

Page 140: ... fX 15 6 ms 218 1 fX 31 3 ms 220 1 fX 125 ms Remarks 1 fX Main system clock oscillation frequency 2 Figures in parentheses apply to operation with fX 8 38 MHz 2 Interval timer mode Interrupt requests are generated at preset time intervals Table 11 2 Interval Time Interval Time 212 1 fX 489 µs 213 1 fX 978 µs 214 1 fX 1 96 ms 215 1 fX 3 91 ms 216 1 fX 7 82 ms 217 1 fX 15 6 ms 218 1 fX 31 3 ms 220 1...

Page 141: ...f the watchdog timer and the interval timer WDCS is set with an 8 bit memory manipulation instruction RESET input clears WDCS to 00H Figure 11 2 Watchdog Timer Clock Select Register WDCS Format Address FF42H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 WDCS 0 0 0 0 0 WDCS2 WDCS1 WDCS0 WDCS2 WDCS1 WDCS0 Overflow Time of Watchdog Timer Interval Timer 0 0 0 212 fX 489 µs 0 0 1 213 fX 978 µs 0 1 0 214 f...

Page 142: ...ation of an overflow 1 0 Watchdog timer mode 1 Non maskable interrupt request occurs upon generation of an overflow 1 1 Watchdog timer mode 2 Reset operation is activated upon generation of an overflow Notes 1 Once set to 1 RUN cannot be cleared to 0 by software Thus once counting starts it can only be stopped by RESET input 2 Once set to 1 WDTM3 and WDTM4 cannot be cleared to 0 by software Cautio...

Page 143: ... a non maskable interrupt request is generated according to the WDTM bit 3 WDTM3 value The watchdog timer continues operating in the HALT mode but it stops in the STOP mode Thus set RUN to 1 before the STOP mode is set clear the watchdog timer and then execute the STOP instruction Caution The actual runaway detection time may be shorter than the set time by a maximum of 0 5 Table 11 4 Watchdog Tim...

Page 144: ...riority The interval timer continues operating in the HALT mode but it stops in STOP mode Thus set RUN to 1 before the STOP mode is set clear the interval timer and then execute the STOP instruction Cautions 1 Once bit 4 WDTM4 of WDTM is set to 1 with the watchdog timer mode selected the interval timer mode is not set unless RESET input is applied 2 The interval time just after setting with WDTM m...

Page 145: ...ock diagram Figure 12 1 Clock Output Control Circuit Block Diagram fX fX 2 fX 22 fX 23 fX 24 fX 25 fX 26 fX 27 Selector Clock control circuit CLOE CCS2 CCS1 CCS0 PM60 PCL SGOA P60 Clock output selection register CKS Port mode register 6 PM6 P60 output latch 3 Internal bus SGOA Note Note SGOA Sound generator amplitude signal 12 2 Clock Output Control Circuit Configuration The clock output control c...

Page 146: ...ss FF40H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 CKS 0 0 0 CLOE 0 CCS2 CCS1 CCS0 CLOE PCL Output Enable Disable Specification 0 Stop clock division circuit operation 1 Enable clock division circuit operation CCS2 CCS1 CCS0 PCL Output Clock Selection 0 0 0 fX 8 38 MHz 0 0 1 fX 2 4 19 MHz 0 1 0 fX 22 2 09 MHz 0 1 1 fX 23 1 04 MHz 1 0 0 fX 24 524 kHz 1 0 1 fX 25 262 kHz 1 1 0 fX 26 131 kHz 1 1 1 f...

Page 147: ...ut set PM60 and the output latch of P60 to 0 PM6 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM6 to FFH Figure 12 3 Port Mode Register 6 PM6 Format Address FF26H After Reset FFH R W Symbol 7 6 5 4 3 2 1 0 PM6 1 1 1 1 1 1 PM61 PM60 PM6n P6n Pin Input Output Mode Selection n 0 1 0 Output mode output buffer ON 1 Input mode output buffer OFF ...

Page 148: ...SGCR to 1 SGOF output in disabled status 3 Set the P60 output latch to 0 4 Set bit 0 PM60 of port mode register 6 to 0 set to output mode 5 Set bit 4 CLOE of CKS to 1 and enable clock output Remark The clock output control circuit is designed not to output pulses with a small width during output enable disable switching of the clock output As shown in Figure 12 4 be sure to start output from the l...

Page 149: ...erated 2 Power fail detection function This function is to detect a voltage drop in the battery of an automobile The result of A D conversion value of the ADCR1 register and the value of PFT register PFT power fail compare threshold value register are compared If the condition for comparison is satisfied INTAD is generated Figure 13 1 A D Converter Block Diagram ANI0 P10 ANI1 P11 ANI2 P12 ANI3 P13...

Page 150: ...oximation register SAR This register compares the analog input voltage value to the voltage tap compare voltage value applied from the series resistor string and holds the result from the most significant bit MSB When up to the least significant bit LSB is set end of A D conversion the SAR contents are transferred to the A D conversion result register 2 A D conversion result register ADCR1 This re...

Page 151: ...Caution Use ANI0 to ANI4 input voltages within the specification range If a voltage higher than AVREF or lower than AVSS is applied even if within the absolute maximum rating range the conversion value of that channel will be undefined and the conversion values of other channels may also be affected 7 AVREF pin Shared with AVDD pin This pin inputs the A D converter reference voltage This pin also ...

Page 152: ...rigger ADM1 is set with an 8 bit memory manipulation instruction RESET input clears ADM1 to 00H Figure 13 3 A D Converter Mode Register ADM1 Format Address FF80H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 ADM1 ADCS1 0 FR12 FR11 FR10 0 0 0 ADCS1 A D Conversion Operation Control 0 Stop conversion operation 1 Enable conversion operation FR12 FR11 FR10 Conversion Time Selection Note 0 0 0 144 fX 0 0 1...

Page 153: ...ipulation instruction RESET input clears ADS1 to 00H Figure 13 4 Analog Input Channel Specification Register ADS1 Format Address FF81H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 ADS1 0 0 0 0 0 ADS12 ADS11 ADS10 ADS12 ADS11 ADS10 Analog Input Channel Specification 0 0 0 ANI0 0 0 1 ANI1 0 1 0 ANI2 0 1 1 ANI3 1 0 0 ANI4 Other than above Setting prohibited Caution Bits 3 to 7 must be set to 0 ...

Page 154: ...wer fail comparison used to detect power failure PFCM Power Fail Compare Mode Selection 0 ADCR1 PFT Generates interrupt request signal INTAD ADCR1 PFT Does not generate interrupt request signal INTAD 1 ADCR1 PFT Does not generate interrupt request signal INTAD ADCR1 PFT Generates interrupt request signal INTAD Caution Bits 0 to 5 must be set to 0 4 Power fail compare threshold value register PFT T...

Page 155: ...ed with the voltage comparator If the analog input is greater than 1 2 AVREF the MSB of SAR remains set If the analog input is smaller than 1 2 AVREF the MSB is reset 6 Next bit 6 of SAR is automatically set and the operation proceeds to the next comparison The series resistor string voltage tap is selected according to the preset value of bit 7 as described below Bit 7 1 3 4 AVREF Bit 7 0 1 4 AVR...

Page 156: ...version operations are performed continuously until bit 7 ADCS1 of the A D converter mode register ADM1 is reset to 0 by software If a write operation to the ADM1 and analog input channel specification register ADS1 is performed during an A D conversion operation the conversion operation is initialized and if the ADCS1 bit is set to 1 conversion starts again from the beginning RESET input sets the...

Page 157: ... 5 AVREF VIN ADCR1 0 5 AVREF 256 256 where INT Function which returns integer part of value in parentheses VIN Analog input voltage AVREF AVREF pin voltage ADCR1 A D conversion result register ADCR1 value Figure 13 7 shows the relation between the analog input voltage and the A D conversion result Figure 13 7 Relation between Analog Input Voltage and A D Conversion Result 255 254 253 3 2 1 0 A D c...

Page 158: ...diately started A D conversion operations are repeated until new data is written to ADS1 If ADS1 is rewritten during A D conversion operation the A D conversion operation under execution is stopped and A D conversion of a newly selected analog input channel is started If data with ADCS1 set to 0 is written to ADM1 during A D conversion operation the A D conversion operation stops immediately 2 Pow...

Page 159: ...n ADM1 rewrite ADCS1 1 ADS1 rewrite ADCS1 0 A D conversion ADCR1 INTAD PFEN 0 INTAD PFEN 1 ANIn ANIn ANIn ANIm ANIm Stop ANIn ANIn ANIm Conversion suspended Conversion results are not stored First conversion Condition satisfied Remarks 1 n 0 1 4 2 m 0 1 4 ...

Page 160: ...ge In particular if a voltage higher than AVREF or lower than AVSS is input even if within the absolute maximum rating range the conversion value of that channel will be undefined and the conversion values of other channels may also be affected 3 Contending operations 1 Contention between A D conversion result register ADCR1 write and ADCR1 read by instruction upon the end of conversion ADCR1 read...

Page 161: ... ANI0 to ANI4 also function as input port pins P10 to P14 When A D conversion is performed with any of pins ANI0 to ANI4 selected do not execute a port input instruction while conversion is in progress as this may reduce the conversion resolution Also if digital pulses are applied to a pin adjacent to the pin in the process of A D conversion the expected A D conversion value may not be obtainable ...

Page 162: ... not ended When the A D conversion is stopped and then resumed clear ADIF before the A D conversion operation is resumed Figure 13 11 A D Conversion End Interrupt Request Generation Timing ADS1 rewrite start of ANIn conversion A D conversion ADCR1 INTAD ANIn ANIn ANIm ANIm ANIn ANIn ANIm ANIm ADS1 rewrite start of ANIm conversion ADIF is set but ANIm conversion has not ended Remarks 1 n 0 1 4 2 m ...

Page 163: ...tion function Figure 13 12 D A Converter Mode Register DAM1 Format Address FF89H After Reset 00H W Symbol 7 6 5 4 3 2 1 0 DAM1 0 0 0 0 0 0 0 DACE DACE Reference Voltage Control 0 Disabled 1 Enabled when power fail detection function is used Cautions 1 DAM1 is a special register that must be set when debugging is performed with an in circuit emulator Even if this register is used the operation of t...

Page 164: ...164 MEMO ...

Page 165: ...erator can also be used to generate a MIDI standard baud rate 31 25 kbps For details see 14 4 2 Asynchronous serial interface UART mode Figure 14 1 shows the UART block diagram Figure 14 1 UART Block Diagram Internal bus Internal bus Receive buffer register RXB Receive shift register RXS Direction control circuit Direction control circuit Transmit control circuit Baud rate generator Transmit shift...

Page 166: ...A read operation reads values from RXB 2 Receive shift register RXS This register converts serial data input via the RxD pin to parallel data When one byte of data is received at this register the receive data is transferred to the receive buffer register RXB RXS cannot be manipulated directly by a program 3 Receive buffer register RXB This register is used to hold receive data When one byte of da...

Page 167: ...l functions Asynchronous serial interface mode register ASIM Asynchronous serial interface status register ASIS Baud rate generator control register BRGC 1 Asynchronous serial interface mode register ASIM This is an 8 bit register that controls UART s serial transfer operations ASIM is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears the value to 00H Figure 14 2 shows t...

Page 168: ...o parity always added during transmission No parity detection during reception parity errors do not occur 1 0 Odd parity 1 1 Even parity CL Character Length Specification 0 7 bits 1 8 bits SL Stop Bit Length Specification for Transmit Data 0 1 bit 1 2 bits ISRM Receive Completion Interrupt Control when Error Occurs 0 Receive completion interrupt is issued when an error occurs 1 Receive completion ...

Page 169: ...t detected OVE Overrun Error Flag 0 No overrun error 1 Overrun error Note 2 Next receive operation was completed before data was read from receive buffer register Notes 1 Even if a stop bit length of two bits has been set to bit 2 SL in the asynchronous serial interface mode register ASIM stop bit detection during a receive operation only applies to a stop bit length of 1 bit 2 Be sure to read the...

Page 170: ... 16 0 0 0 0 1 fSCK 17 1 0 0 1 0 fSCK 18 2 0 0 1 1 fSCK 19 3 0 1 0 0 fSCK 20 4 0 1 0 1 fSCK 21 5 0 1 1 0 fSCK 22 6 0 1 1 1 fSCK 23 7 1 0 0 0 fSCK 24 8 1 0 0 1 fSCK 25 9 1 0 1 0 fSCK 26 10 1 0 1 1 fSCK 27 11 1 1 0 0 fSCK 28 12 1 1 0 1 fSCK 29 13 1 1 1 0 fSCK 30 14 1 1 1 1 Setting prohibited Cautions 1 Writing to BRGC during a communication operation may cause abnormal output from the baud rate gener...

Page 171: ... Port function 0 1 UART mode Serial function Port function receive only 1 0 UART mode Port function Serial function transmit only 1 1 UART mode Serial function Serial function transmit and receive Cautions 1 Do not switch the operation mode until after the current serial transmit receive operation has stopped 2 Bit 0 must be set to 0 14 4 2 Asynchronous serial interface UART mode This mode enables...

Page 172: ...p Port function Port function 0 1 UART mode Serial function Port function receive only 1 0 UART mode Port function Serial function transmit only 1 1 UART mode Serial function Serial function transmit and receive PS1 PS0 Parity Bit Specification 0 0 No parity 0 1 Zero parity always added during transmission No parity detection during reception parity errors do not occur 1 0 Odd parity 1 1 Even pari...

Page 173: ...Framing error Note 1 Stop bit not detected OVE Overrun Error Flag 0 No overrun error 1 Overrun error Note 2 Next receive operation was completed before data was read from receive buffer register Notes 1 Even if a stop bit length of two bits has been set to bit 2 SL in the asynchronous serial interface mode register ASIM stop bit detection during a receive operation only applies to a stop bit lengt...

Page 174: ... for Baud Rate Generator k 0 0 0 0 fSCK 16 0 0 0 0 1 fSCK 17 1 0 0 1 0 fSCK 18 2 0 0 1 1 fSCK 19 3 0 1 0 0 fSCK 20 4 0 1 0 1 fSCK 21 5 0 1 1 0 fSCK 22 6 0 1 1 1 fSCK 23 7 1 0 0 0 fSCK 24 8 1 0 0 1 fSCK 25 9 1 0 1 0 fSCK 26 10 1 0 1 1 fSCK 27 11 1 1 0 0 fSCK 28 12 1 1 0 1 fSCK 29 13 1 1 1 0 fSCK 30 14 1 1 1 1 Setting prohibited Cautions 1 Writing to BRGC during a communication operation may cause a...

Page 175: ...fX Hz 2n 1 k 16 fX Main system clock oscillation frequency n Value set via TPS0 to TPS2 1 n 8 For details see Table 14 2 k Value set via MDL0 to MDL3 0 k 14 Table 14 2 shows the relation between the 5 bit counter s source clock assigned to bits 4 to 6 TPS0 to TPS2 of BRGC and the n value in the above formula Table 14 2 Relation between 5 bit Counter s Source Clock and n Value TPS2 TPS1 TPS0 5 bit ...

Page 176: ... 1 10 2400 5BH 1 10 4800 4BH 1 10 9600 3BH 1 10 19200 2BH 1 3 31250 21H 1 10 38400 1BH 1 10 76800 0BH 1 10 115200 01H 1 03 Remark fX Main system clock oscillation frequency Figure 14 5 Error Tolerance when k 0 including Sampling Errors Basic timing clock cycle T START D0 D7 P STOP High speed clock clock cycle T enabling normal reception START D0 D7 P STOP Low speed clock clock cycle T enabling nor...

Page 177: ... Parity bit Stop bit 1 data frame Start bit 1 bit Character bits 7 bits or 8 bits Parity bit Even parity odd parity zero parity or no parity Stop bit s 1 bit or 2 bits When 7 bits is selected as the number of character bits only the low order 7 bits bits 0 to 6 are valid so that during a transmission the highest bit bit 7 is ignored and during reception the highest bit bit 7 must be set to 0 The a...

Page 178: ...t include a parity bit and a parity error occurs when the result is an odd number ii Odd parity During transmission The number of bits in transmit data that includes a parity bit is controlled so that there is an odd number of 1 bits The value of the parity bit is as follows If the transmit data contains an odd number of 1 bits the parity bit value is 0 If the transmit data contains an even number...

Page 179: ...g of Asynchronous Serial Interface Transmit Completion Interrupt TxD output D0 D1 D2 D6 D7 Parity STOP START INTST i Stop bit length 1 bit TxD output D0 D1 D2 D6 D7 Parity START INTST ii Stop bit length 2 bits STOP Caution Do not rewrite the asynchronous serial interface mode register ASIM during a transmit operation Rewriting to the ASIM register during a transmit operation may disable further tr...

Page 180: ...he receive data in the shift register is transferred to the receive buffer register RXB and a receive completion interrupt INTSR occurs Even if an error has occurred the receive data in which the error occurred is still transferred to RXB INTSR occurs if bit 1 ISRM of ASIM is cleared to 0 on occurrence of an error If the ISRM bit is set to 1 INTSR does not occur see Figure 14 9 If the RXE bit is r...

Page 181: ... Value Parity error Parity specified during transmission does not match parity of receive data 04H Framing error Stop bit was not detected 02H Overrun error Reception of the next data was completed before data was read from the 01H receive buffer register Figure 14 9 Receive Error Timing RxD input D0 D1 D2 D6 D7 Parity STOP START INTSR Note INTSER when framing overrun error occurs INTSER when pari...

Page 182: ...182 MEMO ...

Page 183: ...s are enabled in 3 wire serial I O mode the processing time for data transfers is reduced The first bit in the 8 bit data in serial transfers is fixed as the MSB 3 wire serial I O mode is useful for connection to a peripheral I O device that includes a clock synchronous serial interface a display controller etc For details see 15 4 2 Three wire serial I O mode Figure 15 1 shows the SIO3 block diag...

Page 184: ...onized with the serial clock SIO is set with an 8 bit memory manipulation instruction When 1 is set to bit 7 CSIE of the serial operation mode register CSIM a serial operation can be started by writing data to or reading data from SIO When transmitting data written to SIO is output via the serial output SO When receiving data is read from the serial input SI and written to SIO The RESET signal res...

Page 185: ... transmit or Master receive Set P50 SCK to the output mode PM50 0 When serial clock input Slave transmit or Slave receive Set P50 to the input mode PM50 1 When transmit transceive mode Set P51 SO to the output mode PM51 0 When receive mode Set P52 SI to the input mode PM52 1 Figure 15 2 Serial Operation Mode Register CSIM Format Address FF84H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 CSIM CSIE 0 ...

Page 186: ... O ports as well 1 Register settings Operation stop mode are set via serial operation mode register CSIM CSIM is set with a 1 bit or 8 bit memory manipulation instruction The RESET input resets the value to 00H Figure 15 3 Serial Operation Mode Register CSIM Format Address FF84H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 CSIM CSIE 0 0 0 0 MODE SCL1 SCL0 CSIE SIO3 Operation Enable Disable Specifica...

Page 187: ...s that set all output latches to 0 When serial clock output Master transmit or Master receive Set P50 SCK to the output mode PM50 0 When serial clock input Slave transmit or Slave receive Set P50 to the input mode PM50 1 When transmit transceive mode Set P51 SO to the output mode PM51 0 When receive mode Set P52 SI to the input mode PM52 1 Figure 15 4 Serial Operation Mode Register CSIM Format Add...

Page 188: ...I3 DI2 DI1 DI0 Serial transfer completion flag Serial clock 1 SO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 2 3 4 5 6 7 8 Transfer completion Transfer starts in synchronized with the serial clock s falling edge 3 Transfer start A serial transfer starts when the following two conditions have been satisfied and transfer data has been set to serial I O shift register SIO SIO3 operation control bit CSIE 1 After ...

Page 189: ...uencies can be selected in each display mode 4 Maximum of 20 segment signal outputs S0 to S19 4 common signal outputs COM0 to COM3 Fifteen of the segment signal outputs can be switched to input output ports in units of 2 P81 S19 to P87 S13 P90 S12 to P97 S5 The maximum number of displayable pixels is shown in Table 16 1 Table 16 1 Maximum Number of Display Pixels Bias Method Time Division Common S...

Page 190: ...ers LCD display mode register LCDM LCD display control register LCDC Figure 16 1 LCD Controller Driver Block Diagram Internal bus FA59H 7 6 5 4 3 2 1 0 FA67H 7 6 5 4 3 2 1 0 FA68H 7 6 5 4 3 2 1 0 FA6CH 7 6 5 4 3 2 1 0 Display data memory 3 2 1 0 selector 3 2 1 0 selector 3 2 1 0 selector 3 2 1 0 selector Note Note Note Note P97 output buffer S4 S0 S5 P97 P81 output buffer S19 P81 Segment selector ...

Page 191: ...DRIVER Figure 16 2 LCD Clock Select Circuit Block Diagram Prescaler fLCD 2 3 fX 2 14 fLCD 2 2 fLCD 2 fLCD Selector LCDM6 LCDM5 LCDM4 3 LCDCL LCD display mode register Internal bus Remarks 1 LCDCL LCD clock 2 fLCD LCD clock frequency ...

Page 192: ...ith a 1 bit or 8 bit memory manipulation instruction RESET input clears LCDM to 00H Figure 16 3 LCD Display Mode Register LCDM Format Address FFB0H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 LCDM LCDON LCDM6 LCDM5 LCDM4 0 0 0 0 LCDON LCD Display Enable Disable 0 Display off all segment outputs are non select signal outputs 1 Display on LCDM6 LCDM5 LCDM4 LCD Clock Selection fX 8 38 MHz 0 0 0 fX 217...

Page 193: ...C4 0 0 0 LIPS LCDC7 LCDC6 LCDC5 LCDC4 P81 S19 to P97 S5 Pin Functions Port Pins Segment Pins 0 0 0 0 P81 to P97 None 0 0 0 1 P81 to P95 S5 to S6 0 0 1 0 P81 to P93 S5 to S8 0 0 1 1 P81 to P91 S5 to S10 0 1 0 0 P81 to P87 S5 to S12 0 1 0 1 P81 to P85 S5 to S14 0 1 1 0 P81 to P83 S5 to S16 0 1 1 1 P81 S5 to S18 1 0 0 0 None S5 to S19 Other than above Setting prohibited LIPS LCD Driving Power Supply ...

Page 194: ...be performed as shown below 1 Set the initial value in the display data memory FA59H to FA6CH 2 Set the pins to be used as segment outputs in the LCD display control register LCDC 3 Set the LCD clock in the LCD display mode register LCDM Next set data in the display data memory according to the display contents ...

Page 195: ...ship between the LCD display data memory contents and the segment outputs common outputs Any area not used for display can be used as normal RAM Figure 16 5 Relationship between LCD Display Data Memory Contents and Segment Common Outputs S0 FA6CH S1 FA6BH S2 FA6AH S3 FA69H S17 P83 FA5BH S18 P82 FA5AH S19 P81 FA59H COM3 COM2 COM1 COM0 b7 b6 b5 b4 b3 b2 b1 b0 Address Caution The higher 4 bits of the...

Page 196: ...ectively and if the value of the bit is 1 it is converted to the selection voltage If the value of the bit is 0 it is converted to the non selection voltage and output to a segment pin S0 to S19 S18 to S5 have an alternate function as input output port pins Consequently it is necessary to check what combination of front surface electrodes corresponding to the segment signals and rear surface elect...

Page 197: ...signal voltages and phases Figure 16 6 Common Signal Waveform TF 4 x T COMn Divided by 4 VLC0 VSS VLCD VLC1 VLC2 T One LCDCL cycle TF Frame frequency Figure 16 7 Common Signal and Segment Signal Voltages and Phases Selected Not selected Common signal Segment signal VLC0 VSS VLCD VLC0 VSS VLCD T T VLC2 VLC2 VLC1 VLC1 T One LCDCL cycle ...

Page 198: ... To supply various LCD drive voltages internal VDD or external VLCD supply voltage can be selected Table 16 5 LCD Drive Voltage Bias Method 1 3 Bias Method LCD Drive Voltage VLC0 VLCD VLC1 2 3 VLCD VLC2 1 3 VLCD Figure 16 8 shows an example of supplying an LCD drive voltage from an internal source according to Table 16 5 By using variable resistors r1 and r2 a non stepwise LCD drive voltage can be...

Page 199: ...ive Power Supply a To supply LCD drive voltage from VDD VDD VSS VLCD VDD P ch LIPS 1 R R R VSS VLC2 VLC1 VLC0 VLCD Open VLCD pin b To supply LCD drive voltage from external source VDD VLCD VDD r1 r2 VSS VSS VLCD VDD P ch LIPS 0 R R R VSS VLC2 VLC1 VLC0 VLCD 3R r2 3R r2 3R r1 r1 r2 ...

Page 200: ... pins S8 and S9 as shown in Table 16 6 at the COM0 to COM3 common signal timings Table 16 6 Selection and Non Selection Voltages COM0 to COM3 Segment S8 S9 Common COM0 S S COM1 NS S COM2 S S COM3 NS S S Selection NS Non selection From this it can be seen that 0101 must be prepared in the display data memory address FA64H corresponding to S8 Examples of the LCD drive waveforms between S8 and the CO...

Page 201: ...BIT0 BIT1 BIT2 BIT3 S0 S1 S2 S3 1 1 0 FA6CH 1 1 1 B 1 1 0 A 1 0 0 9 S4 S5 S6 S7 1 1 0 8 1 1 1 7 1 1 0 6 1 0 0 5 S8 S9 S10 S11 1 1 0 4 1 1 1 3 1 1 0 2 1 0 1 1 S12 S13 S14 S15 0 1 0 0 1 0 0 FA5FH 1 1 0 E 0 0 1 D S16 S17 S18 S19 1 0 0 C 0 1 1 B 0 1 0 A 0 0 0 FA59H Data memory address LCD panel 1 0 1 1 1 1 1 0 0 1 0 1 1 1 1 1 1 1 1 0 ...

Page 202: ...ime Division LCD Drive Waveform Examples 1 3 Bias Method TF VLC0 VLC2 COM0 VLCD 0 COM0 to S8 VLCD VLC1 1 3VLCD 1 3VLCD VSS VLC0 VLC2 COM1 VLC1 VSS VLC0 VLC2 COM2 VLC1 VSS VLC0 VLC2 COM3 VLC1 VSS VLCD 0 COM1 to S8 VLCD 1 3VLCD 1 3VLCD VLC0 VLC2 S8 VLC1 VSS ...

Page 203: ...ntroller driver Figure 16 12 LCD Timer Control Register LCDTM Format Address FF4AH After Reset 00H W Symbol 7 6 5 4 3 2 1 0 LCDTM 0 0 0 0 0 0 TMC21 0 TMC21 LCD Clock Supply Control 0 LCD controller driver stop mode supply of LCD clock is stopped 1 LCD controller driver operating mode supply of LCD clock is enabled Cautions 1 LCDTM is a special register that must be set when debugging is performed ...

Page 204: ...204 MEMO ...

Page 205: ...al to enable control of the buzzer sound volume 2 Amplitude output signal A PWM signal with a 7 bit resolution for variable amplitude can be independently output Figure 17 1 shows the sound generator block diagram and Figure 17 2 shows the concept of each signal Figure 17 1 Sound Generator Block Diagram Internal bus Internal bus Sound generator control register SGCR TCE SGOB SGCL2 SGCL1 SGCL0 2 4 ...

Page 206: ...ator Configuration The sound generator consists of the following hardware Table 17 1 Sound Generator Configuration Item Configuration Counter 8 bits 1 5 bits 1 SG output SGO SGOF with without append bit of basic cycle output SGOA amplitude output Control register Sound generator control register SGCR Sound generator buzzer control register SGBR Sound generator amplitude register SGAM ...

Page 207: ... SGBR Sound generator amplitude register SGAM 1 Sound generator control register SGCR SGCR is a register which sets up the following four types Controls sound generator output Selects output of sound generator Selects sound generator input frequency fSG1 Selects 5 bit counter input frequency fSG2 SGCR is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears SGCR to 00H Figur...

Page 208: ...etting the TCE bit set all the other bits Remark SGOF Basic cycle signal without amplitude SGO Basic cycle signal with amplitude SGOA Amplitude signal SGOB Sound Generator Output Selection 0 Selects SGOF and SGOA outputs 1 Selects SGO and PCL outputs SGCL2 SGCL1 5 Bit Counter Input Frequency fSG2 Selection 0 0 fSG2 fSG1 25 0 1 fSG2 fSG1 26 1 0 fSG2 fSG1 27 1 1 fSG2 fSG1 28 SGCL0 Sound Generator In...

Page 209: ...0 460 0 244 0 481 0 256 1 1 1 fSG1 28 0 919 0 488 0 963 0 512 The sound generator output frequency fSG can be calculated by the following expression fSG 2 SGCL0 SGCL1 2 SGCL2 7 fX SGBR 17 Substitute set 0 or 1 to SGCL0 to SGCL2 in the above expression Substitute a decimal value to SGBR Where fX 8 MHz SGCL0 to SGCL2 is 1 0 0 and SGBR0 to SGBR3 is 1 1 1 1 SGBR 15 Therefore fSG 2 1 0 2 0 7 fX 15 17 3...

Page 210: ... 1 1 2 604 2 728 1 0 0 0 2 500 2 619 1 0 0 1 2 404 2 518 1 0 1 0 2 315 2 425 1 0 1 1 2 232 2 339 1 1 0 0 2 155 2 258 1 1 0 1 2 083 2 182 1 1 1 0 2 016 2 112 1 1 1 1 1 953 2 046 Note Output frequency where SGCL0 SGCL1 and SGCL2 are 0 0 and 0 Cautions 1 When rewriting SGBR to other data stop the timer operation TCE 0 beforehand 2 Bits 4 to 7 must be set to 0 3 Sound generator amplitude register SGAM...

Page 211: ... 0 1 0 11 128 0 0 0 1 0 1 1 12 128 0 0 0 1 1 0 0 13 128 0 0 0 1 1 0 1 14 128 0 0 0 1 1 1 0 15 128 0 0 0 1 1 1 1 16 128 0 0 1 0 0 0 0 17 128 0 0 1 0 0 0 1 18 128 0 0 1 0 0 1 0 19 128 0 0 1 0 0 1 1 20 128 0 0 1 0 1 0 0 21 128 0 0 1 0 1 0 1 22 128 0 0 1 0 1 1 0 23 128 0 0 1 0 1 1 1 24 128 0 0 1 1 0 0 0 25 128 0 0 1 1 0 0 1 26 128 0 0 1 1 0 1 0 27 128 0 0 1 1 0 1 1 28 128 0 0 1 1 1 0 0 29 128 0 0 1 1 ...

Page 212: ...to SGAM6 is output from the SGOA pin Figure 17 6 Sound Generator Output Operation Timing Timer Comparator 1 coincidence SGOF SGOA n n n n n n 17 4 2 To output basic cycle signal SGO with amplitude Select SGO output by setting bit 3 SGOB of the sound generator control register SGCR to 1 The basic cycle signal with a frequency specified by the SGCL0 to SGCL2 and SGBR0 to SGBR3 is output When SGO out...

Page 213: ...ram of the meter controller driver Figure 18 2 shows 1 bit addition circuit block diagram Figure 18 1 Meter Controller Driver Block Diagram Remark n 1 to 4 Internal bus Compare register MCMPn0 8 bit timer register fCC Selector 1 bit addition circuit fX fX 2 PCS PCE Compare register MCMPn1 1 bit addition circuit Internal bus MODn ENn Port mode control register PMC Timer mode control register MCNTC ...

Page 214: ...circuit 1 bit addition circuit output control circuit Remark n 1 to 4 1 Free running up counter MCNT MCNT is an 8 bit free running up counter and is a register that executes increment at the rising edge of input clock A PWM pulse with a resolution of 8 bits can be output The duty factor can be set in a range of 0 to 100 The count value is cleared in the following cases When RESET signal input When...

Page 215: ...4 1 bit addition circuit The 1 bit addition circuit repeats 1 bit addition non addition to PWM output alternately upon MCNT overflow output and enables the state of PWM output between current compare value and the next compare value This circuit is controlled by bits 2 and 3 ADBn0 ADBn1 of the MCMPCn register 5 Output control circuit This circuit consists of a Pch and Nch drivers and can drive a m...

Page 216: ...ion of the free running up counter MCNT MCNTC is set with an 8 bit memory manipulation instruction RESET input clears MCNTC to 00H Figure 18 3 shows the MCNTC format Figure 18 3 Timer Mode Control Register MCNTC Format Address FF69H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 MCNTC 0 0 PCS PCE 0 0 0 0 PCS Timer Counter Clock Selection 0 fX 1 fX 2 PCE Timer Operation Control 0 Operation stopped time...

Page 217: ...New data cannot be written ADBn1 Control of 1 bit addition circuit cos side of meter n 0 No 1 bit addition to PWM output 1 1 bit addition to PWM output ADBn0 Control of 1 bit addition circuit sin side of meter n 0 No 1 bit addition to PWM output 1 1 bit addition to PWM output Note TENn functions as a control bit and status flag As soon as the timer overflows and PWM data is output TENn is cleared ...

Page 218: ...er 2 Full Half Bridge Selection 0 Meter 2 output is full bridge 1 Meter 2 output is half bridge MOD1 Meter 1 Full Half Bridge Selection 0 Meter 1 output is full bridge 1 Meter 1 output is half bridge EN4 Meter 4 Port PWM Mode Selection 0 Meter 4 output is in port mode 1 Meter 4 output is in PWM mode EN3 Meter 3 Port PWM Mode Selection 0 Meter 3 output is in port mode 1 Meter 3 output is in PWM mod...

Page 219: ...T PWM PORT PWM 1 1 1 1 PORT PWM PWM PORT DIRn1 and DIRn0 mean the quadrant of sin and cos and DIRn1 DIRn0 00 through 11 correspond to quadrants 1 through 4 respectively The PWM signal is output to the specific pin of the and polarities of sin and cos of each quadrant When ENn 0 all the output pins are used as port pins regardless of MODn DIRn1 and DIRn0 When ENn 1 and MODn 0 the full bridge mode i...

Page 220: ...TC Figure 18 6 shows the timing from count start to restart Figure 18 6 Restart Timing after Count Stop Count Start Count Stop Count Start Remark N 00H to FFH 18 4 2 To update PWM data Confirm that bit 4 TENn of MCMPCn is 0 and then set 8 bit PWM data to MCMPn1 and MCMPn0 and bits 2 and 3 ADBn1 and ADBn0 of MCMPCn and at the same time set TENn to 1 The data will be automatically transferred to the...

Page 221: ...of PWM output between current compare value N and the next compare value N 1 In this mode 1 bit addition to the PWM output is set by setting ADBn of the MCMPCn register to 1 and 1 bit non addition normal output is set by setting ADBn to 0 Remark n 1 to 4 MCNT Value OVF Overflow Match signal of expected value N PWM output of expected value N 1 bit non addition PWM output of expected value N 1 bit a...

Page 222: ...eter 1 cos SM13 SM14 Meter 2 sin SM21 SM22 Meter 2 cos SM23 SM24 Meter 3 sin SM31 SM32 Meter 3 cos SM33 SM34 Meter 4 sin SM41 SM42 Meter 4 cos SM43 SM44 If the wave of sin and cos of meters 1 to 4 rises and falls internally as indicated by the broken line the SM11 to SM44 pins always shift the count clock by 1 clock and output signals in order to prevent VDD GND from fluctuating ...

Page 223: ... priority group by setting the priority specify flag registers PR0L PR0H PR1L Multiple high priority interrupts can be applied to low priority interrupts If two or more interrupts with the same priority are simultaneously generated each interrupt has a predetermined priority see Table 19 1 A standby release signal is generated Three external interrupt requests and sixteen internal interrupt reques...

Page 224: ...ransfer Internal 0016H B 10 INTSER Generation of serial interface UART receive error 0018H 11 INTSR End of serial interface UART reception 001AH 12 INTST End of serial interface UART transmission 001CH 13 INTTM1 Generation of 8 bit timer register and capture 001EH register CR1 match signal 14 INTTM2 Generation of 8 bit timer register and capture 0020H register CR2 match signal 15 INTTM3 Generation...

Page 225: ...ternal bus Interrupt request Priority control circuit Vector table address generator Standby release signal Internal bus Interrupt request IF MK IE PR ISP Priority control circuit Vector table address generator Standby release signal Internal bus Interrupt request IF MK IE PR ISP Priority control circuit Vector table address generator Standby release signal Sampling clock Edge detector Prescaler m...

Page 226: ...errupt request Priority control circuit Vector table address generator Standby release signal External interrupt edge enable register EGP EGN Edge detector E Software interrupt Internal bus Interrupt request Priority control circuit Vector table address generator IF Interrupt request flag IE Interrupt enable flag ISP In service priority flag MK Interrupt mask flag PR Priority specify flag ...

Page 227: ...s Table 19 2 Flags Corresponding to Interrupt Request Sources Interrupt Source Interrupt Request Flag Interrupt Mask Flag Priority Specify Flag Register Register Register INTWDT WDTIF IF0L WDTMK MK0L WDTPR PR0L INTAD ADIF ADMK ADPR INTOVF OVFIF OVFMK OVFPR INTTM00 TMIF00 TMMK00 TMPR00 INTTM01 TMIF01 TMMK01 TMPR01 INTTM02 TMIF02 TMMK02 TMPR02 INTP0 PIF0 PMK0 PPR0 INTP1 PIF1 PMK1 PPR1 INTP2 PIF2 IF0...

Page 228: ... RESET input sets these registers to 00H Figure 19 2 Interrupt Request Flag Register IF0L IF0H IF1L Format Address FFE0H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 IF0L PIF1 PIF0 TMIF02 TMIF01 TMIF00 OVFIF ADIF WDTIF Address FFE1H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 IF0H TMIF3 TMIF2 TMIF1 STIF SRIF SERIF CSIIF PIF2 Address FFE2H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 IF1L 0 0 0 0 0 WTIF...

Page 229: ...MMK01 TMMK00 OVFMK ADMK WDTMK Address FFE5H After Reset FFH R W Symbol 7 6 5 4 3 2 1 0 MK0H TMMK3 TMMK2 TMMK1 STMK SRMK SERMK CSIMK PMK2 Address FFE6H After Reset FFH R W Symbol 7 6 5 4 3 2 1 0 MK1L 1 1 1 1 1 WTMK WTIMK WEMK XXMKX Interrupt Servicing Control 0 Interrupt servicing enabled 1 Interrupt servicing disabled Cautions 1 If the watchdog timer is used in watchdog timer mode 1 the contents o...

Page 230: ...s these registers to FFH Figure 19 4 Priority Specify Flag Register PR0L PR0H PR1L Format Address FFE8H After Reset FFH R W Symbol 7 6 5 4 3 2 1 0 PR0L PPR1 PPR0 TMPR02 TMPR01 TMPR00 OVFPR ADPR WDTPR Address FFE9H After Reset FFH R W Symbol 7 6 5 4 3 2 1 0 PR0H TMPR3 TMPR2 TMPR1 STPR SRPR SERPR CSIPR PPR2 Address FFEAH After Reset FFH R W Symbol 7 6 5 4 3 2 1 0 PR1L 1 1 1 1 1 WTPR WTIPR WEPR XXPRX...

Page 231: ... RESET input sets these registers to 00H Figure 19 5 External Interrupt Rising Edge Enable Register EGP External Interrupt Falling Edge Enable Register EGN Format Address FF48H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 EGP 0 0 0 0 0 EGP2 EGP1 EGP0 Address FF49H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 EGN 0 0 0 0 0 EGN2 EGN1 EGN0 EGPn EGNn INTPn Pin Valid Edge Selection n 0 to 2 0 0 Interrupt d...

Page 232: ... ES10 ES01 ES00 PRM01 PRM00 ES21 ES20 TI02 Valid Edge Selection 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges ES11 ES10 TI01 Valid Edge Selection 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges ES01 ES00 TI00 Valid Edge Selection 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling ...

Page 233: ...e IE flag is reset to 0 If a maskable interrupt request is acknowledged the contents of the priority specify flag of the acknowledged interrupt are transferred to the ISP flag The PSW contents are also saved into the stack with the PUSH PSW instruction They are reset from the stack with the RETI RETB and POP PSW instructions RESET input sets PSW to 02H Figure 19 7 Program Status Word Format 7 IE 6...

Page 234: ...upt request generated during execution of a non maskable interrupt servicing program is acknowledged after the current execution of the non maskable interrupt servicing program is terminated following RETI instruction execution and one main routine instruction is executed However if a new non maskable interrupt request is generated twice or more during non maskable interrupt servicing program exec...

Page 235: ...quest generation Start of interrupt servicing Interrupt request held pending No No No Yes Yes Yes Yes Yes WDTM Watchdog timer mode register WDT Watchdog timer WDTM3 0 with non maskable interrupt selected Figure 19 9 Non Maskable Interrupt Request Acknowledge Timing Instruction Instruction PSW and PC save jump to interrupt servicing Interrupt servicing program CPU processing WDTIF Interrupt request...

Page 236: ...NMI request 2 held pending Servicing of NMI request 2 that was pended b If two non maskable interrupt requests are generated during non maskable interrupt servicing program execution Main routine NMI request 1 Execution of 1 instruction Execution of NMI request 1 NMI request 2 held pending NMI request 3 held pending Servicing of NMI request 2 that was pended NMI request 3 not acknowledged Although...

Page 237: ... 33 clocks Note If an interrupt request is generated just before a divide instruction the wait time becomes longer Remark 1 clock 1 fCPU fCPU CPU clock If two or more maskable interrupt requests are generated simultaneously the request with a higher priority level specified in the priority specify flag is acknowledged first If two or more interrupts requests have the same priority level the reques...

Page 238: ...st held pending Interrupt request held pending Interrupt request held pending Interrupt request held pending Interrupt request held pending Vectored interrupt servicing Any interrupt request among those simultaneously generated Any interrupt request among those simultaneously generated with PR 0 IF Interrupt request flag MK Interrupt mask flag PR Priority specify flag IE Flag that controls acknowl...

Page 239: ... CPU processing IF PR 1 IF PR 0 6 clocks 25 clocks Remark 1 clock 1 fCPU fCPU CPU clock 19 4 3 Software interrupt request acknowledge operation A software interrupt acknowledge is acknowledged by BRK instruction execution Software interrupts cannot be disabled If a software interrupt request is acknowledged the contents are saved into the stacks in the order of the program status word PSW then pro...

Page 240: ...viced is generated during interrupt servicing it is not acknowledged for multiple interrupt servicing Interrupt requests that are not enabled because of the interrupt disable state or they have a lower priority are held pending When servicing of the current interrupt ends the pended interrupt request is acknowledged following execution of one main processing instruction execution Multiple interrup...

Page 241: ...ust always be issued to enable interrupt request acknowledge Example 2 Multiple interrupt servicing does not occur due to priority control Main processing INTxx servicing INTyy servicing INTxx PR 0 INTyy PR 1 EI RETI IE 0 IE 0 EI 1 instruction execution RETI Interrupt request INTyy issued during servicing of interrupt INTxx is not acknowledged because its priority is lower than that of INTxx and m...

Page 242: ...ecution RETI RETI INTxx PR 0 INTyy PR 0 IE 0 IE 0 Interrupt is not enabled during servicing of interrupt INTxx EI instruction is not issued therefore interrupt request INTyy is not acknowledged and multiple interrupt servicing does not take place The INTyy interrupt request is held pending and is acknowledged following execution of one main processing instruction PR 0 Higher priority level IE 0 In...

Page 243: ...gisters Caution The BRK instruction is not one of the above listed interrupt request hold instruction However the software interrupt activated by executing the BRK instruction causes the IE flag to be cleared Therefore even if a maskable interrupt request is generated during execution of the BRK instruction the interrupt request is not acknowledged However a non maskable interrupt request is ackno...

Page 244: ...244 MEMO ...

Page 245: ...2 0 V is possible Thus the STOP mode is effective to hold data memory contents with ultra low current consumption Because this mode can be cleared upon interrupt request it enables intermittent operations to be carried out However because a wait time is required to secure an oscillation stabilization time after the STOP mode is cleared select the HALT mode if it is necessary to start processing im...

Page 246: ... 0 OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0 OSTS2 OSTS1 OSTS0 Selection of Oscillation Stabilization Time 0 0 0 212 fX 488 µs 0 0 1 214 fX 1 95 ms 0 1 0 215 fX 3 91 ms 0 1 1 216 fX 7 81 ms 1 0 0 217 fX 15 6 ms Other than above Setting prohibited Caution The wait time after the STOP mode is cleared does not include the time see a in the illustration below from STOP mode clear to clock oscillation start reg...

Page 247: ...de Operating Status HALT Mode Setting During HALT Instruction Execution Using Main System Clock Item Clock generator Main system clock can be oscillated Clock supply to CPU stops CPU Operation stops Port Output latch Status before HALT mode setting is held 16 bit timer Operable 8 bit timer Watch timer Watchdog timer A D converter Operation stops Serial interface Operable LCD controller driver Exte...

Page 248: ...ALT Mode Clear upon Interrupt Generation HALT instruction Wait Wait Operating mode HALT mode Operating mode Oscillation Clock Standby release signal Remarks 1 The broken line indicates the case when the interrupt request which has cleared the standby mode is acknowledged 2 Wait times are as follows When vectored interrupt service is carried out 8 to 9 clocks When vectored interrupt service is not ...

Page 249: ...k RESET signal Oscillation Oscillation Reset period Remarks 1 fX Main system clock oscillation frequency 2 Values in parentheses apply to operation with fX 8 38 MHz Table 20 2 Operation after HALT Mode Clear Clear Source MK PR IE ISP Operation Maskable interrupt request 0 0 0 Next address instruction execution 0 0 1 Interrupt service execution 0 1 0 1 Next address instruction execution 0 1 0 0 1 1...

Page 250: ... STOP instruction After the wait set using the oscillation stabilization time select register OSTS the operating mode is set The operating status in the STOP mode is described below Table 20 3 STOP Mode Operating Status STOP Mode Setting During STOP Instruction Execution Using Main System Clock Item Clock generator Only main system clock oscillation is stopped CPU Operation stops Port Output latch...

Page 251: ...lization time vectored interrupt service is carried out If interrupt acknowledge is disabled the next address instruction is executed Figure 20 4 STOP Mode Clear upon Interrupt Generation STOP instruction Wait Time set by OSTS Oscillation stabilization wait status Operating mode STOP mode Operating mode Oscillation Clock Standby release signal Oscillation stop Oscillation Remark The broken line in...

Page 252: ...ting mode Oscillation stop Clock RESET signal Oscillation Oscillation Reset period Remarks 1 fX Main system clock oscillation frequency 2 Values in parentheses apply to operation with fX 8 38 MHz Table 20 4 Operation after STOP Mode Clear Clear Source MK PR IE ISP Operation Maskable interrupt request 0 0 0 Next address instruction execution 0 0 1 Interrupt service execution 0 1 0 1 Next address in...

Page 253: ...et clear When a high level is input to the RESET pin the reset is cleared and program execution starts after the lapse of oscillation stabilization time 217 fX The reset applied by watchdog timer overflow is automatically cleared after a reset and program execution starts after the lapse of oscillation stabilization time 217 fX see Figures 21 2 to 21 4 Cautions 1 For an external reset input a low ...

Page 254: ...chdog Timer Overflow Hi Z Normal operation Reset period Oscillation stop Oscillation stabilization time wait Normal operation Reset processing X1 Watchdog timer overflow Internal reset signal Port pin Figure 21 4 Timing of Reset in STOP Mode by RESET Input Delay Delay Hi Z Normal operation Oscillation stabilization time wait Normal operation Reset processing X1 RESET Internal reset signal Port pin...

Page 255: ...ssor clock control register PCC 04H Memory size switching register IMS CFH Oscillation stabilization time select register OSTS 04H Oscillator mode register OSCM Note 3 00H 16 bit timer TM0 Timer register TM0 00H Capture registers CR00 to CR02 00H Prescaler mode register PRM0 00H Mode control register TMC0 00H Capture pulse control register CRC0 00H Notes 1 During reset input or oscillation stabili...

Page 256: ... status register ASIS 00H Baud rate generator control register BRGC 00H Transmit shift register TXS FFH Receive buffer register RXB Serial interface SIO3 Shift register SIO 00H Mode register CSIM 00H LCD controller driver Display mode register LCDM 00H Display control register LCDC 00H EEPROM Write control register EEWC 00H Sound generator Control register SGCR 00H Buzzer control register SGBR 00H...

Page 257: ...ory size switching register IC pin None Available VPP pin Available None Electrical specifications See data sheet of each product Quality grade Standard Special Note Although the initial value is CFH set the following values IMS Setting Value Flash Memory Internal Remarks High speed RAM 06H 24 Kbytes 768 bytes When using the same memory map as that of µPD780973 A C8H 32 Kbytes 1024 bytes When usin...

Page 258: ... Switching Register IMS Format Address FFF0H After Reset CFH R W Symbol 7 6 5 4 3 2 1 0 IMS RAM2 RAM1 RAM0 0 ROM3 ROM2 ROM1 ROM0 RAM2 RAM1 RAM0 Internal High Speed RAM Capacity Selection 0 0 0 768 bytes 1 1 0 1024 bytes Other than above Setting prohibited ROM3 ROM2 ROM1 ROM0 Internal ROM Capacity Selection 0 1 1 0 24 Kbytes 1 0 0 0 32 Kbytes Other than above Setting prohibited The IMS settings to ...

Page 259: ...ion method a format like the one shown in Figure 22 2 is used The transmission methods are selected with the VPP pulse numbers shown in Table 22 3 Table 22 3 Transmission Method List Transmission Method Number of Channels Pin Used Number of VPP Pulses 3 wire serial I O 1 SI P52 0 SO P51 SCK P50 UART 1 RxD P53 8 TxD P54 Pseudo 3 wire serial I O 2 P05 serial clock input 12 P06 serial data output P07...

Page 260: ...ata bytes Continuous write Performs successive write operations using the data input with high speed write operation Status Checks the current operation mode and operation end Oscillation frequency setting Inputs the resonator oscillation frequency information Delete time setting Inputs the memory delete time Baud rate setting Sets the transmission rate when the UART method is used Silicon signatu...

Page 261: ...2 5 Flashpro II Connection Using Pseudo 3 Wire Serial I O Method VPP VDD RESET SCK SO SI GND VPP VDD RESET P05 P95 Serial clock input P07 P97 Serial data input P06 P96 Serial data output VSS Flashpro II PD78F0974 µ VPP VDD RESET SO SI GND VPP VDD RESET RxD TxD VSS Flashpro II PD78F0974 µ ...

Page 262: ...262 MEMO ...

Page 263: ...UCTION SET This chapter lists the instruction set of the µPD780973 Subseries For details of the operation and machine language instruction code refer to the separate document 78K 0 Series User s Manual Instructions U12326E ...

Page 264: ...es names in parentheses in the table below R0 R1 R2 etc can be used for description Table 23 1 Operand Identifiers and Description Formats Identifier Description Format r X R0 A R1 C R2 B R3 E R4 D R5 L R6 H R7 rp AX RP0 BC RP1 DE RP2 HL RP3 sfr Special function register symbol Note sfrp Special function register symbol 16 bit manipulatable register even addresses only Note saddr FE20H to FF1FH Im...

Page 265: ...rry flag Z Zero flag RBS Register bank select flag IE Interrupt request enable flag NMIS Non maskable interrupt servicing flag Memory contents indicated by address or register contents in parentheses H L Higher 8 bits and lower 8 bits of 16 bit register Logical product AND Logical sum OR Exclusive logical sum exclusive OR Inverted data addr16 16 bit immediate data or label jdisp8 Signed 8 bit data...

Page 266: ... byte A 2 8 9 HL byte A A HL B 1 6 7 A HL B HL B A 1 6 7 HL B A A HL C 1 6 7 A HL C HL C A 1 6 7 HL C A A r Note 3 1 2 A r A saddr 2 4 6 A saddr A sfr 2 6 A sfr A addr16 3 8 10 A addr16 XCH A DE 1 4 6 A DE A HL 1 4 6 A HL A HL byte 2 8 10 A HL byte A HL B 2 8 10 A HL B A HL C 2 8 10 A HL C Notes 1 When the internal high speed RAM area is accessed or instruction with no data access 2 When an area e...

Page 267: ...A HL byte A HL B 2 8 9 A CY A HL B A HL C 2 8 9 A CY A HL C A byte 2 4 A CY A byte CY saddr byte 3 6 8 saddr CY saddr byte CY A r Note 4 2 4 A CY A r CY r A 2 4 r CY r A CY A saddr 2 4 5 A CY A saddr CY A addr16 3 8 9 A CY A addr16 CY A HL 1 4 5 A CY A HL CY A HL byte 2 8 9 A CY A HL byte CY A HL B 2 8 9 A CY A HL B CY A HL C 2 8 9 A CY A HL C CY Notes 1 When the internal high speed RAM area is ac...

Page 268: ...5 A CY A HL CY A HL byte 2 8 9 A CY A HL byte CY A HL B 2 8 9 A CY A HL B CY A HL C 2 8 9 A CY A HL C CY A byte 2 4 A A byte saddr byte 3 6 8 saddr saddr byte A r Note 3 2 4 A A r r A 2 4 r r A A saddr 2 4 5 A A saddr A addr16 3 8 9 A A addr16 A HL 1 4 5 A A HL A HL byte 2 8 9 A A HL byte A HL B 2 8 9 A A HL B A HL C 2 8 9 A A HL C Notes 1 When the internal high speed RAM area is accessed or instr...

Page 269: ... A HL byte 2 8 9 A A HL byte A HL B 2 8 9 A A HL B A HL C 2 8 9 A A HL C A byte 2 4 A byte saddr byte 3 6 8 saddr byte A r Note 3 2 4 A r r A 2 4 r A A saddr 2 4 5 A saddr A addr16 3 8 9 A addr16 A HL 1 4 5 A HL A HL byte 2 8 9 A HL byte A HL B 2 8 9 A HL B A HL C 2 8 9 A HL C Notes 1 When the internal high speed RAM area is accessed or instruction with no data access 2 When an area except the int...

Page 270: ...ion Decimal Adjust Accumulator after Subtract CY saddr bit 3 6 7 CY saddr bit CY sfr bit 3 7 CY sfr bit CY A bit 2 4 CY A bit CY PSW bit 3 7 CY PSW bit CY HL bit 2 6 7 CY HL bit saddr bit CY 3 6 8 saddr bit CY sfr bit CY 3 8 sfr bit CY A bit CY 2 4 A bit CY PSW bit CY 3 8 PSW bit CY HL bit CY 2 6 8 HL bit CY Notes 1 When the internal high speed RAM area is accessed or instruction with no data acce...

Page 271: ... CY PSW bit CY HL bit 2 6 7 CY CY HL bit saddr bit 2 4 6 saddr bit 1 sfr bit 3 8 sfr bit 1 SET1 A bit 2 4 A bit 1 PSW bit 2 6 PSW bit 1 HL bit 2 6 8 HL bit 1 saddr bit 2 4 6 saddr bit 0 sfr bit 3 8 sfr bit 0 CLR1 A bit 2 4 A bit 0 PSW bit 2 6 PSW bit 0 HL bit 2 6 8 HL bit 0 SET1 CY 1 2 CY 1 1 CLR1 CY 1 2 CY 0 0 NOT1 CY 1 2 CY CY Notes 1 When the internal high speed RAM area is accessed or instruct...

Page 272: ... 2 PCH SP 1 PCL SP RETI 1 6 PSW SP 2 SP SP 3 R R R NMIS 0 PCH SP 1 PCL SP PSW SP 2 SP SP 3 PSW 1 2 SP 1 PSW SP SP 1 SP 1 rpH SP 2 rpL SP SP 2 PSW 1 2 PSW SP SP SP 1 R R R rpH SP 1 rpL SP SP SP 2 SP word 4 10 SP word MOVW SP AX 2 8 SP AX AX SP 2 8 AX SP addr16 3 6 PC addr16 BR addr16 2 6 PC PC 2 jdisp8 AX 2 8 PCH A PCL X BC addr16 2 6 PC PC 2 jdisp8 if CY 1 BNC addr16 2 6 PC PC 2 jdisp8 if CY 0 BZ ...

Page 273: ... PC 3 jdisp8 if A bit 1 then reset A bit PC PC 4 jdisp8 if PSW bit 1 then reset PSW bit PC PC 3 jdisp8 if HL bit 1 then reset HL bit B B 1 then PC PC 2 jdisp8 if B 0 C C 1 then PC PC 2 jdisp8 if C 0 saddr saddr 1 then PC PC 3 jdisp8 if saddr 0 SEL RBn 2 4 RBS1 0 n NOP 1 2 No Operation EI 2 6 IE 1 Enable Interrupt DI 2 6 IE 0 Disable Interrupt HALT 2 6 Set HALT Mode STOP 2 6 Set STOP Mode Notes 1 W...

Page 274: ...274 CHAPTER 23 INSTRUCTION SET 23 3 Instructions Listed by Addressing Type 1 8 bit instructions MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MULU DIVUW INC DEC ROR ROL RORC ROLC ROR4 ROL4 PUSH POP DBNZ ...

Page 275: ...DD ADD ADD RORC SUBC ADDC ADDC ADDC ADDC ADDC ROLC AND SUB SUB SUB SUB SUB OR SUBC SUBC SUBC SUBC SUBC XOR AND AND AND AND AND CMP OR OR OR OR OR XOR XOR XOR XOR XOR CMP CMP CMP CMP CMP r MOV MOV INC ADD DEC ADDC SUB SUBC AND OR XOR CMP B C DBNZ sfr MOV MOV saddr MOV MOV DBNZ INC ADD DEC ADDC SUB SUBC AND OR XOR CMP addr16 MOV PSW MOV MOV PUSH POP DE MOV HL MOV ROR4 ROL4 HL byte MOV HL B HL C X MU...

Page 276: ...L 3 Bit manipulation instructions MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 BT BF BTCLR Second Operand First Operand A bit MOV1 BT SET1 BF CLR1 BTCLR sfr bit MOV1 BT SET1 BF CLR1 BTCLR saddr bit MOV1 BT SET1 BF CLR1 BTCLR PSW bit MOV1 BT SET1 BF CLR1 BTCLR HL bit MOV1 BT SET1 BF CLR1 BTCLR CY MOV1 MOV1 MOV1 MOV1 MOV1 SET1 AND1 AND1 AND1 AND1 AND1 CLR1 OR1 OR1 OR1 OR1 OR1 NOT1 XOR1 XOR1 XOR1 XOR1 XOR1 word...

Page 277: ...branch instructions CALL CALLF CALLT BR BC BNC BZ BNZ BT BF BTCLR DBNZ Second Operand First Operand Basic instruction BR CALL CALLF CALLT BR BR BC BNC BZ BNZ Compound BT instruction BF BTCLR DBNZ 5 Other instructions ADJBA ADJBS BRK RET RETI RETB SEL NOP EI DI HALT STOP ...

Page 278: ...278 MEMO ...

Page 279: ...279 APPENDIX A DEVELOPMENT TOOLS The following development tools are available for the development of systems that employ the µPD780973 Subseries Figure A 1 shows the development tool configuration ...

Page 280: ...are Real time OS OS Debugging Tools Assembler package C compiler package C library source file Device file Language Processing Software On chip flash memory version In circuit emulator Power unit Emulation probe Conversion socket or conversion adapter Target system Host Machine PC Interface adapter PC card interface etc Emulation board Flash programmer Flash memory writing environment ...

Page 281: ...or Integrated debugger Device file Embedded Software Real time OS OS Debugging Tools Assembler package C compiler package C library source file Device file Language Processing Software In circuit emulator Emulation probe Conversion socket or conversion adapter Target system Host Machine PC or EWS Interface board Interface adapter CPU core board I O board Probe board On chip flash memory version Fl...

Page 282: ...nverts programs written in C language into an object code executable C Compiler Package with a microcontroller This compiler is used in combination with an optional assembler package RA78K 0 and device file DF780974 Caution when using in PC environment This C compiler package is a DOS based application however using Project Manager which is included in the assembler package enables use of this com...

Page 283: ...tes 1 2 3P16 HP9000 Series 700 HP UX Rel 9 05 DAT DDS 3K13 SPARCstation SunOS Rel 4 1 4 3 5 inch 2HC FD 3K15 1 4 inch CGMT 3R13 NEWS RISC NEWS OS Rel 6 1 3 5 inch 2HC FD Notes 1 DOS is also supported 2 WindowsNT is not supported A 2 Flash Memory Writing Tools Flashpro II FL PR2 Flash Writer Remark Flashpro II is a product of Naitou Densei Machidaseisakusho Co Ltd Naitou Densei Machidaseisakusho Co...

Page 284: ...00 Series notebook as the PC Card Interface IE 78K0 NS host machine IE 70000 PC IF C Note This adapter is required when using an IBM PC AT or compatible as the IE 78K0 NS host Interface Adapter machine IE 780974 NS EM1 Note This board is used to emulate the peripheral hardware that is peculiar to the device This Emulation Board board is used in combination with an in circuit emulator EP 80GF NS Th...

Page 285: ...ith an emulation probe and an interface adapter for connection to a host machine This adapter is required when using the PC 9800 Series computer except notebook type as the IE 78001 R A host machine This adapter is required when using an IBM PC AT or compatible as the IE 78001 R A host machine This is an adapter and cable when an EWS is used as the host machine for the IE 78001 R A and is connecte...

Page 286: ...endent basis from hardware development without having to use an in circuit emulator thereby providing higher development efficiency and software quality The SM78K0 is used in combination with the optional device file DF780974 Part Number µS SM78K0 Remark in the part number differs depending on the host machine and OS used µS SM78K0 Host Machine OS Supply Medium AA13 PC 9800 Series Windows Japanese...

Page 287: ...9000 Series 700 HP UX Rel 9 05 DAT DDS 3K13 SPARCstation SunOS Rel 4 1 4 3 5 inch 2HC FD 3K15 1 4 inch CGMT 3R13 NEWS RISC NEWS OS Rel 6 1 3 5 inch 2HC FD Note WindowsNT is not supported This is a control program used to debug the 78K 0 Series The graphical user interfaces employed are Windows for personal computers and OSF MotifTM for EWSs offering the standard appearance and operability typical ...

Page 288: ...it emulator can be upgraded to be equivalent to the IE 78001 R A in circuit emulator by simply replacing the break board with the IE 78001 R BK under development Table A 1 Upgrading Former In circuit Emulator for 78K 0 Series to IE 78001 R A In circuit Emulator Cabinet Upgrading Note Board to be Purchased IE 78000 R Required IE 78001 R BK IE 78000 R A Not required Note To upgrade your cabinet brin...

Page 289: ... X Y T U V Z 0 8 0 8x23 18 4 0 031 0 031x0 906 0 724 G 21 2 0 835 Note Product of TOKYO ELETECH CORPORATION 1 325 0 052 19 75 0 778 23 55 0 927 27 05 1 065 10 6 0 417 17 1 0 673 1 125 0 044 14 40 0 567 18 8 0 740 20 65 0 813 9 5 0 374 1 8 0 071 3 55 0 140 5 3 0 209 5 0 0 197 0 9 0 035 0 3 0 012 q 3 5 0 138 r 2 0 0 079 0 25 0 010 s n 7 35 0 289 o 1 2 p 1 85 0 073 0 047 w t u v 7 7 16 95 0 303 0 667...

Page 290: ...290 MEMO ...

Page 291: ... in advance and sign the User Agreement Remark and in the part number differ depending on the host machine and OS used µS RX78013 Product Outline Upper Limit of Mass Production Quantity 001 Evaluation object Do not use for mass produced products 100K Object for mass produced product 0 1 million units 001M 1 million units 010M 10 million units S01 Source program Source program for mass produced obj...

Page 292: ...d OS used µS MX78K0 Product Outline Note 001 Evaluation object Use for trial product Object for mass produced product Use for mass produced product S01 Source program Can be purchased only when object for mass produced product is purchased Host Machine OS Supply Medium AA13 PC 9800 Series Windows Japanese version Notes 1 2 3 5 inch 2HD FD AB13 IBM PC AT and compatibles Windows Japanese version Not...

Page 293: ...are control register 1 MCMPC1 217 Compare control register 2 MCMPC2 217 Compare control register 3 MCMPC3 217 Compare control register 4 MCMPC4 217 Compare register 10 MCMP10 215 Compare register 11 MCMP11 215 Compare register 20 MCMP20 215 Compare register 21 MCMP21 215 Compare register 30 MCMP30 215 Compare register 31 MCMP31 215 Compare register 40 MCMP40 215 Compare register 41 MCMP41 215 D D ...

Page 294: ...ime select register OSTS 246 Oscillator mode register OSCM 91 P Port 0 P0 75 Port 1 P1 76 Port 2 P2 77 Port 3 P3 78 Port 4 P4 79 Port 5 P5 80 Port 6 P6 81 Port 8 P8 82 Port 9 P9 83 Port mode control register PMC 217 Port mode register 0 PM0 84 Port mode register 2 PM2 84 Port mode register 3 PM3 84 Port mode register 4 PM4 84 Port mode register 5 PM5 84 Port mode register 6 PM6 84 147 Port mode re...

Page 295: ...amplitude register SGAM 210 Sound generator buzzer control register SGBR 209 Sound generator control register SGCR 207 T Timer clock select register 1 TCL1 113 Timer clock select register 2 TCL2 122 Timer clock select register 3 TCL3 122 Timer mode control register MCNTC 216 Transmit shift register TXS 166 W Watch timer mode control register WTM 135 Watchdog timer clock select register WDCS 141 Wa...

Page 296: ...gister 2 121 CR3 8 bit compare register 3 121 CRC0 Capture pulse control register 104 CSIM Serial operation mode register 185 186 D DAM1 D A converter mode register 163 E EEWC EEPROM write control register 69 EGN External interrupt falling edge enable register 231 EGP External interrupt rising edge enable register 231 I IF0H Interrupt request flag register 0H 228 IF0L Interrupt request flag regist...

Page 297: ... 80 P6 Port 6 81 P8 Port 8 82 P9 Port 9 83 PCC Processor clock control register 90 PFM Power fail compare mode register 154 PFT Power fail compare threshold value register 154 PM0 Port mode register 0 84 PM2 Port mode register 2 84 PM3 Port mode register 3 84 PM4 Port mode register 4 84 PM5 Port mode register 5 84 PM6 Port mode register 6 84 147 PM8 Port mode register 8 84 PM9 Port mode register 9...

Page 298: ...bit timer register 102 TM1 8 bit counter 1 112 TM2 8 bit counter 2 121 TM3 8 bit counter 3 121 TMC0 16 bit timer mode control register 103 TMC1 8 bit timer mode control register 1 114 TMC2 8 bit timer mode control register 2 123 TMC3 8 bit timer mode control register 3 123 TXS Transmit shift register 166 W WDCS Watchdog timer clock select register 141 WDTM Watchdog timer mode register 142 WTM Watc...

Page 299: ... 9 P81 Block Diagram Correction of Figure 5 10 P82 to P87 Block Diagram 5 2 9 Port 9 Correction of description Correction of Figure 5 11 P90 to P97 Block Diagram Table 5 3 Port Mode Register and Output Latch Settings when Using Alternate Functions Change of P setting values of P20 to P27 and P30 to P37 from 0 to Change of Note 2 Addition of Note in Figure 5 13 Port Mode Register PM2 PM3 Format Add...

Page 300: ...perable Operation stops Addition of oscillator mode register to Table 21 1 Hardware Status CHAPTER 21 RESET FUNCTION after Reset Change of Note in Table 22 1 Differences between µPD78F0974 and CHAPTER 22 µPD78F0974 µPD780973 A Support of in circuit emulator IE 78K0 NS APPENDIX A DEVELOPMENT Change in supported OS TOOLS Addition of A 4 Upgrading Former In circuit Emulator for 78K 0 Series to IE 780...

Page 301: ...x 02 719 5951 Address North America NEC Electronics Inc Corporate Communications Dept Fax 1 800 729 9288 1 408 588 6130 Europe NEC Electronics Europe GmbH Technical Documentation Dept Fax 49 211 6503 274 South America NEC do Brasil S A Fax 55 11 6465 6829 Asian Nations except Philippines NEC Electronics Singapore Pte Ltd Fax 65 250 3583 Japan NEC Semiconductor Technical Hotline Fax 044 548 7900 I ...

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