NEC mPD780973 Series, Preliminary User'S Manual

Page: 176 / 301

176
CHAPTER 14 SERIAL INTERFACE UART
• Error tolerance range for baud rates
The tolerance range for baud rates depends on the number of bits per frame and the counter’s division
rate [1/(16 + k)].
Table 14-3 describes the relation between the main system clock and the baud rate and Figure 14-5 shows
an example of a baud rate error tolerance range.
Table 14-3. Relation between Main System Clock and Baud Rate
Baud rate
f
X
= 8.386 MHz
(bps)
BRGC Set Value Error (%)
600 7BH 1.10
1200 6BH 1.10
2400 5BH 1.10
4800 4BH 1.10
9600 3BH 1.10
19200 2BH –1.3
31250 21H 1.10
38400 1BH 1.10
76800 0BH 1.10
115200 01H 1.03
Remark f
X
: Main system clock oscillation frequency
Figure 14-5. Error Tolerance (when k = 0) including Sampling Errors
Basic timing
(clock cycle T)
START D0 D7 P
STOP
High-speed clock
(clock cycle T’)
enabling normal
reception
START D0 D7 P
STOP
Low-speed clock
(clock cycle T”)
enabling normal
reception
START D0 D7 P
STOP
32T 64T 256T 288T 320T 352T
Ideal
sampling
point
304T 336T
30.45T 60.9T 304.5T
15.5T
15.5T
0.5T
Sampling error
33.55T 67.1T 301.95T 335.5T
Remark T : 5-bit counter’s source clock cycle
Baud rate error tolerance (when k = 0) =
±
15.5
×
100 = 4.8438 (%)
320