NEC mPD780973 Series, Preliminary User'S Manual

Page: 95 / 301

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CHAPTER 6 CLOCK GENERATOR
6.5 Operation of Clock Generator
The clock generator generates the following clocks and controls the operation modes of the CPU, such as the
standby mode:
• Main system clock f
X
• CPU clock f
CPU
• Clock to peripheral hardware
The operation of the clock generator is determined by the processor clock control register (PCC) and oscillator
mode register (OSCM) as follows:
(a) The slowest mode (3.81
µ
s: at 8.38-MHz operation) of the main system clock is selected when the RESET
signal is generated (PCC = 04H). While a low level is input to the RESET pin, oscillation of the main system
clock is stopped.
(b) Five types of CPU clocks (0.24
µ
s, 0.48
µ
s, 0.95
µ
s, 1.91
µ
s, and 3.81
µ
s: at 8.38-MHz operation) can be
selected by the PCC setting.
(c) Two standby modes, STOP and HALT, can be used.
(d) The clock to the peripheral hardware is supplied by dividing the main system clock. The other peripheral
hardware is stopped when the main system clock is stopped (except, however, the external clock input
operation).
(e) The
µ
PD780973(A) can be set to the reduced current consumption mode by setting OSCM (only when operated
at f
X
= 4 to 4.19 MHz). Setting 1 to bit 7 (HALFOSC) of OSCM will reduce the power consumption.
Cautions 1. This function is available only when the device is operated at f
X
= 4 to 4.19 MHz. In other cases,
be sure not to set 1 to bit 7.
2. When using in normal operation mode, setting OSCM is not necessary.
3. Only the first setting of OSCM is effective.