NEC mPD780973 Series, Preliminary User'S Manual

Page: 150 / 301

150
CHAPTER 13 A/D CONVERTER
Figure 13-2. Power-Fail Detection Function Block Diagram
ANI0/P10
ANI1/P11
ANI2/P12
ANI3/P13
ANI4/P14
Multiplexer
Selector
A/D converter
Internal bus
Power-fail compare
mode register (PFM)
Comparator
PFEN PFCM
Power-fail compare
threshold value
register (PFT)
INTAD
PFEN PFCM
13.2 A/D Converter Configuration
A/D converter consists of the following hardware.
Table 13-1. A/D Converter Configuration
Item Configuration
Analog input 5 channels (ANI0 to ANI4)
Register Successive approximation register (SAR)
A/D conversion result register (ADCR1)
Control register A/D converter mode register (ADM1)
Analog input channel specification register (ADS1)
Power-fail compare mode register (PFM)
Power-fail compare threshold value register (PFT)
(1) Successive approximation register (SAR)
This register compares the analog input voltage value to the voltage tap (compare voltage) value applied from
the series resistor string, and holds the result from the most significant bit (MSB).
When up to the least significant bit (LSB) is set (end of A/D conversion), the SAR contents are transferred to
the A/D conversion result register.
(2) A/D conversion result register (ADCR1)
This register holds the A/D conversion result. Each time A/D conversion ends, the conversion result is loaded
from the successive approximation register.
ADCR1 is read with an 8-bit memory manipulation instruction.
RESET input clears ADCR1 to 00H.
Caution When write operation is executed to A/D converter mode register (ADM1) and analog input
channel specification register (ADS1), the contents of ADCR1 are undefined. Read the
conversion result before write operation is executed to ADM1, ADS1. If a timing other than
the above is used, the correct conversion result may not be read.