NEC 78K0/KD1 Series User Manual Download

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CHAPTER 13 SERIAL INTERFACE UART0

Preliminary User’s Manual U16315EJ1V0UD

266

(4) Permissible baud rate range during reception

The permissible error from the baud rate at the transmission destination during reception is shown below.

Caution

Make sure that the baud rate error during reception is within the permissible error range, by

using the calculation expression shown below.

Figure 13-11. Permissible Baud Rate Range During Reception

1 data frame (11

FL)

FLmin

FLmax

Transfer rate

of UART0

Start bit

Bit 0

Bit 1

Bit 7

Parity bit

Minimum permissible

transfer rate

Maximum permissible

transfer rate

Stop bit

Start bit

Bit 0

Bit 1

Bit 7

Parity bit

Latch timing

Stop bit

Start bit

Bit 0

Bit 1

Bit 7

Parity bit

Stop bit

As shown in Figure 13-11, the latch timing of the receive data is determined by the counter set by baud rate

generator control register 0 (BRGC0) after the start bit has been detected. If the last data (stop bit) meets this

latch timing, the data can be correctly received.

Assuming that 11-bit data is received, the theoretical values can be calculated as follows.

FL = (Brate)

−

Brate: Baud rate of UART0

Set value of BRGC0

FL:

1-bit data length

Margin of latch timing: 2 clocks

Summary of Contents for 78K0/KD1 Series

Page 1: ...0121 µ µ µ µPD780121 A µ µ µ µPD780121 A1 µ µ µ µPD780122 µ µ µ µPD780122 A µ µ µ µPD780122 A1 µ µ µ µPD780123 µ µ µ µPD780123 A µ µ µ µPD780123 A1 µ µ µ µPD780124 µ µ µ µPD780124 A µ µ µ µPD780124 A1 µ µ µ µPD78F0124 µ µ µ µPD78F0124 A 78K0 KD1 8 Bit Single Chip Microcontrollers Preliminary User s Manual ...

Page 2: ...Preliminary User s Manual U16315EJ1V0UD 2 MEMO ...

Page 3: ...ust be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected to VDD or GND with a resistor if it is considered to have a possibility of being an output pin All handling related to the unused pins must be judged device by device and related specifications governing the devices 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note Power on does not necessarily ...

Page 4: ...on of these circuits software and information in the design of the customer s equipment shall be done under the full responsibility of the customer NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits software and information While NEC Corporation has been making continuous effort to enhance the reliability of its...

Page 5: ...9 9288 NEC Electronics Hong Kong Ltd Hong Kong Tel 2886 9318 Fax 2886 9022 9044 NEC Electronics Hong Kong Ltd Seoul Branch Seoul Korea Tel 02 528 0303 Fax 02 528 4411 NEC Electronics Shanghai Ltd Shanghai P R China Tel 021 6841 1138 Fax 021 6841 1137 NEC Electronics Taiwan Ltd Taipei Taiwan Tel 02 2719 2377 Fax 02 2719 5951 NEC Electronics Singapore Pte Ltd Novena Square Singapore Tel 253 8311 Fax...

Page 6: ...A 78F0124 A 780121 A1 780122 A1 780123 A1 780124 A1 Purpose This manual is intended to give users an understanding of the functions described in the Organization below Organization The 78K0 KD1 Series manual is separated into two parts this manual and the instructions edition common to the 78K 0 Series 78K0 KD1 User s Manual This Manual 78K 0 Series User s Manual Instructions Pin functions Interna...

Page 7: ...fined as a reserved word in the assembler and is already defined in the header file named sfrbit h in the C compiler To check the details of a register when you know the register name Refer to APPENDIX C REGISTER INDEX To know details of the 78K 0 Series instructions Refer to the separate document 78K 0 Series Instructions User s Manual U12326E Caution Examples in this manual employ the standard q...

Page 8: ...s U11537E RX78K0 Real Time OS Installation U11536E Project Manager Ver 3 12 or Later Windows Based U14610E Documents Related to Development Tools Hardware User s Manuals Document Name Document No IE 78K0 NS In Circuit Emulator U13731E IE 78K0 NS A In Circuit Emulator U14889E IE 780148 NS EM1 Emulation Board To be prepared Documents Related to Flash Memory Programming Document Name Document No PG F...

Page 9: ...P130 port 13 41 2 2 9 P140 port 14 41 2 2 10 AVREF 41 2 2 11 AVSS 41 2 2 12 RESET 42 2 2 13 REGC 42 2 2 14 X1 and X2 42 2 2 15 XT1 and XT2 42 2 2 16 VDD and EVDD 42 2 2 17 VSS and EVSS 42 2 2 18 VPP flash memory versions only 42 2 2 19 IC mask ROM versions only 42 2 3 Pin I O Circuits and Recommended Connection of Unused Pins 43 CHAPTER 3 CPU ARCHITECTURE 46 3 1 Memory Space 46 3 1 1 Internal prog...

Page 10: ...2 9 Port 14 97 4 3 Registers Controlling Port Function 98 4 4 Port Function Operations 102 4 4 1 Writing to I O port 102 4 4 2 Reading from I O port 102 4 4 3 Operations on I O port 102 CHAPTER 5 CLOCK GENERATOR 103 5 1 Functions of Clock Generator 103 5 2 Configuration of Clock Generator 104 5 3 Registers Controlling Clock Generator 105 5 4 System Clock Oscillator 112 5 4 1 X1 oscillator 112 5 4 ...

Page 11: ...rs 50 and 51 162 7 2 Configuration of 8 Bit Timer Event Counters 50 and 51 164 7 3 Registers Controlling 8 Bit Timer Event Counters 50 and 51 165 7 4 Operations of 8 Bit Timer Event Counters 50 and 51 171 7 4 1 Operation as interval timer 171 7 4 2 Operation as external event counter 173 7 4 3 Square wave output operation 174 7 4 4 PWM output operation 176 7 5 Cautions for 8 Bit Timer Event Counte...

Page 12: ...n of A D Converter 226 12 3 Registers Controlling A D Converter 228 12 4 A D Converter Operations 232 12 4 1 Basic operations of A D converter 232 12 4 2 Input voltage and conversion results 234 12 4 3 A D converter operation mode 235 12 5 How to Read A D Converter Characteristics Table 238 12 6 Cautions for A D Converter 240 CHAPTER 13 SERIAL INTERFACE UART0 245 13 1 Functions of Serial Interface...

Page 13: ...errupt 341 17 3 Register Controlling Key Interrupt 342 CHAPTER 18 STANDBY FUNCTION 343 18 1 Standby Function and Configuration 343 18 1 1 Standby function 343 18 1 2 Registers controlling standby function 345 18 2 Standby Function Operation 347 18 2 1 HALT mode 347 18 2 2 STOP mode 351 CHAPTER 19 RESET FUNCTION 354 19 1 Register for Confirming Reset Source 359 CHAPTER 20 CLOCK MONITOR 360 20 1 Fun...

Page 14: ...ication methods 395 26 1 2 Description of operation column 396 26 1 3 Description of flag operation column 396 26 2 Operation List 397 26 3 Instructions Listed by Addressing Type 405 CHAPTER 27 ELECTRICAL SPECIFICATIONS TARGET VALUES 408 CHAPTER 28 PACKAGE DRAWING 426 CHAPTER 29 CAUTIONS FOR WAIT 427 29 1 Cautions for Wait 427 29 2 Peripheral Hardware That Generates Wait 428 29 3 Example of Wait O...

Page 15: ...f General Purpose Registers 62 4 1 Port Types 78 4 2 Block Diagram of P00 and P03 81 4 3 Block Diagram of P01 82 4 4 Block Diagram of P02 83 4 5 Block Diagram of P10 84 4 6 Block Diagram of P11 and P14 85 4 7 Block Diagram of P12 86 4 8 Block Diagram of P13 87 4 9 Block Diagram of P15 88 4 10 Block Diagram of P16 and P17 89 4 11 Block Diagram of P20 to P27 90 4 12 Block Diagram of P30 to P32 91 4 ...

Page 16: ...7 Control Register Settings for Interval Timer Operation 139 6 8 Interval Timer Configuration Diagram 140 6 9 Timing of Interval Timer Operation 140 6 10 Control Register Settings for PPG Output Operation 141 6 11 Configuration of PPG Output 142 6 12 PPG Output Operation Timing 142 6 13 Control Register Settings for Pulse Width Measurement with Free Running Counter and One Capture Register 143 6 1...

Page 17: ...e Control Register 50 TMC50 167 7 6 Format of 8 Bit Timer Mode Control Register 51 TMC51 168 7 7 Format of Port Mode Register 1 PM1 170 7 8 Format of Port Mode Register 3 PM3 170 7 9 Interval Timer Operation Timing 171 7 10 External Event Counter Operation Timing with Rising Edge Specified 173 7 11 Square Wave Output Operation Timing 175 7 12 PWM Output Operation Timing 177 7 13 Timing of Operatio...

Page 18: ...rmat of Analog Input Channel Specification Register ADS 230 12 7 Format of Power Fail Comparison Mode Register PFM 231 12 8 Format of Power Fail Comparison Threshold Register PFT 231 12 9 Basic Operation of A D Converter 233 12 10 Relationship Between Analog Input Voltage and A D Conversion Result 234 12 11 A D Conversion Operation 235 12 12 Power Fail Detection When PFEN 1 and PFCM 0 236 12 13 Ov...

Page 19: ...ta 290 14 12 Example of Normal UART Transmit Receive Data Format 291 14 13 Normal Transmission Completion Interrupt Request Timing 293 14 14 Processing Flow of Continuous Transmission 295 14 15 Timing of Starting Continuous Transmission 296 14 16 Timing of Ending Continuous Transmission 297 14 17 Reception Completion Interrupt Request Timing 298 14 18 Reception Error Interrupt 299 14 19 Noise Filt...

Page 20: ...Mode Release by Interrupt Request Generation 352 18 7 STOP Mode Release by RESET Input 353 19 1 Block Diagram of Reset Function 355 19 2 Timing of Reset by RESET Input 356 19 3 Timing of Reset Due to Watchdog Timer Overflow 356 19 4 Timing of Reset in STOP Mode by RESET Input 356 19 5 Format of Reset Control Flag Register RESF 359 20 1 Block Diagram of Clock Monitor 360 20 2 Format of Clock Monito...

Page 21: ... Connection of Flashpro III Flashpro IV in UART UART0 Mode Using Handshake 389 25 7 Connection of Flashpro III Flashpro IV in UART UART6 Mode 389 25 8 Example of Wiring Adapter for Flash Memory Writing in 3 Wire Serial I O Mode 390 25 9 Example of Wiring Adapter for Flash Memory Writing in 3 Wire Serial I O Mode Using Handshake 391 25 10 Example of Wiring Adapter for Flash Memory Writing in UART U...

Page 22: ...illation Control Flags and Clock Oscillation Status 121 5 5 Time Required to Switch Between Ring OSC Clock and X1 Input Clock 122 5 6 Maximum Time Required for CPU Clock Switchover 123 5 7 Clock and Register Setting 128 6 1 Configuration of 16 Bit Timer Event Counter 00 130 6 2 TI000 Pin Valid Edge and CR000 CR010 Capture Trigger 131 6 3 TI010 Pin Valid Edge and CR000 Capture Trigger 131 7 1 Confi...

Page 23: ...me from Generation of Maskable Interrupt Request Until Servicing 334 16 5 Interrupt Request Enabled for Multiple Interrupt Servicing During Interrupt Servicing 337 17 1 Assignment of Key Interrupt Detection Pins 341 17 2 Configuration of Key Interrupt 341 18 1 Relationship Between HALT Mode STOP Mode and Clock 343 18 2 Operating Statuses in HALT Mode 347 18 3 Operation After HALT Mode Release 350 ...

Page 24: ...al U16315EJ1V0UD 24 LIST OF TABLES 3 3 Table No Title Page 29 1 Registers That Generate Wait and Number of CPU Wait Clocks 428 29 2 Number of Wait Clocks and Number of Execution Clocks on Occurrence of Wait A D Converter 429 ...

Page 25: ... via the CPU default start using the on chip Ring OSC On chip clock monitor function using on chip Ring OSC On chip watchdog timer operable with Ring OSC clock On chip UART supporting LIN Local Interconnect Network bus On chip key interrupt function On chip clock output controller On chip regulator Minimum instruction execution time can be changed from high speed 0 2 µs 10 MHz operation with X1 in...

Page 26: ... for body electricals power windows keyless entry reception etc Sub microcontrollers for control Home audio car audio AV equipment PC peripheral equipment keyboards etc Household electrical appliances Outdoor air conditioner units Microwave ovens electric rice cookers Industrial equipment Pumps Vending machines FA ...

Page 27: ...in plastic LQFP 10 10 Special µPD78F0124M1GB 8ET 52 pin plastic LQFP 10 10 Standard µPD78F0124M2GB 8ET 52 pin plastic LQFP 10 10 Standard µPD78F0124M3GB 8ET 52 pin plastic LQFP 10 10 Standard µPD78F0124M4GB 8ET 52 pin plastic LQFP 10 10 Standard µPD78F0124M5GB 8ET 52 pin plastic LQFP 10 10 Standard µPD78F0124M6GB 8ET 52 pin plastic LQFP 10 10 Standard µPD78F0124M1GB A 8ET 52 pin plastic LQFP 10 10...

Page 28: ...e mask ROM versions are as follows Table 1 1 Flash Memory Versions Corresponding to Mask Options of Mask ROM Versions Mask Option POC Circuit Ring OSC Flash Memory Versions Part Number Cannot be stopped µPD78F0124M1GB 8ET µPD78F0124M1GB A 8ET POC cannot be used Can be stopped by software µPD78F0124M2GB 8ET µPD78F0124M2GB A 8ET Cannot be stopped µPD78F0124M3GB 8ET µPD78F0124M3GB A 8ET POC used VPOC...

Page 29: ... P00 TI000 P01 TI010 TO00 P02 P03 P10 SCK10 TxD0 P11 SI10 RxD0 P12 SO10 P13 TxD6 P14 RxD6 EVDD P20 ANI0 P21 ANI1 P22 ANI2 P23 ANI3 P24 ANI4 P25 ANI5 P26 ANI6 P27 ANI7 P70 KR0 P71 KR1 P72 KR2 P73 KR3 P74 KR4 P33 TI51 TO51 INTP4 P32 INTP3 P31 INTP2 P30 INTP1 P140 PCL INTP6 P17 TI50 TO50 P16 TOH1 INTP5 P15 TOH0 P60 P61 P62 P63 EV SS 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27...

Page 30: ...0 to P17 Port 1 P20 to P27 Port 2 P30 to P33 Port 3 P60 to P63 Port 6 P70 to P77 Port 7 P120 Port 12 P130 Port 13 P140 Port 14 PCL Programmable clock output REGC Regulator capacitance RESET Reset RxD0 RxD6 Receive data SCK10 Serial clock input output SI10 Serial data input SO10 Serial data output TI000 TI010 TI50 TI51 Timer input TO00 TO50 TO51 TOH0 TOH1 Timer output TxD0 TxD6 Transmit data VDD Po...

Page 31: ...sk ROM 32 KB RAM 1 KB Mask ROM 24 KB RAM 1 KB Mask ROM 16 KB RAM 512 bytes PD780124 PD780123 PD780122 Mask ROM 8 KB RAM 512 bytes PD780121 78K0 KD1 Series 52 pin 10 10 mm 0 65 mm pitch PD78F0148 Flash memory 60 KB RAM 2 KB Mask ROM 60 KB RAM 2 KB Mask ROM 48 KB RAM 2 KB Mask ROM 32 KB RAM 1 KB PD780148 PD780146 PD780144 Mask ROM 24 KB RAM 1 KB PD780143 78K0 KF1 Series 80 pin 12 12 mm 0 5 mm pitch ...

Page 32: ...1 input 2 to 10 MHz Sub 32 768 kHz Clock Ring OSC 240 kHz TYP CMOS I O 17 19 26 38 54 CMOS input 4 8 CMOS output 1 Port N ch open drain I O 4 16 bits TM0 1 ch 2 ch 1 ch 2 ch 8 bits TM5 1 ch 2 ch 8 bits TMH 2 ch For watch 1 ch Timer WDT 1 ch 3 wire CSINote 1 ch 2 ch 1 ch 2 ch Automatic transmit receive 3 wire CSI 1 ch UARTNote 1 ch Serial interface UART supporting LIN bus 1 ch 10 bit A D converter ...

Page 33: ... TOH1 P16 TI50 TO50 P17 8 bit timer event counter 50 8 A D converter RxD0 P11 TxD0 P10 Serial interface UART0 Watchdog timer RxD6 P14 TxD6 P13 Serial interface UART6 AVREF AVSS INTP1 P30 to INTP4 P33 4 INTP0 P120 8 System control RESET X1 X2 Clock monitor Power on clear low voltage indicator Reset control Port 6 P60 to P63 4 Port 7 P70 to P77 Port 12 P120 Port 13 P130 8 Port 14 P140 Ring OSC XT1 X...

Page 34: ... 8 3 µs 16 6 µs 33 2 µs 66 4 µs 132 8 µs TYP Ring OSC clock fR 240 kHz TYP operation Minimum instruction execution time 122 µs subsystem clock fXT 32 768 kHz operation Instruction set 16 bit operation Multiply divide 8 bits 8 bits 4 banks Bit manipulate set reset test and Boolean operation BCD adjust etc I O ports Total 39 CMOS I O 26 CMOS input 8 CMOS output 1 N ch open drain I O 4 Timers 16 bit ...

Page 35: ...A products TA 40 to 85 C A1 products TA 40 to 110 C µPD780121 780122 780123 and 780124 only Package 52 pin plastic LQFP 10 10 An outline of the timer is shown below 16 Bit Timer Event Counter 00 8 Bit Timer Event Counters 50 and 51 8 Bit Timers H0 and H1 Watch Timer Watchdog Timer Interval timer 1 channel 2 channels 2 channels 1 channelNote 1 channel Operation mode External event counter 1 channel...

Page 36: ...33 I O Port 3 4 bit I O port Input output can be specified in 1 bit units Use of an on chip pull up resistor can be specified by a software setting Input INTP4 TI51 TO51 P60 to P63 I O Port 6 4 bit I O port N ch open drain Input output can be specified in 1 bit units Use of an on chip pull up resistor can be specified by a mask option only for mask ROM versions Input P70 to P77 I O Port 7 8 bit I ...

Page 37: ...0 of 16 bit timer event counter 00 Input P01 TO00 TO00 Output 16 bit timer event counter 00 output Input P01 TI010 TI50 External count clock input to 8 bit timer event counter 50 P17 TO50 TI51 Input External count clock input to 8 bit timer event counter 51 Input P33 TO51 INTP4 TO50 8 bit timer event counter 50 output P17 TI50 TO51 8 bit timer event counter 51 output P33 TI51 INTP4 TOH0 8 bit time...

Page 38: ...sitive power supply except for ports EVDD Positive power supply for ports VSS Ground potential except for ports EVSS Ground potential for ports IC Internally connected Connect directly to EVSS or VSS VPP Flash memory programming mode setting High voltage application for program write verify Connect directly to EVSS or VSS in normal operation mode ...

Page 39: ...r signal to the capture register CR000 of 16 bit timer event counter 00 c TO00 This is a timer output pin 2 2 2 P10 to P17 port 1 P10 to P17 function as an 8 bit I O port These pins also function as pins for external interrupt request input serial interface data I O clock I O and timer I O The following operation modes can be specified in 1 bit units 1 Port mode P10 to P17 function as an 8 bit I O...

Page 40: ...n as a 4 bit I O port P30 to P33 can be set to input or output in 1 bit units using port mode register 3 PM3 Use of an on chip pull up resistor can be specified by pull up resistor option register 3 PU3 2 Control mode P30 to P33 function as external interrupt request input pins and timer I O pins a INTP1 to INTP4 These are the external interrupt request input pins for which the valid edge rising e...

Page 41: ... and falling edges can be specified 2 2 8 P130 port 13 P130 functions as a 1 bit output only port 2 2 9 P140 port 14 P140 functions as a 1 bit I O port This pin also functions as a pin for external interrupt request input and clock output The following operation modes can be specified in 1 bit units 1 Port mode P140 functions as a 1 bit I O port P140 can be set to input or output in 1 bit units us...

Page 42: ...T2 pin 2 2 16 VDD and EVDD VDD is the positive power supply pin for other than ports EVDD is the positive power supply pin for ports 2 2 17 VSS and EVSS VSS is the ground potential pin for other than ports EVSS is the ground potential pin for ports 2 2 18 VPP flash memory versions only This is a pin for flash memory programming mode setting and high voltage application for program write verify Con...

Page 43: ...tput Leave open P20 ANI0 to P27 ANI7 9 C Input Connect to EVDD or EVSS P30 INTP1 to P32 INTP3 P33 TI51 TO51 INTP4 8 A Input Independently connect to EVDD or EVSS via a resistor Output Leave open P60 P61 Mask ROM version 13 S P60 P61 Flash memory version 13 R P62 P63 Mask ROM version 13 W P62 P63 Flash memory version 13 V Input Connect to EVSS Output Leave open and keep this pin to low P70 KR0 to P...

Page 44: ...ype 9 C Schmitt triggered input with hysteresis characteristics IN Pullup enable Data Output disable EVDD P ch VDD P ch IN OUT N ch EVDD P ch N ch Data OUT IN Comparator VREF threshold voltage AVSS P ch N ch Input enable Pullup enable Data Output disable Input enable EVDD P ch VDD P ch IN OUT N ch Data Output disable IN OUT N ch Type 13 R ...

Page 45: ...uit List 2 2 Type 13 V Type 13 S Type 13 W Type 16 Data Output disable IN OUT N ch EVDD Mask option Data Output disable IN OUT N ch Input enable Middle voltage input buffer Data Output disable IN OUT N ch EVDD Mask option Input enable Middle voltage input buffer P ch Feedback cut off XT1 XT2 ...

Page 46: ...memory capacity the initial value of the internal memory size switching register IMS of all products in the 78K0 KD1 Series is fixed IMS CFH Therefore set the value corresponding to each product as indicated below Table 3 1 Set Values of Internal Memory Size Switching Register IMS Internal Memory Size Switching Register IMS µPD780121 42H µPD780122 44H µPD780123 C6H µPD780124 C8H µPD78F0124 Value c...

Page 47: ...General purpose registers 32 8 bits Reserved Internal ROM 8192 8 bits Program memory space Data memory space Vector table area H CALLT table area Program area CALLF entry area Program area 0 0 0 0 H F 3 0 0 H 0 4 0 0 H F 7 0 0 H 0 8 0 0 H F F 7 0 H 0 0 8 0 H F F F 0 H 0 0 0 1 H F F F 1 H 0 0 0 0 H F F F 1 H 0 0 0 2 H F F C F H 0 0 D F H F D E F H 0 E E F H F F E F H 0 0 F F H F F F F ...

Page 48: ...General purpose registers 32 8 bits Reserved Internal ROM 16384 8 bits Program memory space Data memory space Vector table area H CALLT table area Program area CALLF entry area Program area 0 0 0 0 H F 3 0 0 H 0 4 0 0 H F 7 0 0 H 0 8 0 0 H F F 7 0 H 0 0 8 0 H F F F 0 H 0 0 0 1 H F F F 3 H 0 0 0 0 H F F F 3 H 0 0 0 4 H F F C F H 0 0 D F H F D E F H 0 E E F H F F E F H 0 0 F F H F F F F ...

Page 49: ...General purpose registers 32 8 bits Reserved Internal ROM 24576 8 bits Program memory space Data memory space Vector table area H CALLT table area Program area CALLF entry area Program area 0 0 0 0 H F 3 0 0 H 0 4 0 0 H F 7 0 0 H 0 8 0 0 H F F 7 0 H 0 0 8 0 H F F F 0 H 0 0 0 1 H F F F 5 H 0 0 0 0 H F F F 5 H 0 0 0 6 H F F A F H 0 0 B F H F D E F H 0 E E F H F F E F H 0 0 F F H F F F F ...

Page 50: ...General purpose registers 32 8 bits Reserved Internal ROM 32768 8 bits Program memory space Data memory space Vector table area H CALLT table area Program area CALLF entry area Program area 0 0 0 0 H F 3 0 0 H 0 4 0 0 H F 7 0 0 H 0 8 0 0 H F F 7 0 H 0 0 8 0 H F F F 0 H 0 0 0 1 H F F F 7 H 0 0 0 0 H F F F 7 H 0 0 0 8 H F F A F H 0 0 B F H F D E F H 0 E E F H F F E F H 0 0 F F H F F F F ...

Page 51: ... General purpose registers 32 8 bits Reserved Flash memory 32768 8 bits Program memory space Data memory space Vector table area H CALLT table area Program area CALLF entry area Program area 0 0 0 0 H F 3 0 0 H 0 4 0 0 H F 7 0 0 H 0 8 0 0 H F F 7 0 H 0 0 8 0 H F F F 0 H 0 0 0 1 H F F F 7 H 0 0 0 0 H F F F 7 H 0 0 0 8 H F F A F H 0 0 B F H F D E F H 0 E E F H F F E F H 0 0 F F H F F F F ...

Page 52: ...addresses for branch upon RESET input or generation of each interrupt request are stored in the vector table area Of the 16 bit address the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd addresses Table 3 3 Vector Table Vector Table Address Interrupt Source Vector Table Address Interrupt Source 001AH INTTMH1 0000H RESET input POC LVI clock monitor WDT 001CH INTTM...

Page 53: ...yte area FEE0H to FEFFH is assigned to four general purpose register banks consisting of eight 8 bit registers per one bank This area cannot be used as a program area in which instructions are written and executed The internal high speed RAM can also be used as a stack memory 3 1 3 Special function register SFR area On chip peripheral hardware special function registers SFRs are allocated in the a...

Page 54: ... areas containing data memory in particular special addressing methods designed for the functions of special function registers SFR and general purpose registers are available for use Data memory addressing is illustrated in Figures 3 6 to 3 10 For details of each addressing mode refer to 3 4 Operand Address Addressing Figure 3 6 Data Memory Addressing µ µ µ µPD780121 Special function registers SF...

Page 55: ...dressing SFR addressing Internal high speed RAM 512 8 bits General purpose registers 32 8 bits Reserved Internal ROM 16384 8 bits Register addressing Direct addressing Register indirect addressing Based addressing Based indexed addressing H 0 0 0 0 H F F F 3 H 0 0 0 4 H F F C F H 0 0 D F H F D E F H 0 E E F H F F E F H 0 0 F F H F F F F H F 1 E F H 0 2 E F H F 1 F F H 0 2 F F ...

Page 56: ...dressing SFR addressing Internal high speed RAM 1024 8 bits General purpose registers 32 8 bits Reserved Internal ROM 24576 8 bits Register addressing Direct addressing Register indirect addressing Based addressing Based indexed addressing H 0 0 0 0 H F F F 5 H 0 0 0 6 H F F A F H 0 0 B F H F D E F H 0 E E F H F F E F H 0 0 F F H F F F F H F 1 E F H 0 2 E F H F 1 F F H 0 2 F F ...

Page 57: ...dressing SFR addressing Internal high speed RAM 1024 8 bits General purpose registers 32 8 bits Reserved Internal ROM 32768 8 bits Register addressing Direct addressing Register indirect addressing Based addressing Based indexed addressing H 0 0 0 0 H F F F 7 H 0 0 0 8 H F F A F H 0 0 B F H F D E F H 0 E E F H F F E F H 0 0 F F H F F F F H F 1 E F H 0 2 E F H F 1 F F H 0 2 F F ...

Page 58: ...ddressing SFR addressing Internal high speed RAM 1024 8 bits General purpose registers 32 8 bits Reserved Flash memory 32768 8 bits Register addressing Direct addressing Register indirect addressing Based addressing Based indexed addressing H 0 0 0 0 H F F F 7 H 0 0 0 8 H F F A F H 0 0 B F H F D E F H 0 E E F H F F E F H 0 0 F F H F F F F H F 1 E F H 0 2 E F H F 1 F F H 0 2 F F ...

Page 59: ...bytes of the instruction to be fetched When a branch instruction is executed immediate data and register contents are set RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter Figure 3 11 Format of Program Counter 15 0 PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 2 Program status word PSW The program status word is an 8 bit r...

Page 60: ...ister banks In these flags the 2 bit information that indicates the register bank selected by SEL RBn instruction execution is stored d Auxiliary carry flag AC If the operation result has a carry from bit 3 or a borrow at bit 3 this flag is set 1 It is reset 0 in all other cases e In service priority flag ISP This flag manages the priority of acknowledgeable maskable vectored interrupts When this ...

Page 61: ... undefined be sure to initialize the SP before instruction execution Figure 3 14 Data to Be Saved to Stack Memory Interrupt and BRK instructions PSW PC15 to PC8 PC15 to PC8 PC7 to PC0 Register pair lower SP SP _ 2 SP _ 2 Register pair upper CALL CALLF and CALLT instructions PUSH rp instruction SP _ 1 SP SP SP _ 2 SP _ 2 SP _ 1 SP PC7 to PC0 SP _ 3 SP _ 2 SP _ 1 SP SP SP _ 3 Figure 3 15 Data to Be ...

Page 62: ...es X A C B E D L H AX BC DE and HL and absolute names R0 to R7 and RP0 to RP3 Register banks to be used for instruction execution are set by the CPU control instruction SEL RBn Because of the 4 register bank configuration an efficient program can be created by switching between a register for normal processing and a register for interrupts for each bank Figure 3 16 Configuration of General Purpose...

Page 63: ...he 8 bit manipulation instruction operand sfr This manipulation can also be specified with an address 16 bit manipulation Describe the symbol reserved by the assembler for the 16 bit manipulation instruction operand sfrp When specifying an address describe an even address Table 3 5 gives a list of the special function registers The meanings of items in the table are as follows Symbol Symbol indica...

Page 64: ...ure compare register 010 CR010 R W 0000H FF16H 8 bit timer counter 50 TM50 R 00H FF17H 8 bit timer compare register 50 CR50 R W 00H FF18H 8 bit timer H compare register 00 CMP00 R W 00H FF19H 8 bit timer H compare register 10 CMP10 R W 00H FF1AH 8 bit timer H compare register 01 CMP01 R W 00H FF1BH 8 bit timer H compare register 11 CMP11 R W 00H FF1FH 8 bit timer counter 51 TM51 R 00H FF20H Port m...

Page 65: ...ion register 6 CKSR6 R W 00H FF57H Baud rate generator control register 6 BRGC6 R W FFH FF58H Asynchronous serial interface control register 6 ASICL6 R W 16H FF69H 8 bit timer H mode register 0 TMHMD0 R W 00H FF6AH Timer clock selection register 50 TCL50 R W 00H FF6BH 8 bit timer mode control register 50 TMC50 R W 00H FF6CH 8 bit timer H mode register 1 TMHMD1 R W 00H FF6DH 8 bit timer H carrier c...

Page 66: ...egister LVIS R W 00H FFE0H Interrupt request flag register 0L IF0L R W 00H FFE1H Interrupt request flag register 0H IF0 IF0H R W 00H FFE2H Interrupt request flag register 1L IF1L R W 00H FFE4H Interrupt mask flag register 0L MK0L R W FFH FFE5H Interrupt mask flag register 0H MK0 MK0H R W FFH FFE6H Interrupt mask flag register 1L MK1L R W FFH FFE8H Priority specification flag register 0L PR0L R W F...

Page 67: ...ive addressing Function The value obtained by adding 8 bit immediate data displacement value jdisp8 of an instruction code to the start address of the following instruction is transferred to the program counter PC and branched The displacement value is treated as signed two s complement data 128 to 127 and bit 7 becomes a sign bit In other words relative addressing consists of relative branching f...

Page 68: ...en the CALL addr16 or BR addr16 or CALLF addr11 instruction is executed CALL addr16 and BR addr16 instructions can be branched to the entire memory space The CALLF addr11 instruction is branched to the 0800H to 0FFFH area Illustration In the case of CALL addr16 and BR addr16 instructions 15 0 PC 8 7 7 0 CALL or BR Low Addr High Addr In the case of CALLF addr11 instruction 15 0 PC 8 7 7 0 fa10 8 11...

Page 69: ...xecuted This instruction references the address stored in the memory table from 40H to 7FH and allows branching to the entire memory space Illustration 15 1 15 0 PC 7 0 Low Addr High Addr Memory Table Effective address 1 Effective address 0 1 0 0 0 0 0 0 0 0 8 7 8 7 6 5 0 0 1 1 1 7 6 5 1 0 ta4 0 Operation code 3 3 4 Register addressing Function Register pair AX contents to be specified with an ins...

Page 70: ...nstruction Register to Be Specified by Implied Addressing MULU A register for multiplicand and AX register for product storage DIVUW AX register for dividend and quotient storage ADJBA ADJBS A register for storage of numeric values that become decimal correction targets ROR4 ROL4 A register for storage of digit data that undergoes digit rotation Operand format Because implied addressing can be aut...

Page 71: ...following operand format is executed When an 8 bit register is specified one of the eight registers is specified with 3 bits in the operation code Operand format Identifier Description r X A C B E D L H rp AX BC DE HL r and rp can be described by absolute names R0 to R7 and RP0 to RP3 as well as function names X A C B E D L H AX BC DE and HL Description example MOV A C when selecting C register as...

Page 72: ...ssed with immediate data in an instruction word becoming an operand address Operand format Identifier Description addr16 Label or 16 bit immediate data Description example MOV A 0FE00H when setting addr16 to FE00H Operation code 1 0 0 0 1 1 1 0 OP code 0 0 0 0 0 0 0 0 00H 1 1 1 1 1 1 1 0 FEH Illustration Memory 0 7 addr16 lower addr16 upper OP code ...

Page 73: ...unter are mapped in this area allowing SFRs to be manipulated with a small number of bytes and clocks When 8 bit immediate data is at 20H to FFH bit 8 of an effective address is set to 0 When it is at 00H to 1FH bit 8 is set to 1 Refer to the Illustration shown below Operand format Identifier Description saddr Label or FE20H to FF1FH immediate data saddrp Label or FE20H to FF1FH immediate data eve...

Page 74: ... FF00H to FFCFH and FFE0H to FFFFH However the SFRs mapped at FF00H to FF1FH can be accessed with short direct addressing Operand format Identifier Description sfr Special function register name sfrp 16 bit manipulatable special function register name even address only Description example MOV PM0 A when selecting PM0 FF20H as sfr Operation code 1 1 1 1 0 1 1 0 OP code 0 0 1 0 0 0 0 0 20H sfr offse...

Page 75: ...ect flag RBS0 and RBS1 serve as an operand address for addressing the memory This addressing can be carried out for all the memory spaces Operand format Identifier Description DE HL Description example MOV A DE when selecting DE as register pair Operation code 1 0 0 0 0 1 0 1 Illustration 16 0 8 D 7 E 0 7 7 0 A DE The contents of the memory addressed are transferred Memory The memory address speci...

Page 76: ...nk specified by the register bank select flag RBS0 and RBS1 and the sum is used to address the memory Addition is performed by expanding the offset data as a positive number to 16 bits A carry from the 16th bit is ignored This addressing can be carried out for all the memory spaces Operand format Identifier Description HL byte Description example MOV A HL 10H when setting byte to 10H Operation cod...

Page 77: ...carry from the 16th bit is ignored This addressing can be carried out for all the memory spaces Operand format Identifier Description HL B HL C Description example In the case of MOV A HL B Operation code 1 0 1 0 1 0 1 1 3 4 9 Stack addressing Function The stack area is indirectly addressed with the stack pointer SP contents This addressing method is automatically employed when the PUSH POP subrou...

Page 78: ...control operations The functions of each port are shown in Table 4 1 In addition to the function as digital I O ports these ports have several alternate functions For details of the alternate functions refer to CHAPTER 2 PIN FUNCTIONS Figure 4 1 Port Types Port 2 P20 P27 Port 3 P30 P33 Port 0 P00 P03 Port 1 P10 P17 Port 6 P60 P63 Port 7 P70 P77 P120 Port 12 Port 14 P140 P130 Port 13 ...

Page 79: ... O Port 3 4 bit I O port Input output can be specified in 1 bit units Use of an on chip pull up resistor can be specified by a software setting Input INTP4 TI51 TO51 P60 to P63 I O Port 6 4 bit I O port N ch open drain Input output can be specified in 1 bit units Use of an on chip pull up resistor can be specified by a mask option only for mask ROM versions Input P70 to P77 I O Port 7 8 bit I O po...

Page 80: ...onfiguration Control registers Port mode register PM0 PM1 PM3 PM6 PM7 PM12 PM14 Pull up resistor option register PU0 PU1 PU3 PU7 PU12 PU14 Input switch control register ISC Port Total 39 CMOS I O 26 CMOS input 8 CMOS output 1 N ch open drain I O 4 Pull up resistor Mask ROM version Total 30 software control 26 mask option specification 4 Flash memory version Total 26 ...

Page 81: ...an on chip pull up resistor can be specified by pull up resistor option register 0 PU0 This port can also be used for timer I O RESET input sets port 0 to input mode Figures 4 2 to 4 4 show block diagrams of port 0 Figure 4 2 Block Diagram of P00 and P03 P00 TI000 P03 WRPU RD WRPORT WRPM PU00 PU03 Alternate function Output latch P00 P03 PM00 PM03 EVDD P ch Selector Internal bus PU0 Pull up resisto...

Page 82: ...Figure 4 3 Block Diagram of P01 P01 TI010 TO00 WRPU RD WRPORT WRPM PU01 Alternate function Output latch P01 PM01 Alternate function EVDD P ch Selector Internal bus PU0 Pull up resistor option register 0 PM Port mode register RD Port 0 read signal WR Port 0 write signal ...

Page 83: ...6315EJ1V0UD 83 Figure 4 4 Block Diagram of P02 P02 WRPU RD WRPORT WRPM PU02 Output latch P02 PM02 Alternate function EVDD P ch Selector Internal bus PU0 Pull up resistor option register 0 PM Port mode register RD Port 0 read signal WR Port 0 write signal ...

Page 84: ...used for external interrupt request input serial interface data I O clock I O and timer I O RESET input sets port 1 to input mode Figures 4 5 to 4 10 show block diagrams of port 1 Caution When P10 SCK10 TxD0 P11 SI10 RxD0 and P12 SO10 are used as general purpose ports do not write to serial clock selection register 10 CSIC10 Figure 4 5 Block Diagram of P10 P10 SCK10 TxD0 WRPU RD WRPORT WRPM PU10 A...

Page 85: ...e 4 6 Block Diagram of P11 and P14 P11 SI10 RxD0 P14 RxD6 WRPU RD WRPORT WRPM PU11 PU14 Alternate function Output latch P11 P14 PM11 PM14 EVDD P ch Selector Internal bus PU1 Pull up resistor option register 1 PM Port mode register RD Port 1 read signal WR Port 1 write signal ...

Page 86: ...15EJ1V0UD 86 Figure 4 7 Block Diagram of P12 P12 SO10 WRPU RD WRPORT WRPM PU12 Output latch P12 PM12 Alternate function EVDD P ch Selector Internal bus PU1 Pull up resistor option register 1 PM Port mode register RD Port 1 read signal WR Port 1 write signal ...

Page 87: ...15EJ1V0UD 87 Figure 4 8 Block Diagram of P13 P13 TxD6 WRPU RD WRPORT WRPM PU13 Output latch P13 PM13 Alternate function EVDD P ch Internal bus Selector PU1 Pull up resistor option register 1 PM Port mode register RD Port 1 read signal WR Port 1 write signal ...

Page 88: ...15EJ1V0UD 88 Figure 4 9 Block Diagram of P15 P15 TOH0 WRPU RD WRPORT WRPM PU15 Output latch P15 PM15 Alternate function EVDD P ch Selector Internal bus PU1 Pull up resistor option register 1 PM Port mode register RD Port 1 read signal WR Port 1 write signal ...

Page 89: ...Diagram of P16 and P17 P16 TOH1 INTP5 P17 TI50 TO50 WRPU RD WRPORT WRPM PU16 PU17 Alternate function Output latch P16 P17 PM16 PM17 Alternate function EVDD P ch Selector Internal bus PU1 Pull up resistor option register 1 PM Port mode register RD Port 1 read signal WR Port 1 write signal ...

Page 90: ... 4 2 3 Port 2 Port 2 is an 8 bit input only port This port can also be used for A D converter analog input Figure 4 11 shows a block diagram of port 2 Figure 4 11 Block Diagram of P20 to P27 VREF RD A D converter P20 ANI0 to P27 ANI7 Internal bus RD Port 2 read signal ...

Page 91: ... specified by pull up resistor option register 3 PU3 This port can also be used for external interrupt request input RESET input sets port 3 to input mode Figures 4 12 and 4 13 show block diagrams of port 3 Figure 4 12 Block Diagram of P30 to P32 P30 INTP1 to P32 INTP3 WRPU RD WRPORT WRPM PU30 to PU32 Alternate function Output latch P30 to P32 PM30 to PM32 EVDD P ch Selector Internal bus PU3 Pull ...

Page 92: ...ure 4 13 Block Diagram of P33 P33 INTP4 TI51 TO51 WRPU RD WRPORT WRPM PU33 Alternate function Output latch P33 PM33 Alternate function EVDD P ch Selector Internal bus PU0 Pull up resistor option register 3 PM Port mode register RD Port 3 read signal WR Port 3 write signal ...

Page 93: ...ersion Table 4 3 Pull up Resistor of Port 6 Pins P60 to P63 Mask ROM version An on chip pull up resistor can be specified in 1 bit units by mask option Flash memory version On chip pull up resistors are not provided RESET input sets port 6 to input mode Figure 4 14 shows a block diagram of port 6 Figure 4 14 Block Diagram of P60 to P63 RD P60 to P63 WRPORT WRPM Output latch P60 to P63 PM60 to PM63...

Page 94: ...ip pull up resistor can be specified by pull up resistor option register 7 PU7 This port can also be used for key return input RESET input sets port 7 to input mode Figure 4 15 shows a block diagram of port 7 Figure 4 15 Block Diagram of P70 to P77 P70 KR0 to P77 KR7 WRPU RD WRPORT WRPM PU70 to PU77 Alternate function Output latch P70 to P77 PM70 to PM77 EVDD P ch Selector Internal bus PU7 Pull up...

Page 95: ...p pull up resistor can be specified by pull up resistor option register 12 PU12 This port can also be used for external interrupt input RESET input sets port 12 to input mode Figure 4 16 shows a block diagram of port 12 Figure 4 16 Block Diagram of P120 P120 INTP0 WRPU RD WRPORT WRPM PU120 Alternate function Output latch P120 PM120 EVDD P ch Selector Internal bus PU12 Pull up resistor option regis...

Page 96: ...Manual U16315EJ1V0UD 96 4 2 8 Port 13 Port 13 is a 1 bit output only port Figure 4 17 shows a block diagram of port 13 Figure 4 17 Block Diagram of P130 RD Output latch P130 WRPORT P130 Internal bus RD Port 13 read signal WD Port 13 write signal ...

Page 97: ...or can be specified by pull up resistor option register 14 PU14 This port can also be used for external interrupt request input and clock output RESET input sets port 14 to input mode Figure 4 18 shows a block diagram of port 14 Figure 4 18 Block Diagram of P140 P140 PCL INTP6 WRPU RD WRPORT WRPM PU140 Alternate function Output latch P140 PM140 Alternate function EVDD P ch Selector Internal bus PU...

Page 98: ...rs to FFH When port pins are used as alternate function pins set the port mode register and output latch as shown in Table 4 4 Figure 4 19 Format of Port Mode Register 7 1 Symbol PM0 6 1 5 1 4 1 3 PM03 2 PM02 1 PM01 0 PM00 Address FF20H After reset FFH R W R W 7 PM17 PM1 6 PM16 5 PM15 4 PM14 3 PM13 2 PM12 1 PM11 0 PM10 FF21H FFH R W 7 1 PM3 6 1 5 1 4 1 3 PM33 2 PM32 1 PM31 0 PM30 FF23H FFH R W 7 1...

Page 99: ...tput 0 0 Input 1 SCK10 Output 0 1 P10 TxD0 Output 0 1 SI10 Input 1 P11 RxD0 Input 1 P12 SO10 Output 0 0 P13 TxD6 Output 0 1 P14 RxD6 Input 1 P15 TOH0 Output 0 0 TOH1 Output 0 0 P16 INTP5 Input 1 TI50 Input 1 P17 TO50 Output 0 0 P30 to P32 INTP1 to INTP3 Input 1 INTP4 Input 1 TI51 Input 1 P33 TO51 Output 0 0 P70 to P77 KR0 to KR7 Input 1 P120 INTP0 Input 1 PCL Output 0 0 P140 INTP6 Input 1 Remark D...

Page 100: ... These registers can be set by a 1 bit or 8 bit memory manipulation instruction RESET input clears these registers to 00H Caution Use of a pull up resistor can be specified for P60 to P63 pins by a mask option only in the mask ROM versions Figure 4 20 Format of Pull up Resistor Option Register 7 0 Symbol PU0 6 0 5 0 4 0 3 PU03 2 PU02 1 PU01 0 PU00 Address FF30H After reset 00H R W R W 7 PU17 PU1 6...

Page 101: ...ation during LIN reception refer to Figure 14 3 Port Configuration for LIN Reception Operation in CHAPTER 14 SERIAL INTERFACE UART6 This register can be set by a 1 bit or 8 bit memory manipulation instruction RESET input clears this register to 00H Figure 4 21 Format of Input Switch Control Register ISC Address FF4FH After reset 00H R W Symbol 7 6 5 4 3 2 1 0 ISC 0 0 0 0 0 0 ISC1 ISC0 ISC1 Input s...

Page 102: ...t mode The output latch contents are read by a transfer instruction The output latch contents do not change 2 Input mode The pin status is read by a transfer instruction The output latch contents do not change 4 4 3 Operations on I O port 1 Output mode An operation is performed on the output latch contents and the result is written to the output latch The output latch contents are output from the ...

Page 103: ...MOC and processor clock control register PCC Ring OSC oscillator The Ring OSC oscillator oscillates a clock of 240 kHz TYP Oscillation can be stopped by setting the Ring OSC mode register RCM when Can be stopped by software is set by a mask option and the X1 input clock is used as the CPU clock Subsystem clock oscillator The subsystem clock oscillator oscillates a clock of 32 768 kHz Oscillation c...

Page 104: ...enerator X1 X2 fXP fXT FRC XT1 XT2 fX 22 STOP MSTOP fX 23 fX 24 fX 2 4 RSTOP CSS PCC2 CLS MCM0 MCS CLS MCC OSTS1 OSTS0 OSTS2 1 2 3 MOST 16 MOST 15 MOST 14 MOST 13 MOST 11 C P U fR fX PCC1 PCC0 X1 oscillator Internal bus Ring OSC mode register RCM Main OSC control register MOC Internal bus Ring OSC oscillator Mask option 1 Cannot be stopped 0 Can be stopped CPU clock fCPU Controller Processor clock...

Page 105: ...on stabilization time counter status register OSTC Oscillation stabilization time select register OSTS 1 Processor clock control register PCC The PCC register is used to select the CPU clock the division ratio main system clock oscillator operation stop and whether to use the on chip feedback resistor of the subsystem clock oscillator The PCC is set by a 1 bit or 8 bit memory manipulation instruct...

Page 106: ...e CPU is operating on the subsystem clock MCC should be used to stop the X1 oscillator operation When the CPU is operating on the Ring OSC clock use bit 7 MSTOP of the main OSC control register MOC to stop the X1 oscillator operation this cannot be set by MCC A STOP instruction should not be used 3 The feedback resistor is required to adjust the bias point of the oscillation waveform to close to t...

Page 107: ...2 1 µs Note The main clock mode register MCM is used to set the CPU clock X1 input clock Ring OSC clock see Figure 5 5 2 Ring OSC mode register RCM This register sets the operation mode of Ring OSC This register is valid when Can be stopped by software is set for Ring OSC by a mask option and the X1 input clock or subsystem clock is selected as the CPU clock If Cannot be stopped is selected for Ri...

Page 108: ...ing OSC oscillator output fX is supplied to the peripheral hardware fX 240 kHz TYP Operation of the peripheral hardware with Ring OSC clock cannot be guaranteed Therefore when Ring OSC clock is selected as the clock supplied to the CPU do not use peripheral hardware In addition stop the peripheral hardware before switching the clock supplied to the CPU from the X1 input clock to the Ring OSC clock...

Page 109: ... by a 1 bit or 8 bit memory manipulation instruction RESET input clears this register to 00H Figure 5 6 Format of Main OSC Control Register MOC Address FFA2H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 MOC MSTOP 0 0 0 0 0 0 0 MSTOP Control of X1 oscillator operation 0 X1 oscillator operating 1 X1 oscillator stopped Cautions 1 Make sure that bit 1 MCS of the main clock mode register MCM is 0 before ...

Page 110: ...OP instruction MSTOP 1 and MCC 1 clear OSTC to 00H Figure 5 7 Format of Oscillation Stabilization Time Counter Status Register OSTC Address FFA3H After reset 00H R Symbol 7 6 5 4 3 2 1 0 OSTC 0 0 0 MOST11 MOST13 MOST14 MOST15 MOST16 MOST11 MOST13 MOST14 MOST15 MOST16 Oscillation stabilization time status 1 0 0 0 0 211 fXP min 204 8 µs min 1 1 0 0 0 213 fXP min 819 2 µs min 1 1 1 0 0 214 fXP min 1 ...

Page 111: ...04 8 µs 0 1 0 213 fXP 819 2 µs 0 1 1 214 fXP 1 64 ms 1 0 0 215 fXP 3 27 ms 1 0 1 216 fXP 6 55 ms Other than above Setting prohibited Cautions 1 If the STOP mode is entered and then released while the Ring OSC clock is being used as the CPU clock set the oscillation stabilization time as follows Desired OSTC oscillation stabilization time Oscillation stabilization time set by OSTS The X1 oscillatio...

Page 112: ...ernal Circuit of X1 Oscillator a Crystal ceramic oscillation b External clock IC X1 X2 Crystal resonator or ceramic resonator VSS External clock X1 X2 5 4 2 Subsystem clock oscillator The subsystem clock oscillator oscillates with a crystal resonator Standard 32 768 kHz connected to the XT1 and XT2 pins External clocks can be input to the subsystem clock oscillator when the REGC pin is directly co...

Page 113: ... flows Always make the ground point of the oscillator capacitor the same potential as VSS Do not ground the capacitor to a ground pattern through which a high current flows Do not fetch signals from the oscillator Note that the subsystem clock oscillator is designed as a low amplitude circuit for reducing power consumption Figure 5 11 shows examples of incorrect resonator connection Figure 5 11 Ex...

Page 114: ...D0 High current High current VSS VSS e Signals are fetched IC X2 X1 VSS Remark When using the subsystem clock replace X1 and X2 with XT1 and XT2 respectively Also insert resistors in series on the XT2 side Cautions 2 When X2 and XT1 are wired in parallel the crosstalk noise of X2 may increase with XT1 resulting in malfunctioning To prevent that from occurring it is recommended to wire X2 and XT1 s...

Page 115: ...as the clock to be supplied to the CPU Caution When the Ring OSC clock is selected as the clock supplied to the CPU the prescaler generates various clocks by dividing the Ring OSC oscillator output fX fX 240 kHz TYP 5 5 Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU such as standby mode X1 input clock fXP Ring OSC clock fR S...

Page 116: ...ck and Ring OSC clock is stopped b After RESET release the CPU clock can be switched from the Ring OSC clock to the X1 input clock using bit 0 MCM0 of the main clock mode register MCM after the X1 input clock oscillation stabilization time has elapsed At this time check the oscillation stabilization time using the oscillation stabilization time counter status register OSTC before switching the CPU...

Page 117: ...Status 3 CPU clock fXP fXP Oscillating fR Oscillating Status 1 CPU clock fR fXP Oscillation stopped fR Oscillating Status 2 CPU clock fR fXP Oscillating fR Oscillating HALTNote 4 Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Reset release Interrupt Interrupt HALT instruction STOP instruction STOP instruction STOP instruction STOP instruction RSTOP 0 RSTOP 1Note 1 MCM0 0 MCM0 1Note 2 ...

Page 118: ...tion stopped fR Oscillating oscillation stopped Status 5 CPU clock fXT fXP Oscillating fR Oscillating oscillation stopped Notes 1 When shifting from status 3 to status 4 make sure that bit 1 MCS of the main clock mode register MCM is 1 2 Before shifting from status 2 to status 3 after reset and STOP are released check the X1 input clock oscillation stabilization time status using the oscillation s...

Page 119: ...instruction Reset release Notes 1 Before shifting from status 2 to status 3 after reset and STOP are released check the X1 input clock oscillation stabilization time status using the oscillation stabilization time counter status register OSTC 2 When shifting from status 2 to status 1 make sure that MCS is 0 3 The watchdog timer operates using Ring OSC even in STOP mode if Ring OSC cannot be stoppe...

Page 120: ...lock fXT fXP Oscillating fR Oscillating oscillation stopped Notes 1 Before shifting from status 2 to status 3 after reset and STOP are released check the X1 input clock oscillation stabilization time status using the oscillation stabilization time counter status register OSTC 2 When shifting from status 2 to status 1 make sure that MCS is 0 3 The watchdog timer operates using Ring OSC even in STOP...

Page 121: ...on 4 Operates using the CPU clock at HALT instruction execution Remark RSTOP Bit 0 of the Ring OSC mode register RCM MCM0 Bit 0 of the main clock mode register MCM Table 5 4 Oscillation Control Flags and Clock Oscillation Status X1 Oscillator Ring OSC Oscillator RSTOP 0 Stopped Oscillating MSTOP 1Note RSTOP 1 Setting prohibited RSTOP 0 Oscillating MSTOP 0Note RSTOP 1 Oscillating Stopped RSTOP 0 Os...

Page 122: ...ration is performed using either the Ring OSC clock or X1 input clock To stop the clock wait for the number of clocks shown in Table 5 5 before stopping Table 5 5 Time Required to Switch Between Ring OSC Clock and X1 Input Clock PCC Time Required for Switching PCC2 PCC1 PCC0 X1 Ring OSC Ring OSC X1 0 0 0 fXP fR 1 clock 0 0 1 fXP 2fR 1 clock 0 1 0 fXP 4fR 1 clock 0 1 1 fXP 8fR 1 clock 1 0 0 fXP 16f...

Page 123: ...C0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 1 0 0 0 16 clocks 16 clocks 16 clocks 16 clocks fXP fXT clocks 306 clocks 0 0 1 8 clocks 8 clocks 8 clocks 8 clocks fXP 2fXT clocks 153 clocks 0 1 0 4 clocks 4 clocks 4 clocks 4 clocks fXP 4fXT clocks 77 clocks 0 1 1 2 clocks 2 clocks 2 clocks 2 clocks fXP 8fXT clocks 39 clocks 0 1 0 0 1 clock 1 clo...

Page 124: ...illation stabilization time has elapsed X1 oscillation stabilization time has not elapsed PCC 00H RCM 00H MCM 00H MOC 00H OSTC 00H OSTS 05HNote OSTC checkNote Each processing After reset release PCC setting MCM 0 1 X1 input clock operation Ring OSC clock operation dividing set PCC Register initial value after reset Ring OSC clock operation X1 input clock operation Note Check the oscillation stabil...

Page 125: ...0 Ring OSC clock operation Ring OSC oscillating Ring OSC clock operation X1 oscillation X1 input clock or Ring OSC clock X1 input clock operation No RSTOP 0 Yes RSTOP 1 PCC 7 MCC 0 PCC 4 CSS 0 MCM 03H RCM 0Note RSTOP 1 RSTOP 0 MCM0 0 Register setting in X1 input clock operation X1 input clock operation Ring OSC clock operation Note Required only when clock can be stopped by software is selected fo...

Page 126: ...ng from X1 Input Clock to Subsystem Clock Flowchart MCS 1 not changed CLS is changed from 0 to 1 Subsystem clock operation Subsystem clock operation X1 oscillation X1 input clock or Ring OSC clock X1 input clock operation PCC 7 MCC 0 PCC 4 CSS 0 MCM 03H CSS 1 Register setting in X1 input clock operation X1 input clock operation Subsystem clock ...

Page 127: ...eration X1 oscillating X1 oscillation enabled Wait for X1 oscillation stabilization time X1 input clock operation CLS is changed from 1 to 0 MCS 1 not changed X1 oscillation stabilization time elapsed X1 oscillation stabilization time not elapsed Yes X1 oscillation stopped No X1 oscillating MCC 0 PCC 4 CSS 1 MCM 03H MCC 1 OSTC check CSS 0 X1 input clock operation Subsystem clock operation X1 input...

Page 128: ...C stopped 1 1 1Note 5 0Note 6 1 1 1 Notes 1 Valid only when clock can be stopped by software is selected for Ring OSC by a mask option 2 Do not set MCC 1 or MSTOP 1 during X1 input clock operation even if MCC 1 or MSTOP 1 is set the X1 oscillation does not stop 3 Do not set MCC 1 during Ring OSC operation even if MCC 1 is set the X1 oscillation does not stop To stop X1 oscillation during Ring OSC ...

Page 129: ... interval 2 PPG output 16 bit timer event counter 00 can output a rectangular wave whose frequency and output pulse width can be set freely 3 Pulse width measurement 16 bit timer event counter 00 can measure the pulse width of an externally input signal 4 External event counter 16 bit timer event counter 00 can measure the number of pulses of an externally input signal 5 Square wave output 16 bit ...

Page 130: ...0 Note Note See Figure 4 2 Block Diagram of P00 and P03 and Figure 4 3 Block Diagram of P01 Figure 6 1 shows the block diagram Figure 6 1 Block Diagram of 16 Bit Timer Event Counter 00 Internal bus Capture compare control register 00 CRC00 TI010 TO00 P01 fX fX 22 fX 28 fX TI000 P00 Prescaler mode register 00 PRM00 2 PRM001 PRM000 CRC002 16 bit timer capture compare register 010 CR010 Match Match 1...

Page 131: ...rupt request INTTM000 is generated if they match It can also be used as the register that holds the interval time when TM00 is set to interval timer operation When CR000 is used as a capture register It is possible to select the valid edge of the TI000 pin or the TI010 pin as the capture trigger The TI000 or TI010 valid edge is set using prescaler mode register 00 PRM00 If the capture trigger is s...

Page 132: ...peration 3 16 bit timer capture compare register 010 CR010 CR010 is a 16 bit register that has the functions of both a capture register and a compare register Whether it is used as a capture register or a compare register is set by bit 2 CRC002 of capture compare control register 00 CRC00 When CR010 is used as a compare register The value set in the CR010 is constantly compared with the 16 bit tim...

Page 133: ...C00 Prescaler mode register 00 PRM00 Port mode register 0 PM0 1 16 bit timer mode control register 00 TMC00 This register sets the 16 bit timer operating mode the 16 bit timer counter 00 TM00 clear mode and output timing and detects an overflow TMC00 can be set by a 1 bit or 8 bit memory manipulation instruction RESET input clears TMC00 to 00H Caution 16 bit timer counter 00 TM00 starts operation ...

Page 134: ...10 1 1 1 Match between TM00 and CR000 match between TM00 and CR010 or TI000 valid edge Generated on match between TM00 and CR000 or match between TM00 and CR010 OVF00 16 bit timer counter 00 TM00 overflow detection 0 Overflow not detected 1 Overflow detected Cautions 1 Timer operation must be stopped before writing to bits other than the OVF00 flag 2 Set the valid edge of the TI000 P00 pin using p...

Page 135: ... compare register 1 Operates as capture register Cautions 1 Timer operation must be stopped before setting CRC00 2 When the mode in which clear start occurs on a match between TM00 and CR000 is selected with 16 bit timer mode control register 00 TMC00 CR000 should not be specified as a capture register 3 To ensure that the capture operation is performed properly the capture trigger requires a puls...

Page 136: ... 1 1 1 Setting prohibited TOC001 Timer output F F control using match of CR000 and TM00 0 Disables inversion operation 1 Enables inversion operation TOE00 16 bit timer event counter 00 output control 0 Disables output output fixed to level 0 1 Enables output Note The one shot pulse output mode operates correctly only in the free running mode and the mode in which clear start occurs at the TI000 va...

Page 137: ... The external clock requires a pulse two times longer than internal clock fX Cautions 1 If the valid edge of TI000 is to be set for the count clock do not set the clear start mode using the valid edge of TI000 and the capture trigger 2 Always set data to PRM00 after stopping the timer operation 3 If the TI000 or TI010 pin is high level immediately after system reset the rising edge is immediately ...

Page 138: ... pin for timer output set PM01 and the output latch of P01 to 0 PM0 can be set by a 1 bit or 8 bit memory manipulation instruction RESET input sets PM0 to FFH Figure 6 6 Format of Port Mode Register 0 PM0 7 1 6 1 5 1 4 1 3 PM03 2 PM02 1 PM01 0 PM00 Symbol PM0 Address FF20H After reset FFH R W PM0n 0 1 P0n pin I O mode selection n 0 to 3 Output mode output buffer on Input mode output buffer off ...

Page 139: ... INTTM000 is generated The count clock of the 16 bit timer event counter 00 can be selected with bits 0 and 1 PRM000 PRM001 of prescaler mode register 00 PRM00 See 6 5 Cautions for 16 Bit Timer Event Counter 00 2 16 bit timer capture compare register setting for details of the operation when the compare register value is changed during timer count operation Figure 6 7 Control Register Settings for...

Page 140: ...nter 00 TM00 OVF00 Clear circuit INTTM000 fX fX 22 fX 28 TI000 P00 Selector Noise eliminator fX Figure 6 9 Timing of Interval Timer Operation Count clock t TM00 count value CR000 INTTM000 TO00 0000H 0001H N 0000H 0001H N 0000H 0001H N N N N N Count start Clear Clear Interrupt acknowledged Interrupt acknowledged Interval time Interval time Interval time Remark Interval time N 1 t N 0001H to FFFFH ...

Page 141: ...timer mode control register 00 TMC00 0 0 0 0 TMC003 1 TMC002 1 TMC001 0 OVF00 0 TMC00 Clears and starts on match between TM00 and CR000 b Capture compare control register 00 CRC00 0 0 0 0 0 CRC002 0 CRC001 CRC000 0 CRC00 CR000 used as compare register CR010 used as compare register c 16 bit timer output control register 00 TOC00 0 OSPT00 0 OSPE00 0 TOC004 1 LVS00 0 1 LVR00 0 1 TOC001 1 TOE00 1 TOC...

Page 142: ...width M 1 t 1 cycle N 1 t N CR000 capture value CR010 capture value M M N 1 N Clear Count start Caution CR000 cannot be rewritten during TM00 operation Remarks 1 0000H M N FFFFH 2 In the PPG output operation change the pulse width rewrite CR010 during TM00 operation using the following procedure 1 Disable the timer output inversion operation by match of TM00 and CR010 TOC004 0 2 Disable the INTTM0...

Page 143: ...it timer capture compare register 010 CR010 and an external interrupt request signal INTTM010 is set Any of three edges rising falling or both edges can be selected using bits 4 and 5 ES000 and ES001 of PRM00 For valid edge detection sampling is performed using the count clock selected by PRM00 and a capture operation is only performed when a valid level is detected twice thus eliminating noise wi...

Page 144: ...r counter 00 TM00 OVF00 16 bit timer capture compare register 010 CR010 Internal bus INTTM010 Selector Figure 6 15 Timing of Pulse Width Measurement Operation with Free Running Counter and One Capture Register with Both Edges Specified t 0000H 0000H FFFFH 0001H D0 D0 Count clock TM00 count value TI000 pin input CR010 capture value INTTM010 OVF00 D1 D0 t D3 D2 t 10000H D1 D2 t D1 D2 D3 D2 D3 D0 1 D...

Page 145: ...Any of three edges rising falling or both edges can be selected as the valid edge of the TI000 pin and the TI010 pin specified using bits 4 and 5 ES000 and ES001 and bits 6 and 7 ES100 and ES101 of PRM00 respectively For valid edge detection of the TI000 and TI010 pins sampling is performed at the interval selected by prescaler mode register 00 PRM00 and a capture operation is only performed when ...

Page 146: ...ge Specified Count clock TM00 TI000 Rising edge detection CR010 INTTM010 N 3 N 2 N 1 N N 1 N Figure 6 18 Timing of Pulse Width Measurement Operation with Free Running Counter with Both Edges Specified t 0000H 0000H FFFFH 0001H D0 D0 TI010 pin input CR000 capture value INTTM010 INTTM000 OVF00 D1 D0 t D3 D2 t 10000H D1 D2 t 10000H D1 D2 1 t D1 D2 1 D1 D2 D2 D3 D0 1 D1 D1 1 D2 1 D2 2 Count clock TM00...

Page 147: ...lected as the valid edge of the TI000 pin specified using bits 4 and 5 ES000 and ES001 of prescaler mode register 00 PRM00 For TI000 pin valid edge detection sampling is performed at the interval selected by prescaler mode register 00 PRM00 and a capture operation is only performed when a valid level is detected twice thus eliminating noise with a short pulse width Figure 6 19 Control Register Set...

Page 148: ...Pulse Width Measurement Operation with Free Running Counter and Two Capture Registers with Rising Edge Specified t 0000H 0000H FFFFH 0001H D0 D0 INTTM010 OVF00 D2 D1 D3 D2 D3 D0 1 D2 1 D1 D1 1 CR000 capture value Count clock TM00 count value TI000 pin input CR010 capture value D1 D0 t D3 D2 t 10000H D1 D2 t ...

Page 149: ...ormed when a valid level is detected twice thus eliminating noise with a short pulse width Figure 6 21 Control Register Settings for Pulse Width Measurement by Means of Restart a 16 bit timer mode control register 00 TMC00 0 0 0 0 TMC003 1 TMC002 0 TMC001 0 1 OVF00 0 TMC00 Clears and starts at valid edge of TI000 pin b Capture compare control register 00 CRC00 0 0 0 0 0 CRC002 1 CRC001 1 CRC000 1 ...

Page 150: ...ot be carried out Any of three edges rising falling or both edges can be selected using bits 4 and 5 ES000 and ES001 of prescaler mode register 00 PRM00 Because operation is carried out only after the valid edge is detected twice by sampling using the internal clock fX noise with short pulse widths can be eliminated Figure 6 23 Control Register Settings in External Event Counter Mode a 16 bit time...

Page 151: ... fX 22 fX 28 fX Noise eliminator fX Valid edge of TI000 16 bit timer counter 00 TM00 16 bit timer capture compare register 010 CR010 Selector Noise eliminator Figure 6 25 External Event Counter Operation Timing with Rising Edge Specified TI000 pin input TM00 count value CR000 INTTM000 0000H 0001H 0002H 0003H 0004H 0005H N 1 N 0000H 0001H 0002H 0003H N Caution When reading the external event counte...

Page 152: ... 0 TMC003 1 TMC002 1 TMC001 0 OVF00 0 TMC00 Clears and starts on match between TM00 and CR000 b Capture compare control register 00 CRC00 0 0 0 0 0 CRC002 0 1 CRC001 0 1 CRC000 0 CRC00 CR000 used as compare register c 16 bit timer output control register 00 TOC00 0 OSPT00 0 OSPE00 0 TOC004 0 LVS00 0 1 LVR00 0 1 TOC001 1 TOE00 1 TOC00 Enables TO00 output Inverts output on match between TM00 and CR0...

Page 153: ...at the output becomes inactive at the count value M set in advance to 16 bit timer capture compare register 000 CR000 Note Even after the one shot pulse has been output the TM00 register continues its operation To stop the TM00 register the TMC003 and TMC002 bits of the TMC00 register must be set to 00 Note The case where N M is described here When N M the output becomes active with the CR000 regi...

Page 154: ...are register CR010 as compare register 0 0 1 0 c 16 bit timer output control register 00 TOC00 0 0 1 1 0 1 TOC00 LVR00 LVS00 TOC004 OSPE00 OSPT00 TOC001 TOE00 Enables TO00 output Inverts output upon match between TM00 and CR000 Specifies initial value of TO00 output F F Inverts output upon match between TM00 and CR010 Sets one shot pulse output mode Set to 1 for output 0 1 1 1 Caution Do not set 0...

Page 155: ...t timer output control register 00 TOC00 as shown in Figure 6 30 and by using the valid edge of the TI000 pin as an external trigger The valid edge of the TI000 pin is specified by bits 4 and 5 ES000 ES001 of prescaler mode register 00 PRM00 The rising falling or both the rising and falling edges can be specified When the valid edge of the TI000 pin is detected the 16 bit timer event counter is cl...

Page 156: ...RC000 CR000 used as compare register CR010 used as compare register 0 0 1 0 c 16 bit timer output control register 00 TOC00 0 0 1 1 0 1 TOC00 LVR00 TOC001 TOE00 OSPE00 OSPT00 TOC004 LVS00 Enables TO00 output Inverts output upon match between TM00 and CR000 Specifies initial value of TO00 output F F Inverts output upon match between TM00 and CR010 Sets one shot pulse output mode 0 1 1 1 Caution Do ...

Page 157: ... Edge Specified 0000H N N N N N M M M M M N 1 N 2 M 1 M 2 M 2 M 1 0001H 0000H Count clock TM00 count value CR010 set value CR000 set value TI000 pin input INTTM010 INTTM000 TO00 pin output Set TMC00 to 08H TM00 count starts Caution 16 bit timer counter 00 starts operating as soon as a value other than 00 operation stop mode is set to the TMC002 and TMC003 bits Remark N M ...

Page 158: ...M00 and CR000 Set 16 bit timer capture compare registers 000 010 CR000 CR010 to other than 0000H This means a 1 pulse count operation cannot be performed when 16 bit timer event counter 00 is used as an event counter 3 Operation after compare register change during timer count operation If the value after 16 bit timer capture compare register 000 CR000 is changed is smaller than that of 16 bit tim...

Page 159: ...pectively and then stopping timer operation The valid edge is set using bits 4 and 5 ES000 and ES001 of prescaler mode register 00 PRM00 6 Re triggering one shot pulse a One shot pulse output by software When a one shot pulse is output do not set the OSPT00 bit to 1 Do not output the one shot pulse again until INTTM000 which occurs upon a match with the CR000 register or INTTM010 which occurs upon...

Page 160: ...re set newly and clear is disabled 8 Conflicting operations Conflict between the read period of the 16 bit timer capture compare register CR000 CR010 and capture trigger input CR000 CR010 used as capture register Capture trigger input has priority The data read from CR000 CR010 is undefined 9 Timer operation 1 Even if 16 bit timer counter 00 TM00 is read the value is not captured by 16 bit timer c...

Page 161: ...r larger than the timer value 2 A capture operation may not be performed for CR000 CR010 set in compare mode even if a capture trigger has been input 12 Edge detection 1 If the TI000 or TI010 pin is high level immediately after system reset and the rising edge or both the rising and falling edges are specified as the valid edge of the TI000 or TI010 pin to enable the 16 bit timer counter 00 TM00 o...

Page 162: ... block diagrams of 8 bit timer event counters 50 and 51 Figure 7 1 Block Diagram of 8 Bit Timer Event Counter 50 Internal bus 8 bit timer compare register 50 CR50 TI50 TO50 P17 fX 22 fX 26 fX 28 fX 213 fX fX 2 Match Mask circuit OVF Clear 3 Selector TCL502 TCL501 TCL500 Timer clock selection register 50 TCL50 Internal bus TCE50 TMC506 LVS50 LVR50 TMC501 TOE50 Invert level 8 bit timer mode control ...

Page 163: ...are register 51 CR51 TI51 TO51 P33 INTP4 fX 24 fX 26 fX 28 fX 212 fX fX 2 Match Mask circuit OVF Clear 3 Selector TCL512 TCL511 TCL510 Timer clock selection register 51 TCL51 Internal bus TCE51 TMC516 LVS51 LVR51 TMC511 TOE51 Invert level 8 bit timer mode control register 51 TMC51 S R S Q R INV Selector INTTM51 TO51 TI51 P33 INTP4 Selector 8 bit timer counter 51 TM51 Selector ...

Page 164: ...ck When the count value is read during operation count clock input is temporary stopped and then the count value is read In the following situations the count value is cleared to 00H 1 RESET input 2 When TCE5n is cleared 3 When TM5n and CR5n match in the mode in which clear start occurs upon a match of the TM5n and CR5n 2 8 bit timer compare register 5n CR5n CR5n can be read and written by an 8 bi...

Page 165: ...of TI5n input TCL5n can be set by an 8 bit memory manipulation instruction RESET input clears TCL5n to 00H Remark n 0 1 Figure 7 3 Format of Timer Clock Selection Register 50 TCL50 Address FF6AH After reset 00H R W Symbol 7 6 5 4 3 2 1 0 TCL50 0 0 0 0 0 TCL502 TCL501 TCL500 TCL502 TCL501 TCL500 Count clock selection 0 0 0 TI50 falling edge 0 0 1 TI50 rising edge 0 1 0 fX 10 MHz 0 1 1 fX 2 5 MHz 1 ...

Page 166: ... TCL510 TCL512 TCL511 TCL510 Count clock selection 0 0 0 TI51 falling edge 0 0 1 TI51 rising edge 0 1 0 fX 10 MHz 0 1 1 fX 2 5 MHz 1 0 0 fX 24 625 kHz 1 0 1 fX 26 156 25 kHz 1 1 0 fX 28 39 06 kHz 1 1 1 fX 212 2 44 kHz Cautions 1 When rewriting TCL51 to other data stop the timer operation beforehand 2 Be sure to set bits 3 to 7 to 0 Remarks 1 fX X1 input clock oscillation frequency 2 Figures in par...

Page 167: ...s FF6BH After reset 00H R WNote Symbol 7 6 5 4 3 2 1 0 TMC50 TCE50 TMC506 0 0 LVS50 LVR50 TMC501 TOE50 TCE50 TM50 count operation control 0 After clearing to 0 count operation disabled counter stopped 1 Count operation start TMC506 TM50 operating mode selection 0 Mode in which clear start occurs on a match between TM50 and CR50 1 PWM free running mode LVS50 LVR50 Timer output F F status setting 0 ...

Page 168: ...perating mode selection 0 Mode in which clear start occurs on a match between TM51 and CR51 1 PWM free running mode LVS51 LVR51 Timer output F F status setting 0 0 No change 0 1 Timer output F F reset 0 1 0 Timer output F F set 1 1 1 Setting prohibited In other modes TMC516 0 In PWM mode TMC516 1 TMC511 Timer F F control Active level selection 0 Inversion operation disabled Active high 1 Inversion...

Page 169: ... 0 Mask clear TCE5n 1 Timer start 2 The settings of LVS5n and LVR5n are valid in other than PWM mode 3 Do not rewrite TMC5n1 and TOE5n simultaneously 4 When switching to the PWM mode do not rewrite TM5n6 and LVS5n or LVR5n simultaneously 5 To rewrite TMC5n6 stop operation beforehand Remarks 1 In PWM mode PWM output is made inactive by setting TCE5n to 0 2 If LVS5n and LVR5n are read after data is ...

Page 170: ...1 bit or 8 bit memory manipulation instruction RESET input sets these registers to FFH Figure 7 7 Format of Port Mode Register 1 PM1 Address FF21H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 PM1n P1n pin I O mode selection n 0 to 7 0 Output mode output buffer on 1 Input mode output buffer off Figure 7 8 Format of Port Mode Register 3 PM3 Address FF23H Aft...

Page 171: ...k selection register 5n TCL5n Setting 1 Set the registers TCL5n Select the count clock CR5n Compare value TMC5n Stop the count operation select the mode in which clear start occurs on a match of TM5n and CR5n TMC5n 0000 0B Don t care 2 After TCE5n 1 is set the count operation starts 3 If the values of TM5n and CR5n match INTTM5n is generated TM5n is cleared to 00H 4 INTTM5n is generated repeatedly...

Page 172: ...re 7 9 Interval Timer Operation Timing 2 2 b When CR5n 00H t Count clock TM5n CR5n TCE5n INTTM5n TO5n Interval time 00H 00H 00H 00H 00H c When CR5n FFH t Count clock TM5n CR5n TCE5n INTTM5n TO5n 01 FE FF 00 FE FF 00 FF FF FF Interval time Interrupt acknowledged Interrupt acknowledged Remark n 0 1 ...

Page 173: ...ches the value of CR5n INTTM5n is generated Setting 1 Set each register TCL5n Select TI5n input edge TI5n falling edge TCL5n 00H TI5n rising edge TCL5n 01H CR5n Compare value TMC5n Stop the count operation select the mode in which clear start occurs on match of TM5n and CR5n disable the timer F F inversion operation disable timer output TMC5n 0000 00B Don t care 2 When TCE5n 1 is set the number of...

Page 174: ...e count clock CR5n Compare value TMC5n Stop the count operation select the mode in which clear start occurs on a match of TM5n and CR5n LVS5n LVR5n Timer Output F F Status Setting 1 0 High level output 0 1 Low level output Timer output F F inversion enabled Timer output enabled TMC5n 00001011B or 00000111B 2 After TCE5n 1 is set the count operation starts 3 The timer output F F is inverted by a ma...

Page 175: ...5EJ1V0UD 175 Figure 7 11 Square Wave Output Operation Timing Count clock TMn count value CR5n TO5nNote Count start 00H 01H 02H N 1 N 00H 01H 02H N 1 N 00H N Note The initial value of TO5n output can be set by bits 2 and 3 LVR5n LVS5n of 8 bit timer mode control register 5n TMC5n ...

Page 176: ... latches P17 P33 Note and port mode registers PM17 PM33 Note to 0 TCL5n Select the count clock CR5n Compare value TMC5n Stop the count operation select PWM mode The timer output F F is not changed TMC5n1 Active Level Selection 0 Active high 1 Active low Timer output enabled TMC5n 01000001B or 01000011B 2 The count operation starts when TCE5n 1 Set TCE5n to 0 to stop the count operation Note 8 bit ...

Page 177: ...FFH 00H 01H 02H N N 1 FFH 00H 01H 02H M 00H N Active level Active level Inactive level b CR5n 00H Count clock TM5n CR5n TCE5n INTTM5n TO5n L Inactive level Inactive level 01H 00H FFH 00H 01H 02H N N 1 FFH 00H 01H 02H M 00H 00H N 2 c CR5n FFH TM5n CR5n TCE5n INTTM5n TO5n 01H 00H FFH 00H 01H 02H N N 1 FFH 00H 01H 02H M 00H FFH N 2 Inactive level Active level Inactive level Active level Inactive leve...

Page 178: ...ed to CR5n at second overflow Count clock TM5n CR5n TCE5n INTTM5n TO5n N N 1 N 2 FFH 00H 01H N N 1 N 2 FFH 00H 01H 02H N 02H N H M M M 1 M 2 1 CR5n change N M 2 Caution When reading from CR5n between 1 and 2 in Figure 7 13 the value read differs from the actual value read value M actual value of CR5n N 7 5 Cautions for 8 Bit Timer Event Counters 50 and 51 1 Timer start error An error of up to one ...

Page 179: ...ation of 8 Bit Timers H0 and H1 8 bit timers H0 and H1 consist of the following hardware Table 8 1 Configuration of 8 Bit Timers H0 and H1 Item Configuration Timer register 8 bit timer counter Hn TMHn Registers 8 bit timer H compare register 0n CMP0n 8 bit timer H compare register 1n CMP1n Timer output Two outputs TOHn Control registers 8 bit timer H mode register n TMHMDn 8 bit timer H carrier co...

Page 180: ...r H enable signal Clear 3 2 8 bit timer H compare register 00 CMP00 Selector Figure 8 2 Block Diagram of 8 Bit Timer H1 TMHE1 CKS12 CKS11 CKS10 TMMD11TMMD10 TOLEV1 TOEN1 TOH1 INTP5 P16 8 bit timer H carrier control register 1 TMCYC1 INTTMH1 INTTM51 fX fX 22 fX 24 fX 26 fX 212 fR 27 1 0 F F R 3 2 RMC1 NRZB1 NRZ1 Match 8 bit timer H mode control register 1 TMHMD1 8 bit timer H compare register 11 CM...

Page 181: ...can be rewritten during timer count operation In the carrier generator mode an interrupt request signal INTTMHn is generated if the values of the timer counter and CMP1n register match after setting the CMP1n register The timer counter value is cleared at the same time If the CMP1n register value is rewritten during timer operation reloading is performed at the timing at which the counter value an...

Page 182: ...olled by 8 bit timer H mode registers 0 and 1 TMHMD0 TMHMD1 and 8 bit timer H carrier control register 1 TMCYC1 Note Note 8 bit timer H1 only 1 8 bit timer H mode registers 0 and 1 TMHMD0 TMHMD1 These registers control the mode of timer H These registers can be set by a 1 bit or 8 bit memory manipulation instruction RESET input clears these registers to 00H ...

Page 183: ...than above Interval timer mode PWM pulse generator mode Setting prohibited TMMD01 0 1 TMMD00 0 0 Timer operation mode Low level High level TOLEV0 0 1 Timer output level control in default mode Disables output Enables output TOEN0 0 1 Timer output control Other than above 7 6 5 4 3 2 1 0 Cautions 1 When TMHE0 1 setting the other bits of the TMHMD0 register is prohibited 2 In the PWM pulse generator...

Page 184: ... 0 Timer operation mode Low level High level TOLEV1 0 1 Timer output level control in default mode Disables output Enables output TOEN1 0 1 Timer output control Other than above 7 6 5 4 3 2 1 0 Cautions 1 When TMHE1 1 setting the other bits of the TMHMD1 register is prohibited 2 In the PWM pulse generator mode and carrier generator mode be sure to set 8 bit timer H compare register 11 CMP11 when s...

Page 185: ... input clears this register to 00H Figure 8 5 Format of 8 Bit Timer H Carrier Control Register 1 TMCYC1 7 0 TMCYC1 6 0 5 0 4 0 3 0 2 RMC1 1 NRZB1 0 NRZ1 Address FF6DH After reset 00H R WNote Low level output High level output Low level output Carrier pulse output RMC1 0 0 1 1 NRZB1 0 1 0 1 Remote control output Carrier output disabled status low level status Carrier output enabled status RMC1 1 Ca...

Page 186: ...gnal repeatedly at the same interval 1 Set each register Figure 8 6 Register Setting in Interval Timer Mode i Setting timer H mode register n TMHMDn 0 0 1 0 1 0 1 0 0 0 1 0 1 TMMDn0 TOLEVn TOENn CKSn1 CKSn2 TMHEn TMHMDn CKSn0 TMMDn1 Timer output setting Timer output level inversion setting Interval timer mode setting Count clock fCNT selection Count operation stopped ii CMP0n register setting Comp...

Page 187: ...clear 2 Level inversion match interrupt occurrence 8 bit timer counter Hn clear 3 1 1 The count operation is enabled by setting the TMHEn bit to 1 The count clock starts counting no more than 1 clock after the operation is enabled 2 When the values of 8 bit timer counter Hn and the CMP0n register match the value of 8 bit timer counter Hn is cleared the TOHn output level is inverted and the INTTMHn...

Page 188: ...er Operation 2 2 b Operation when CMP0n FFH 00H Count clock Count start 8 bit timer counter Hn CMP0n TMHEn INTTMHn TOHn 01H FEH Clear Clear FFH 00H FEH FFH 00H FFH Interval time c Operation when CMP0n 00H Count clock Count start 8 bit timer counter Hn CMP0n TMHEn INTTMHn TOHn 00H 00H Interval time Remark n 0 1 ...

Page 189: ...bitrary duty and arbitrary cycle can be set is output 1 Set each register Figure 8 8 Register Setting in PWM Pulse Generator Mode i Setting timer H mode register n TMHMDn 0 0 1 0 1 0 1 1 0 0 1 1 TMMDn0 TOLEVn TOENn CKSn1 CKSn2 TMHEn TMHMDn CKSn0 TMMDn1 Timer output enabled Timer output level inversion setting PWM mode selection Count clock fCNT selection Count operation stopped ii Setting CMP0n re...

Page 190: ...ount operation set TMHEn 0 If the setting value of the CMP0n register is N the setting value of the CMP1n register is M and the count clock frequency is fCNT the PWM pulse output cycle and duty ratio are as follows PWM pulse output cycle N 1 fCNT Duty ratio Inactive width Active width M 1 N M Cautions 1 In PWM mode three operation clocks signal selected using the CKSn2 to CKSn0 bits of the TMHMDn ...

Page 191: ... A5H 01H 1 2 3 4 1 The count operation is enabled by setting the TMHEn bit to 1 Start 8 bit timer counter Hn by masking one count clock to count up At this time TOHn output remains inactive when TOLEVn 0 2 When the values of 8 bit timer counter Hn and the CMP0n register match the TOHn output level is inverted the value of 8 bit timer counter Hn is cleared and the INTTMHn signal is output 3 When th...

Page 192: ...tion when CMP0n FFH CMP1n 00H Count clock 8 bit timer counter Hn CMP0n TMHEn INTTMHn TOHn TOLEVn 0 00H 01H FFH 00H 01H 02H FFH 00H FFH 00H 01H 02H CMP1n FFH 00H c Operation when CMP0n FFH CMP1n FEH Count clock 8 bit timer counter Hn CMP0n TMHEn INTTMHn TOHn TOLEVn 0 00H 01H FEH FFH 00H 01H FEH FFH 00H 01H FEH FFH 00H CMP1n FFH FEH Remark n 0 1 ...

Page 193: ...Manual U16315EJ1V0UD 193 Figure 8 9 Operation Timing in PWM Pulse Generator Mode 3 4 d Operation when CMP0n 01H CMP1n 00H Count clock 8 bit timer counter Hn CMP0n TMHEn INTTMHn TOHn TOLEVn 0 01H 00H 01H 00H 01H 00H 00H 01H 00H 01H CMP1n 00H Remark n 0 1 ...

Page 194: ... 8 bit timer counter Hn is cleared the TOHn output becomes active and the INTTMHn signal is output 4 If the CMP1n register value is changed the value is latched and not transferred to the register When the values of 8 bit timer counter Hn and the CMP1n register before the change match the value is transferred to the CMP1n register and the CMP1n register value is changed 2 However three count clock...

Page 195: ... counter 51 Prescaler CPU INTC INTTM51 INTTM51 INTTM5H1 INTTMH1 8 bit timer H1 TO51 TOH1 Selector TMMD10 TMMD11 1 Carrier generation In carrier generator mode 8 bit timer H compare register 01 CMP01 generates a low level width carrier pulse waveform and 8 bit timer H compare register 11 CMP11 generates a high level width carrier pulse waveform Rewriting the CMP11 register during 8 bit timer H1 ope...

Page 196: ...n below Figure 8 11 Transfer Timing 8 bit timer H1 count clock TMHE1 INTTM51 INTTM5H1 NRZ1 NRZB1 RMC1 1 1 1 0 0 0 1 Note 2 1 The INTTM51 signal is synchronized with the count clock of 8 bit timer H1 and is output as the INTTM5H1 signal 2 The value of the NRZB1 bit is transferred to the NRZ1 bit at the second clock from the rising edge of the INTTM5H1 signal Note When 8 bit timer event counter 51 i...

Page 197: ... operation is enabled the first compare register to be compared is the CMP01 register When the count value of 8 bit timer counter H1 and the CMP01 register value match the INTTMH1 signal is generated 8 bit timer counter H1 is cleared and at the same time the compare register to be compared with 8 bit timer counter H1 is switched from the CMP01 register to the CMP11 register 5 When the count value ...

Page 198: ...mer count operation was stopped TMHE1 0 be sure to set again even if setting the same value to the CMP11 register 2 Set so that the count clock frequency of TMH1 becomes more than 6 times the count clock frequency of TM51 4 Timing chart The carrier output control timing is shown below Cautions 1 Set the values of the CMP01 and CMP11 registers in a range of 01H to FFH 2 In the carrier generator mod...

Page 199: ...rst INTTMH1 signal is generated the carrier clock signal is inverted and the compare register to be compared with 8 bit timer counter H1 is switched from the CMP01 register to the CMP11 register 8 bit timer counter H1 is cleared to 00H 4 When the count value of 8 bit timer counter H1 matches the CMP11 register value the INTTMH1 signal is generated the carrier clock signal is inverted and the compa...

Page 200: ...rted and the compare register to be compared with 8 bit timer counter H1 is switched from the CMP01 register to the CMP11 register 8 bit timer counter H1 is cleared to 00H 4 When the count value of 8 bit timer counter H1 matches the CMP11 register value the INTTMH1 signal is generated the carrier clock signal is inverted and the compare register to be compared with 8 bit timer counter H1 is switch...

Page 201: ...1 matches the CMP01 register value 8 bit timer counter H1 is cleared and the INTTMH1 signal is output 3 The CMP11 register can be rewritten during 8 bit timer H1 operation however the changed value L is latched The CMP11 register is changed when the count value of 8 bit timer counter H1 and the CMP11 register value before the change M match 3 4 When the count value of 8 bit timer counter H1 and th...

Page 202: ...1 shows the watch timer block diagram Figure 9 1 Watch Timer Block Diagram fX 27 fW 24 fW 25 fW 26 fW 27 fW 28 fW 210 fW 211 fW 29 fXT INTWT INTWTI WTM0 WTM1 WTM2 WTM3 WTM4 WTM5 WTM6 WTM7 fW Clear 11 bit prescaler Clear 5 bit counter Watch timer operation mode register WTM Internal bus Selector Selector Selector Selector Remark fX X1 input clock oscillation frequency fXT Subsystem clock oscillatio...

Page 203: ...X1 input clock oscillation frequency fXT Subsystem clock oscillation frequency fW Watch timer clock frequency 2 Interval timer Interrupt requests INTWTI are generated at preset time intervals Table 9 2 Interval Timer Interval Time Interval Time When Operated at fXT 32 768 kHz When Operated at fX 10 MHz 24 fW 488 µs 205 µs 25 fW 977 µs 410 µs 26 fW 1 95 ms 820 µs 27 fW 3 91 ms 1 64 ms 28 fW 7 81 ms...

Page 204: ... 1 Control register Watch timer operation mode register WTM 9 3 Register Controlling Watch Timer The watch timer is controlled by the watch timer operation mode register WTM Watch timer operation mode register WTM This register sets the watch timer count clock enables disables operation prescaler interval time and 5 bit counter operation control WTM is set by a 1 bit or 8 bit memory manipulation i...

Page 205: ...fW 1 1 0 210 fW 1 1 1 211 fW WTM3 WTM2 Interrupt time selection 0 0 214 fW 0 1 213 fW 1 0 25 fW 1 1 24 fW WTM1 5 bit counter operation control 0 Clear after operation stop 1 Start WTM0 Watch timer operation enable 0 Operation stop clear both prescaler and timer 1 Operation enable Caution Do not change the count clock and interval time by setting bits 4 to 7 WTM4 to WTM7 of WTM during watch timer o...

Page 206: ...taneously operated zero second start can be achieved only for the watch timer by setting WTM1 to 0 In this case however the 11 bit prescaler is not cleared Therefore an error up to 2 11 1 fW seconds occurs in the first overflow INTWT after zero second start The interrupt request is generated at the following time intervals Table 9 4 Watch Timer Interrupt Time WTM3 WTM2 Interrupt Time Selection Whe...

Page 207: ... is set to 1 the count operation starts When this bit is set to 0 the count operation stops Table 9 5 Interval Timer Interval Time WTM6 WTM5 WTM4 Interval Time When Operated at fXT 32 768 kHz WTM7 1 When Operated at fX 10 MHz WTM7 0 0 0 0 24 fW 488 µs 205 µs 0 0 1 25 fW 977 µs 410 µs 0 1 0 26 fW 1 95 ms 820 µs 0 1 1 27 fW 3 91 ms 1 64 ms 1 0 0 28 fW 7 81 ms 3 28 ms 1 0 1 29 fW 15 6 ms 6 55 ms 1 1 ...

Page 208: ...y the watch timer mode control register WTM by setting bits 0 WTM0 and 1 WTM1 of WTM to 1 the interval until the first interrupt request INTWT is generated after the register is set does not exactly match the specification made with bit 3 WTM3 of WTM This is because there is a delay of one 11 bit prescaler output cycle until the 5 bit counter starts counting Subsequently however the INTWT signal i...

Page 209: ...op Detection Time During Ring OSC Clock Operation During X1 Input Clock Operation fR 211 8 53 ms fXP 213 819 2 µs fR 212 17 07 ms fXP 214 1 64 ms fR 213 34 13 ms fXP 215 3 28 ms fR 214 68 27 ms fXP 216 6 55 ms fR 215 136 53 ms fXP 217 13 11 ms fR 216 273 07 ms fXP 218 26 21 ms fR 217 546 13 ms fXP 219 52 43 ms fR 218 1 09 s fXP 220 104 86 ms Remarks 1 fR Ring OSC clock oscillation frequency 2 fXP ...

Page 210: ...be stopped Current in STOP mode 10 µA The watchdog timer can be stopped in standby modeNote 2 Notes 1 As long as power is being supplied Ring OSC oscillation cannot be stopped except in the reset period 2 Clock supply to the watchdog timer is stopped in accordance with the watchdog timer clock source as follows 1 When the clock source is fXP Clock supply to the watchdog timer is stopped while fXP ...

Page 211: ...e register WDTM Watchdog timer enable register WDTE Figure 10 1 Block Diagram of Watchdog Timer fR 22 Clock input controller Output controller WDTRES internal reset signal WDCS2 Internal bus WDCS1 WDCS0 fXP 24 WDCS3 WDCS4 0 1 1 Selector 16 bit counter fXP 213 to fXP 220 or fR 211 to fR 218 Watchdog timer enable register WDTE Watchdog timer mode register WDTM 3 3 2 Clear Mask option to set Ring OSC...

Page 212: ...peration stopped Overflow time setting WDCS2Note 2 WDCS1Note 2 WDCS0Note 2 During Ring OSC clock operation During X1 input clock operation 0 0 0 fR 211 8 53 ms fXP 213 819 2 µs 0 0 1 fR 212 17 07 ms fXP 214 1 64 ms 0 1 0 fR 213 34 13 ms fXP 215 3 28 ms 0 1 1 fR 214 68 27 ms fXP 216 6 55 ms 1 0 0 fR 215 136 53 ms fXP 217 13 11 ms 1 0 1 fR 216 273 07 ms fXP 218 26 21 ms 1 1 0 fR 217 546 13 ms fXP 21...

Page 213: ... 240 kHz TYP fXP 10 MHz 2 Watchdog timer enable register WDTE Writing ACH to WDTE clears the watchdog timer counter and starts counting again This register can be set by an 8 bit memory manipulation instruction RESET input sets this register to 9AH Figure 10 3 Format of Watchdog Timer Enable Register WDTE 0 1 2 3 4 5 6 7 Symbol WDTE Address FF99H After reset 9AH R W Cautions 1 If a value other tha...

Page 214: ...et in the watchdog timer mode register WDTM by an 8 bit memory manipulation instruction Notes 1 2 Cycle Set using bits 2 to 0 WDCS2 to WDCS0 3 After the above procedures are executed writing ACH to WDTE clears the count to 0 enabling recounting Notes 1 The operation clock Ring OSC clock cannot be changed If any value is written to bits 3 and 4 WDCS3 WDCS4 of WDTM it is ignored 2 As soon as WDTM is...

Page 215: ...eration stopped Cycle Set using bits 2 to 0 WDCS2 to WDCS0 3 After the above procedures are executed writing ACH to WDTE clears the count to 0 enabling recounting Notes 1 As soon as WDTM is written the counter of the watchdog timer is cleared 2 Set bits 7 6 and 5 to 0 1 1 respectively If other values are set the watchdog timer cannot be operated an error occurs in the assembler 3 If the watchdog t...

Page 216: ...d to 0 Figure 10 4 Operation in STOP Mode CPU Clock and WDT Operation Clock X1 Input Clock Watchdog timer Operating Operation stopped Operating fR fXP CPU operation Normal operation STOP Oscillation stabilization time Normal operation Oscillation stopped Oscillation stabilization time set by OSTS register 2 When the CPU clock is the X1 input clock fXP and the watchdog timer operation clock is the ...

Page 217: ...ck WDT Operation Clock X1 Input Clock 1 Timing when counting is started after the oscillation stabilization time set by the oscillation stabilization time select register OSTS has elapsed Watchdog timer Operating Operation stopped Operating fR fXP CPU operation 17 clocks Normal operation Ring OSC clock Clock supply stopped Normal operation Ring OSC clock Oscillation stopped STOP Oscillation stabil...

Page 218: ...operation Ring OSC clock Oscillation stopped STOP Oscillation stabilization time set by OSTS register Operating Operation stopped 10 4 4 Watchdog timer operation in HALT mode when Ring OSC can be stopped by software is selected by mask option The watchdog timer stops counting during HALT instruction execution regardless of whether the CPU clock is the X1 input clock fXP Ring OSC clock fR or subsys...

Page 219: ...ed transmission and clock output for supply to peripheral LSIs The clock selected with the clock output selection register CKS is output Figure 11 1 shows the block diagram of clock output controller Figure 11 1 Block Diagram of Clock Output Controller 8 Clock controller CLOE PCL INTP6 P140 Internal bus Selector CLOE CCS3 CCS2 CCS1 CCS0 Clock output selection register CKS Prescaler fX to fX 27 fXT...

Page 220: ... register CKS Port mode register 14 PM14 Note Note See Figure 4 18 Block Diagram of P140 11 3 Registers Controlling Clock Output Controller The following two registers are used to control the clock output controller Clock output selection register CKS Port mode register 14 PM14 1 Clock output selection register CKS This register sets output enable disable for clock output PCL and sets the output c...

Page 221: ...to low level 1 Clock division circuit operation enabled PCL output enabled CCS3 CCS2 CCS1 CCS0 PCL output clock selection 0 0 0 0 fX 10 MHz 0 0 0 1 fX 2 5 MHz 0 0 1 0 fX 22 2 5 MHz 0 0 1 1 fX 23 1 25 MHz 0 1 0 0 fX 24 625 kHz 0 1 0 1 fX 25 312 5 kHz 0 1 1 0 fX 26 156 25 kHz 0 1 1 1 fX 27 78 125 kHz 1 0 0 0 fXT 32 768 kHz Other than above Setting prohibited Remarks 1 fX X1 input clock oscillation f...

Page 222: ... PCL pin for clock output set PM140 and the output latch of P140 to 0 PM14 is set by a 1 bit or 8 bit memory manipulation instruction RESET input sets PM14 to FFH Figure 11 3 Format of Port Mode Register 14 PM14 Address FF2EH After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PM14 1 1 1 1 1 1 1 PM140 PM140 P140 pin I O mode selection 0 Output mode output buffer on 1 Input mode output buffer off ...

Page 223: ...CKS clock pulse output in disabled status 2 Set bit 4 CLOE of CKS to 1 to enable clock output Remark The clock output controller is designed not to output pulses with a small width during output enable disable switching of the clock output As shown in Figure 11 4 be sure to start output from the low period of the clock marked with in the figure When stopping output do so after securing high level ...

Page 224: ...ower fail detection function This function is used to detect a voltage drop in a battery The A D conversion result ADCR register value and power fail comparison threshold register PFT value are compared INTAD is generated only when a comparative condition has been matched Figure 12 1 Block Diagram of A D Converter Sample hold circuit Series resistor string Successive approximation register SAR ADC...

Page 225: ...tion Function Selector PFEN PFCM Internal bus A D converter PFCM PFEN Comparator Power fail comparison mode register PFM Power fail comparison threshold register PFT INTAD Selector ANI0 P20 ANI1 P21 ANI2 P22 ANI3 P23 ADS1 ADS0 Analog input channel specification register ADS ADS2 ANI4 P24 ANI5 P25 ANI6 P26 ANI7 P27 ...

Page 226: ...result register 2 A D conversion result register ADCR The ADCR is 16 bit register that stores the A D conversion result The lower six bits are fixed to 0 Each time A D conversion ends the conversion result is loaded from the successive approximation register and is stored in ADCR in order starting from the most significant bit MSB ADCR can be read by a 16 bit memory manipulation instruction RESET ...

Page 227: ...P27 When A D conversion is performed with any of ANI0 to ANI7 selected do not execute the input instruction to port 2 while conversion is in progress otherwise the conversion resolution may be degraded If a digital pulse is applied to the pins adjacent to the pins currently used for A D conversion the expected value of the A D conversion may not be obtained due to coupling noise Therefore do not a...

Page 228: ...selectionNote 1 288 fX 240 fX 192 fX 144 fX 120 fX 96 fX Setting prohibited FR2 0 0 0 1 1 1 Other than above FR1 0 0 1 0 0 1 FR0 0 1 0 0 1 0 0 1 2 3 4 5 6 7 ADM Address FF28H After reset 00H R W Symbol µ µ µ µ µ µ 34 3 s 28 6 s 22 9 s 17 2 s 14 3 s 11 5 sNote 1 28 8 s 24 0 s 19 2 s 14 4 s 12 0 sNote 1 9 6 sNote 1 µ µ µ µ µ µ fX 8 38 MHz fX 10 MHz Boost reference voltage generator operation control...

Page 229: ...st reference voltage ADCS Conversion operation Conversion operation Conversion stopped Conversion waiting Boost reference voltage generator operating Note Note 14 µs or more is required for reference voltage stabilization Cautions 1 A D conversion must be stopped before rewriting bits FR0 to FR2 to values other than the identical data 2 For the sampling time of the A D converter and the A D conver...

Page 230: ...nalog Input Channel Specification Register ADS ADS0 ADS1 ADS2 0 0 0 0 0 Analog input channel specification ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ADS0 0 1 0 1 0 1 0 1 ADS1 0 0 1 1 0 0 1 1 ADS2 0 0 0 0 1 1 1 1 0 1 2 3 4 5 6 7 ADS Address FF29H After reset 00H R W Symbol Cautions 1 Be sure to set bits 3 to 7 of ADS to 0 2 If data is written to ADS a wait cycle is generated Do not write data to ADS ...

Page 231: ... Symbol Caution If data is written to PFM a wait cycle is generated Do not write data to PFM when the CPU is operating on the subsystem clock and the X1 input clock is stopped For details refer to CHAPTER 29 CAUTIONS FOR WAIT 4 Power fail comparison threshold register PFT The power fail comparison threshold register PFT is a register that sets the threshold value when comparing the values with the...

Page 232: ... is greater than 1 2 AVREF the MSB of SAR remains set to 1 If the analog input is smaller than 1 2 AVREF the MSB is reset to 0 6 Next bit 8 of SAR is automatically set to 1 and the operation proceeds to the next comparison The series resistor string voltage tap is selected according to the preset value of bit 9 as described below Bit 9 1 3 4 VDD Bit 9 0 1 4 VDD The voltage tap and analog input vol...

Page 233: ...continuously until bit 7 ADCS of the A D converter mode register ADM is reset 0 by software If a write operation is performed to one of the ADM analog input channel specification register ADS power fail comparison mode register PFM or power fail comparison threshold register PFT during an A D conversion operation the conversion operation is initialized and if the ADCS bit is set 1 conversion start...

Page 234: ... VIN ADCR 0 5 where INT Function which returns integer part of value in parentheses VIN Analog input voltage AVREF AVREF pin voltage ADCR A D conversion result register ADCR value Figure 12 10 shows the relationship between the analog input voltage and the A D conversion result Figure 12 10 Relationship Between Analog Input Voltage and A D Conversion Result 1023 1022 1021 3 2 1 0 A D conversion re...

Page 235: ...d by the analog input channel specification register ADS is started When A D conversion has been completed the result of the A D conversion is stored in the A D conversion result register ADCR and an interrupt request signal INTAD is generated Once the A D conversion has started and when one A D conversion has been completed the next A D conversion operation is immediately started The A D conversi...

Page 236: ...shold register PFT and an interrupt request signal INTAD is generated under the condition specified by bit 6 PFCM of PFM 1 When PFEN 0 INTAD is generated at the end of each A D conversion 2 When PFEN 1 and PFCM 0 The ADCR and PFT values are compared when A D conversion ends and INTAD is only generated when ADCR PFT 3 When PFEN 1 and PFCM 1 The ADCR and PFT values are compared when A D conversion e...

Page 237: ... function 1 Set bit 7 PFEN of the power fail comparison mode register PFM to 1 2 Set power fail comparison condition using bit 6 PFCM of PFM 3 Set bit 0 ADCE of the A D converter mode register ADM to 1 4 Select the channel and conversion time using bits 2 to 0 ADS2 to ADS0 of the analog input channel specification register ADS and bits 5 to 3 FR2 to FR0 of ADM 5 Set a threshold value to the power ...

Page 238: ... theoretical value Zero scale error full scale error integral linearity error and differential linearity errors that are combinations of these express the overall error Note that the quantization error is not included in the overall error in the characteristics table 3 Quantization error When analog values are converted to digital values a 1 2LSB error naturally occurs In an A D converter an analo...

Page 239: ...degree to which the conversion characteristics deviate from the ideal linear relationship It expresses the maximum value of the difference between the actual measurement value and the ideal straight line when the zero scale error and full scale error are 0 7 Differential linearity error While the ideal width of code output is 1LSB this indicates the difference between the actual measurement value ...

Page 240: ... operating in the standby mode At this time the power consumption can be reduced by stopping the conversion operation by setting bit 7 ADCS of the A D converter mode register ADM to 0 Figure 12 19 shows the circuit configuration of series resistor string Figure 12 19 Circuit Configuration of Series Resistor String AVREF AVSS P ch Series resistor string ADCS 2 Input range of ANI0 to ANI7 Observe th...

Page 241: ... ADCR and Timing of Data Read from ADCR 1 Timing to read old data Internal clock INTAD Master write signal A D conversion master Slave write signal ADCR slave Read data Conversion end Conversion result N Conversion result N Conversion result N Conversion result N 1 2 Timing to read new data Internal clock INTAD Master write signal A D conversion master Slave write signal ADCR slave Read data Conve...

Page 242: ... a digital pulse is applied to the pins adjacent to the pins currently used for A D conversion the expected value of the A D conversion may not be obtained due to coupling noise Therefore do not apply a pulse to the pins adjacent to the pin undergoing A D conversion 6 Input impedance of ANI0 to ANI7 pins In this A D converter the internal sampling capacitor is charged and sampling is performed for...

Page 243: ...ANIn conversion A D conversion ADCR INTAD ANIn ANIn ANIm ANIm ANIn ANIn ANIm ANIm ADS rewrite start of ANIm conversion ADIF is set but ANIm conversion has not ended Remarks 1 n 0 to 7 2 m 0 to 7 9 Conversion results just after A D conversion start The first A D conversion value immediately after A D conversion starts may not fall within the rating Take measures such as polling the A D conversion e...

Page 244: ...pling and A D Conversion Start Delay ADCS Wait period Conversion time A D conversion start delay time Sampling time Sampling timing INTAD ADCS 1 or ADS rewrite Table 12 3 A D Converter Sampling Time and A D Conversion Start Delay Time ADM Set Value A D Conversion Start Delay TimeNote FR2 FR1 FR0 Conversion Time Sampling Time MIN MAX 0 0 0 288 fX 40 fX 32 fX 36 fX 0 0 1 240 fX 32 fX 28 fX 32 fX 0 1...

Page 245: ...1 The initial value of the TXD0 pin is high level Exercise care when using the TXD0 pin as a port pin 2 If clock supply to serial interface UART0 is not stopped e g in the HALT mode normal operation continues If clock supply to serial interface UART0 is stopped e g in the STOP mode each register stops operating and holds the value immediately before clock supply was stopped The TXD0 pin also holds...

Page 246: ...ardware Table 13 1 Configuration of Serial Interface UART0 Item Configuration Registers Receive buffer register 0 RXB0 Receive shift register 0 RXS0 Transmit shift register 0 TXS0 Control registers Asynchronous serial interface operation mode register 0 ASIM0 Asynchronous serial interface reception error status register 0 ASIS0 Baud rate generator control register 0 BRGC0 ...

Page 247: ...XS0 Receive shift register 0 RXS0 Receive buffer register 0 RXB0 Asynchronous serial interface reception error status register 0 ASIS0 Asynchronous serial interface operation mode register 0 ASIM0 Baud rate generator control register 0 BRGC0 TO50 TI50 P17 TM50 output Registers Selector Baud rate generator Baud rate generator Reception unit Reception control Filter Internal bus Transmission control...

Page 248: ... 0 sets this register to FFH RXB0 can be read by an 8 bit memory manipulation instruction No data can be written to this register 2 Receive shift register 0 RXS0 This register converts the serial data input to the RXD0 pin into parallel data RXS0 cannot be directly manipulated by a program 3 Transmit shift register 0 TXS0 This register is used to set transmit data Transmission is started when data...

Page 249: ...ion of internal operation clock 0Note Disables operation of the internal operation clock fixes the clock to low level and asynchronously resets the internal circuit 1 Enables operation of the internal operation clock TXE0 Enables disables transmission 0 Disables transmission synchronously resets the transmission circuit 1 Enables transmission RXE0 Enables disables reception 0 Disables reception sy...

Page 250: ...mit receive data 0 Character length of data 7 bits 1 Character length of data 8 bits SL0 Specifies number of stop bits of transmit data 0 Number of stop bits 1 1 Number of stop bits 2 Note If reception as 0 parity is selected the parity is not judged Therefore bit 2 PE0 of asynchronous serial interface reception error status register 0 ASIS0 is not set and the error interrupt does not occur Cautio...

Page 251: ...ch the parity bit on completion of reception FE0 Status flag indicating framing error 0 If POWER0 0 and RXE0 0 or if ASIS0 register is read 1 If the stop bit is not detected on completion of reception OVE0 Status flag indicating overrun error 0 If POWER0 0 and RXE0 0 or if ASIS0 register is read 1 If receive data is set to the RXB register and the next reception operation is completed before the d...

Page 252: ...X 2 5 MHz 1 0 fX 23 1 25 MHz 1 1 fX 25 312 5 kHz MDL04 MDL03 MDL02 MDL01 MDL00 k Selection of 5 bit counter output clock 0 0 Setting prohibited 0 1 0 0 0 8 fXCLK 8 0 1 0 0 1 9 fXCLK 9 0 1 0 1 0 10 fXCLK 10 1 1 0 1 0 26 fXCLK 26 1 1 0 1 1 27 fXCLK 27 1 1 1 0 0 28 fXCLK 28 1 1 1 1 0 30 fXCLK 30 1 1 1 1 1 31 fXCLK 31 Cautions 1 Make sure that bit 6 TXE0 and bit 5 RXE0 of the ASIM0 register 0 when rew...

Page 253: ... the internal operation clock fixes the clock to low level and asynchronously resets the internal circuit 1 Enables operation of the internal operation clock TXE0 Enables disables transmission 0 Disables transmission synchronously resets the transmission circuit 1 Enables transmission RXE0 Enables disables reception 0 Disables reception synchronously resets the reception circuit 1 Enables receptio...

Page 254: ...L0 1 POWER0 Enables disables operation of internal operation clock 0Note Disables operation of the internal operation clock fixes the clock to low level and asynchronously resets the internal circuit 1 Enables operation of the internal operation clock TXE0 Enables disables transmission 0 Disables transmission synchronously resets the transmission circuit 1 Enables transmission RXE0 Enables disable...

Page 255: ...7 bits 1 Character length of data 8 bits SL0 Specifies number of stop bits of transmit data 0 Number of stop bits 1 1 Number of stop bits 2 Note If reception as 0 parity is selected the parity is not judged Therefore bit 2 PE0 of asynchronous serial interface reception error status register 0 ASIS0 is not set and the error interrupt does not occur Cautions 1 Clear the TXE0 and RXE0 bits to 0 befor...

Page 256: ...E0 Status flag indicating framing error 0 If POWER0 0 and RXE0 0 or if ASIS0 register is read 1 If the stop bit is not detected on completion of reception OVE0 Status flag indicating overrun error 0 If POWER0 0 and RXE0 0 or if ASIS0 register is read 1 If receive data is set to the RXB register and the next reception operation is completed before the data is read Cautions 1 The operation of the PE...

Page 257: ... bit Even parity odd parity 0 parity or no parity Stop bit 1 or 2 bits The character bit length parity and stop bit length in one data frame are specified by asynchronous serial interface mode register 0 ASIM0 Figure 13 6 Example of Normal UART Transmit Receive Data Format 1 Data length 8 bits Parity Even parity Stop bit 1 bit Transfer data 55H 1 data frame Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Sto...

Page 258: ...e receive data including the parity bit is counted If it is odd a parity error occurs ii Odd parity Transmission Unlike even parity transmit data including the parity bit is controlled so that the number of bits that are 1 is odd If transmit data has an odd number of bits that are 1 0 If transmit data has an even number of bits that are 1 1 Reception The number of bits that are 1 in the receive da...

Page 259: ... from the LSB When transmission is completed the parity and stop bits set by ASIM0 are appended and a transmission completion interrupt request INTST0 is generated Transmission is stopped until the data to be transmitted next is written to TXS0 Figure 13 7 shows the timing of the transmission completion interrupt request INTST0 This interrupt occurs as soon as the last stop bit has been output Cau...

Page 260: ... has been received the reception completion interrupt INTSR0 is generated and the data of RXS0 is written to receive buffer register 0 RXB0 If an overrun error OVE0 occurs however the receive data is not written to RXB0 Even if a parity error PE0 or a framing error FE0 occurs while reception is in progress reception continues to the reception position of the stop bit and an error interrupt INTSR0 ...

Page 261: ...ption Error Reception Error Cause Value of ASIS0 Parity error The parity specified for transmission does not match the parity of the receive data 04H Framing error Stop bit is not detected 02H Overrun error Reception of the next data is completed before data is read from receive buffer register 0 RXB0 01H f Noise filter of receive data The RXD0 signal is sampled using the base clock output by the ...

Page 262: ...ops cleared to 0 when bit 7 POWER0 or bit 6 TXE0 of asynchronous serial interface operation mode register 0 ASIM0 is 0 It starts counting when POWER0 1 and TXE0 1 The counter is cleared to 0 when the first data transmitted is written to transmit shift register 0 TXS0 Reception counter This counter stops operation cleared to 0 when bit 7 POWER0 or bit 5 RXE0 of asynchronous serial interface operati...

Page 263: ...2 1 0 BRGC0 TPS01 TPS00 0 MDL04 MDL03 MDL02 MDL01 MDL00 TPS01 TPS00 Base clock fXCLK selection 0 0 TM50 output TO50 0 1 fX 2 5 MHz 1 0 fX 23 1 25 MHz 1 1 fX 25 312 5 kHz MDL04 MDL03 MDL02 MDL01 MDL00 k Selection of 5 bit counter output clock 0 0 Setting prohibited 0 1 0 0 0 8 fXCLK 8 0 1 0 0 1 9 fXCLK 9 0 1 0 1 0 10 fXCLK 10 1 1 0 1 0 26 fXCLK 26 1 1 0 1 1 27 fXCLK 27 1 1 1 0 0 28 fXCLK 28 1 1 1 1...

Page 264: ... following expression Error 1 100 Cautions 1 Keep the baud rate error during transmission to within the permissible error range at the reception destination 2 Make sure that the baud rate error during reception satisfies the range shown in 4 Permissible baud rate range during reception Example Frequency of base clock Clock 2 5 MHz 2 500 000 Hz Set value of MDL04 to MDL00 bits of BRGC0 register 100...

Page 265: ...10400 3 15 10417 0 16 3 13 10072 3 15 2 25 10475 0 72 19200 3 8 19531 1 73 2 27 19398 1 03 2 14 18705 2 58 31250 2 20 31250 0 2 17 30809 1 41 38400 2 16 39063 1 73 2 14 38796 2 58 2 27 38796 1 03 76800 2 8 78125 1 73 1 27 77593 1 03 1 14 74821 2 58 115200 1 22 113636 1 36 1 18 116389 1 03 1 9 116389 1 03 153600 1 16 156250 1 73 1 14 149643 2 58 230400 1 11 227273 1 36 1 9 232778 1 03 Remark TPS01 ...

Page 266: ... Start bit Bit 0 Bit 1 Bit 7 Parity bit Minimum permissible transfer rate Maximum permissible transfer rate Stop bit Start bit Bit 0 Bit 1 Bit 7 Parity bit Latch timing Stop bit Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit As shown in Figure 13 11 the latch timing of the receive data is determined by the counter set by baud rate generator control register 0 BRGC0 after the start bit has been de...

Page 267: ...e The permissible baud rate error between UART0 and the transmission destination can be calculated from the above minimum and maximum baud rate expressions as follows Table 13 4 Maximum Minimum Permissible Baud Rate Error Division Ratio k Maximum Permissible Baud Rate Error Minimum Permissible Baud Rate Error 8 3 53 3 61 16 4 14 4 19 24 4 34 4 38 31 4 44 4 47 Remarks 1 The accuracy of reception de...

Page 268: ...tion flag provided Cautions 1 The initial value of the TXD6 pin is the high level Exercise care when using the TXD6 pin as a port pin 2 The TXD6 output inversion function inverts only the transmission side and not the reception side To use this function the reception side must be ready for reception of inverted data it must be able to recognize a low level start bit 3 If clock supply to serial int...

Page 269: ...ud rate error Therefore communication is possible when the baud rate error in the slave is 15 or less Figures 14 1 and 14 2 outline the transmission and reception operations of LIN Figure 14 1 LIN Transmission Operation Sleep bus TX6 INTST6 Note 4 Wakeup signal frame Tuning break field Tuning field Match field Data field Checksum field Data field 8 bitsNote 3 Note 1 13 bitNote 2 SBF transmission 5...

Page 270: ...ture timer Detection of errors OVE6 PE6 and FE6 is suppressed and error detection processing of UART communication and data transfer of the shift register and RXB6 is not performed The shift register holds the reset value FFH 4 Calculate the baud rate error from the value obtained from the capture timer disable UART6 after SF reception and then re set baud rate generator control register 6 BRGC6 5...

Page 271: ...B output A B Q MPX Port mode PM00 A B Q Port latch P00 Remark ISC0 ISC1 Bits 0 and 1 of the input switch control register ISC see Figure 4 21 The resources used in the LIN communication operation are shown below Resources used External interrupt INTP0 wakeup signal detection Use Detects the wakeup signal edges and detects start of communication 16 bit timer event counter 00 TI000 baud rate error d...

Page 272: ...e buffer register 6 RXB6 Receive shift register 6 RXS6 Transmit buffer register 6 TXB6 Transmit shift register 6 TXS6 Control registers Asynchronous serial interface operation mode register 6 ASIM6 Asynchronous serial interface reception error status register 6 ASIS6 Asynchronous serial interface transmission status register 6 ASIF6 Clock selection register 6 CKSR6 Baud rate generator control regi...

Page 273: ... register 6 RXS6 Receive buffer register 6 RXB6 RXD6 P14 INTSR6 INTSRE6 Asynchronous serial interface reception error status register 6 ASIS6 Asynchronous serial interface operation mode register 6 ASIM6 Asynchronous serial interface transmission status register 6 ASIF6 fX fX 210 Clock selection register 6 CKSR6 Baud rate generator control register 6 BRGC6 TO50 TI50 P17 TM50 output Registers Selec...

Page 274: ...egister 6 TXB6 This buffer register is used to set transmit data Transmission is started when data is written to TXB6 This register can be read or written by an 8 bit memory manipulation instruction RESET input sets this register to FFH Cautions 1 Do not write data to TXB6 when bit 1 TXBF6 of asynchronous serial interface transmission status register 6 ASIF6 is 1 2 Do not refresh write the same va...

Page 275: ...n by software during a communication operation when bit 7 POWER6 and bit 6 TXE6 of ASIM6 1 or bit 7 POWER6 and bit 5 RXE6 of ASIM6 1 Figure 14 5 Format of Asynchronous Serial Interface Operation Mode Register 6 ASIM6 1 2 Address FF50H After reset 01H R W Symbol 7 6 5 4 3 2 1 0 ASIM6 POWER6 TXE6 RXE6 PS61 PS60 CL6 SL6 ISRM6 POWER6 Enables disables operation of internal operation clock 0Note 1 Disab...

Page 276: ...ber of stop bits 2 ISRM6 Enables disables occurrence of reception completion interrupt in case of error 0 INTSRE6 occurs in case of error at this time INTSR6 does not occur 1 INTSR6 occurs in case of error at this time INTSRE6 does not occur Note If reception as 0 parity is selected the parity is not judged Therefore bit 2 PE6 of asynchronous serial interface reception error status register 6 ASIS...

Page 277: ...atch the parity bit on completion of reception FE6 Status flag indicating framing error 0 If POWER6 0 and RXE6 0 or if ASIS6 register is read 1 If the stop bit is not detected on completion of reception OVE6 Status flag indicating overrun error 0 If POWER6 0 and RXE6 0 or if ASIS6 register is read 1 If receive data is set to the RXB register and the next reception operation is completed before the...

Page 278: ...TXB6 if data exists in TXB6 TXSF6 Transmit shift register data flag 0 If POWER6 0 or TXE6 0 or if the next data is not transferred from transmit buffer register 6 TXB6 after completion of transfer 1 If data is transferred from transmit buffer register 6 TXB6 if data transmission is in progress Cautions 1 To continuously transmit data write the data of the first byte to TXB6 check that the value of...

Page 279: ...IM6 1 Figure 14 8 Format of Clock Selection Register 6 CKSR6 Address FF56H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 CKSR6 0 0 0 0 TPS63 TPS62 TPS61 TPS60 TPS63 TPS62 TPS61 TPS60 Base clock fXCLK 0 0 0 0 fX 10 MHz 0 0 0 1 fX 2 5 MHz 0 0 1 0 fX 22 2 5 MHz 0 0 1 1 fX 23 1 25 MHz 0 1 0 0 fX 24 625 kHz 0 1 0 1 fX 25 312 5 kHz 0 1 1 0 fX 26 156 25 kHz 0 1 1 1 fX 27 78 13 kHz 1 0 0 0 fX 28 39 06 kHz 1 ...

Page 280: ...reset FFH R W Symbol 7 6 5 4 3 2 1 0 BRGC6 MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 MDL60 MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 MDL60 k Output clock selection of 8 bit counter 0 0 0 0 0 Setting prohibited 0 0 0 0 1 0 0 0 8 fXCLK 8 0 0 0 0 1 0 0 1 9 fXCLK 9 0 0 0 0 1 0 1 0 10 fXCLK 10 1 1 1 1 1 1 0 0 252 fXCLK 252 1 1 1 1 1 1 0 1 253 fXCLK 253 1 1 1 1 1 1 1 0 254 fXCLK 254 1 1 1 1 1 1 1 1 255 ...

Page 281: ...ntrol Register 6 ASICL6 1 2 Address FF58H After reset 16H R WNote Symbol 7 6 5 4 3 2 1 0 ASICL6 SBRF6 SBRT6 SBTT6 SBL62 SBL61 SBL60 DIR6 TXDLV6 SBRF6 SBF reception status flag 0 If POWER6 0 and RXE6 0 or if SBF reception has been completed correctly 1 SBF reception in progress SBRT6 SBF reception trigger 0 1 SBF reception trigger SBTT6 SBF transmission trigger 0 1 SBF transmission trigger Note Bit...

Page 282: ...length 1 1 1 SBF is output with 15 bit length 0 0 0 SBF is output with 16 bit length 0 0 1 SBF is output with 17 bit length 0 1 0 SBF is output with 18 bit length 0 1 1 SBF is output with 19 bit length 1 0 0 SBF is output with 20 bit length DIR6 MSB LSB first transfer 0 MSB first transfer 1 LSB first transfer TXDLV6 Enables disables inverting TXD6 output 0 Normal output of TXD6 1 Inverted output o...

Page 283: ...ol 7 6 5 4 3 2 1 0 ASIM6 POWER6 TXE6 RXE6 PS61 PS60 CL SL6 ISRM6 POWER6 Enables disables operation of internal operation clock 0Note 1 Disables operation of the internal operation clock fixes the clock to low level and asynchronously resets the internal circuit 1Note 2 Enables operation of the internal operation clock TXE6 Enables disables transmission 0 Disables transmission operation synchronous...

Page 284: ...tion instruction RESET input sets this register to 01H Remark ASIM6 can be refreshed the same value is written by software during a communication operation when bit 7 POWER6 and bit 6 TXE6 of ASIM6 1 or bit 7 POWER6 and bit 5 RXE6 of ASIM6 1 Address FF50H After reset 01H R W Symbol 7 6 5 4 3 2 1 0 ASIM6 POWER6 TXE6 RXE6 PS61 PS60 CL6 SL6 ISRM6 POWER6 Enables disables operation of internal operatio...

Page 285: ...currence of reception completion interrupt in case of error 0 INTSRE6 occurs in case of error at this time INTSR6 does not occur 1 INTSR6 occurs in case of error at this time INTSRE6 does not occur Note If reception as 0 parity is selected the parity is not judged Therefore bit 2 PE6 of asynchronous serial interface reception error status register 6 ASIS6 is not set and the error interrupt does no...

Page 286: ... FE6 Status flag indicating framing error 0 If POWER6 0 and RXE6 0 or if ASIS6 register is read 1 If the stop bit is not detected on completion of reception OVE6 Status flag indicating overrun error 0 If POWER6 0 and RXE6 0 or if ASIS6 register is read 1 If receive data is set to the RXB register and the next reception operation is completed before the data is read Cautions 1 The operation of the ...

Page 287: ...hift register data flag 0 If POWER6 0 or TXE6 0 or if the next data is not transferred from transmit buffer register 6 TXB6 after completion of transfer 1 If data is transferred from transmit buffer register 6 TXB6 if data transmission is in progress Cautions 1 To continuously transmit data write the data of the first byte to TXB6 check that the value of the TXBF6 flag is 0 and then write the data...

Page 288: ... After reset 16H R WNote Symbol 7 6 5 4 3 2 1 0 ASICL6 SBRF6 SBRT6 SBTT6 SBL62 SBL61 SBL60 DIR6 TXDLV6 SBRF6 SBF reception status flag 0 If POWER6 0 and RXE6 0 or if SBF reception has been completed correctly 1 SBF reception in progress SBRT6 SBF reception trigger 0 1 SBF reception trigger SBTT6 SBF transmission trigger 0 1 SBF transmission trigger Note Bit 7 is read only Cautions 1 In the case of...

Page 289: ...gth 0 0 0 SBF is output with 16 bit length 0 0 1 SBF is output with 17 bit length 0 1 0 SBF is output with 18 bit length 0 1 1 SBF is output with 19 bit length 1 0 0 SBF is output with 20 bit length DIR6 MSB LSB first transfer 0 MSB first transfer 1 LSB first transfer TXDLV6 Enables disables inverting TXD6 output 0 Normal output of TXD6 1 Inverted output of TXD6 Caution Before rewriting the DIR6 a...

Page 290: ...rt bit Parity bit D7 D6 D5 D4 D3 1 data frame Character bits D2 D1 D0 Stop bit One data frame consists of the following bits Start bit 1 bit Character bits 7 or 8 bits Parity bit Even parity odd parity 0 parity or no parity Stop bit 1 or 2 bits The character bit length parity and stop bit length in one data frame are specified by asynchronous serial interface mode register 6 ASIM6 Whether data is ...

Page 291: ...n parity Stop bit 1 bit Transfer data 55H 1 data frame Start D7 D6 D5 D4 D3 D2 D1 D0 Parity Stop 3 Data length 8 bits MSB first Parity Even parity Stop bit 1 bit Transfer data 55H TXD6 pin inverted output 1 data frame Start D7 D6 D5 D4 D3 D2 D1 D0 Parity Stop 4 Data length 7 bits LSB first Parity Odd parity Stop bit 2 bits Transfer data 36H 1 data frame Start D0 D1 D2 D3 D4 D5 D6 Parity Stop Stop ...

Page 292: ...tion The number of bits that are 1 in the receive data including the parity bit is counted If it is odd a parity error occurs ii Odd parity Transmission Unlike even parity transmit data including the parity bit is controlled so that the number of bits that are 1 is odd If transmit data has an odd number of bits that are 1 0 If transmit data has an even number of bits that are 1 1 Reception The num...

Page 293: ...ata in TXB6 is transferred to transmit shift register 6 TXS6 After that the data is sequentially output from TXS6 to the TXD6 pin starting from the LSB When transmission is completed a transmission completion interrupt request INTST6 is generated Transmission is stopped until the data to be transmitted next is written to TXB6 Figure 14 13 shows the timing of the transmission completion interrupt r...

Page 294: ...n of Continuous Transmission Writing to TXB6 During Execution of Continuous Transmission 0 0 Enables writing 2 bytes or transmission completion processing Enables writing 0 1 Enables writing 1 byte Enables writing 1 0 Enables writing 2 bytes or transmission completion processing Disables writing 1 1 Enables writing 1 byte Disables writing Cautions 1 To continuously transmit data write the data of ...

Page 295: ...cuted necessary number of times Write transmit data to TXB6 register Write transmit data to TXB6 register Read ASIF6 register TXBF6 0 Read ASIF6 register TXSF6 1 Read ASIF6 register TXSF6 0 No No No No Yes Yes Yes Yes Completion of transmission processing Remark TXB6 Transmit buffer register 6 ASIF6 Asynchronous serial interface transmission status register 6 TXBF6 Bit 1 of ASIF6 transmit buffer d...

Page 296: ... 1 Data 1 Data 2 Data 3 Data 2 Data 1 Data 3 FF FF Parity Stop Data 2 Parity Stop TXB6 TXS6 TXBF6 TXSF6 Start Start Note Note When ASIF6 is read there is a period in which TXBF6 and TXSF6 1 1 Therefore judge whether writing is enabled using only the TXBF6 bit Remark TXD6 TXD6 pin output INTST6 Interrupt request signal TXB6 Transmit buffer register 6 TXS6 Transmit shift register 6 ASIF6 Asynchronou...

Page 297: ...top TXB6 TXS6 TXBF6 TXSF6 POWER6 or TXE6 Start Remark TXD6 TXD6 pin output INTST6 Interrupt request signal TXB6 Transmit buffer register 6 TXS6 Transmit shift register 6 ASIF6 Asynchronous serial interface transmission status register 6 TXBF6 Bit 1 of ASIF6 TXSF6 Bit 0 of ASIF6 POWER6 Bit 7 of asynchronous serial interface operation mode register ASIM6 TXE6 Bit 6 of asynchronous serial interface o...

Page 298: ...it has been received the reception completion interrupt INTSR6 is generated and the data of RXS6 is written to receive buffer register 6 RXB6 If an overrun error OVE6 occurs however the receive data is not written to RXB6 Even if a parity error PE6 or a framing error FE6 occurs while reception is in progress reception continues to the reception position of the stop bit and an error interrupt INTSR...

Page 299: ...Table 14 3 Cause of Reception Error Reception Error Cause Value of ASIS6 Parity error The parity specified for transmission does not match the parity of the receive data 04H Framing error Stop bit is not detected 02H Overrun error Reception of the next data is completed before data is read from receive buffer register 6 RXB6 01H The error interrupt can be separated into INTSR6 and INTSRE6 by clear...

Page 300: ...6 pin outputs a high level when bit 7 POWER6 of asynchronous serial interface operation mode register 6 ASIM6 is set to 1 Transmission is enabled when bit 6 TXE6 of ASIM6 is set to 1 next time and SBF transmission operation is started when bit 5 SBTT6 of asynchronous serial interface control register 6 ASICL6 is set to 1 After transmission has been started the low levels of bits 13 to 20 set by bi...

Page 301: ...upt request INTSR6 is generated as normal processing At this time the SBRF6 and SBRT6 bits are automatically cleared and SBF reception ends Detection of errors such as OVE6 PE6 and FE6 bits 0 to 2 of asynchronous serial interface reception error status register 6 ASIS6 is suppressed and error detection processing of UART communication is not performed In addition data transfer between receive shif...

Page 302: ... low level when POWER6 0 Transmission counter This counter stops cleared to 0 when bit 7 POWER6 or bit 6 TXE6 of asynchronous serial interface operation mode register 6 ASIM6 is 0 It starts counting when POWER6 1 and TXE6 1 The counter is cleared to 0 when the first data transmitted is written to transmit buffer register 6 TXB6 If data are continuously transmitted the counter is cleared to 0 again...

Page 303: ... detector Baud rate BRGC6 MDL67 to MDL60 1 2 POWER6 TXE6 or RXE6 CKSR6 TPS63 to TPS60 fX fX 2 fX 22 fX 23 fX 24 fX 25 fX 26 fX 27 fX 28 fX 29 fX 210 TO50 TI50 P17 TM50 output Remark POWER6 Bit 7 of asynchronous serial interface operation mode register 6 ASIM6 TXE6 Bit 6 of ASIM6 RXE6 Bit 5 of ASIM6 CKSR6 Clock selection register 6 BRGC6 Baud rate generator control register 6 ...

Page 304: ...this register to 00H Remark CKSR6 can be refreshed the same value is written by software during a communication operation when bit 7 POWER6 and bit 6 TXE6 of ASIM6 1 or bit 7 POWER6 and bit 5 RXE6 of ASIM6 1 Address FF56H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 CKSR6 0 0 0 0 TPS63 TPS62 TPS61 TPS60 TPS63 TPS62 TPS61 TPS60 Base clock fXCLK 0 0 0 0 fX 10 MHz 0 0 0 1 fX 2 5 MHz 0 0 1 0 fX 22 2 5 M...

Page 305: ... 0 BRGC6 MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 MDL60 MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 MDL60 k Output clock selection of 8 bit counter 0 0 0 0 0 Setting prohibited 0 0 0 0 1 0 0 0 8 fXCLK 8 0 0 0 0 1 0 0 1 9 fXCLK 9 0 0 0 0 1 0 1 0 10 fXCLK 10 1 1 1 1 1 1 0 0 252 fXCLK 252 1 1 1 1 1 1 0 1 253 fXCLK 253 1 1 1 1 1 1 1 0 254 fXCLK 254 1 1 1 1 1 1 1 1 255 fXCLK 255 Cautions 1 Make sure tha...

Page 306: ...g expression Error 1 100 Cautions 1 Keep the baud rate error during transmission to within the permissible error range at the reception destination 2 Make sure that the baud rate error during reception satisfies the range shown in 4 Permissible baud rate range during reception Example Frequency of base clock Clock 20 MHz 20 000 000 Hz Set value of MDL67 to MDL60 bits of BRGC6 register 01000001B k ...

Page 307: ...2H 120 10417 0 16 2H 101 10371 0 28 1H 101 10475 0 28 19200 1H 130 19231 0 16 1H 109 19200 0 11 0H 109 19220 0 11 31250 1H 80 31250 0 00 0H 134 31268 0 06 0H 67 31268 0 06 38400 0H 130 38462 0 16 0H 109 38440 0 11 0H 55 38090 0 80 76800 0H 65 76923 0 16 0H 55 76182 0 80 0H 27 77593 1 03 115200 0H 43 116279 0 94 0H 36 116388 1 03 0H 18 116389 1 03 153600 0H 33 151515 1 36 0H 27 155185 1 03 0H 14 14...

Page 308: ...y bit Minimum permissible transfer rate Maximum permissible transfer rate Stop bit Start bit Bit 0 Bit 1 Bit 7 Parity bit Latch timing Stop bit Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit As shown in Figure 14 23 the latch timing of the receive data is determined by the counter set by baud rate generator control register 6 BRGC6 after the start bit has been detected If the last data stop bit m...

Page 309: ...e error between UART6 and the transmission destination can be calculated from the above minimum and maximum baud rate expressions as follows Table 14 5 Maximum Minimum Permissible Baud Rate Error Division Ratio k Maximum Permissible Baud Rate Error Minimum Permissible Baud Rate Error 8 3 53 3 61 20 4 26 4 31 50 4 56 4 58 100 4 66 4 67 255 4 72 4 73 Remarks 1 The accuracy of reception depends on th...

Page 310: ...because the timing is initialized on the reception side when the start bit is detected Figure 14 24 Transfer Rate During Continuous Transmission Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FL 1 data frame FL FL FL FL FL FL FLstp Start bit of second byte Start bit Bit 0 Where the 1 bit data length is FL the stop bit length is FLstp and base clock frequency is fXCLK the following expression is s...

Page 311: ... data transfer can be shortened in the 3 wire serial I O mode because transmission and reception can be simultaneously executed In addition whether 8 bit data is transferred with the MSB or LSB first can be specified so this interface can be connected to any device The 3 wire serial I O mode is useful for connecting peripheral ICs and display controllers with a clocked serial interface 15 2 Config...

Page 312: ...ritten to SOTB10 is converted from parallel data into serial data by serial I O shift register 10 and output to the serial output pin SO10 SOTB10 can be written or read by an 8 bit memory manipulation instruction RESET input makes this register undefined Caution Do not access SOTB10 when CSOT10 1 during serial communication 2 Serial I O shift register 10 SIO10 This is an 8 bit register that conver...

Page 313: ...0 0 0 CSOT10 CSIE10 Operation control in 3 wire serial I O mode 0 Stops operation SI10 P11 RXD0 SO10 P12 and SCK10 P10 TXD0 pins can be used as general purpose port pins 1 Enables operation SI10 P11 RXD0 SO10 P12 and SCK10 P10 TXD0 pins are at active level TRMD10Note 2 Transmit receive mode control 0Note 3 Receive mode transmission disabled 1 Transmit receive mode DIR10Note 4 First bit specificati...

Page 314: ...CK10 SO10 SI10 input timing 1 0 1 D7 D6 D5 D4 D3 D2 D1 D0 SCK10 SO10 SI10 input timing 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 SCK10 SO10 SI10 input timing 3 1 1 D7 D6 D5 D4 D3 D2 D1 D0 SCK10 SO10 SI10 input timing 4 CKS102 CKS101 CKS100 CSI10 count clock selection 0 0 0 fX 2 5 MHz 0 0 1 fX 22 2 5 MHz 0 1 0 fX 23 1 25 MHz 0 1 1 fX 24 625 kHz 1 0 0 fX 25 312 5 kHz 1 0 1 fX 26 156 25 kHz 1 1 0 fX 27 78 13 kHz...

Page 315: ...s ordinary I O port pins in this mode 1 Register setting The operation stop mode is set by serial operation mode register 10 CSIM10 a Serial operation mode register 10 CSIM10 CSIM10 can be set by a 1 bit or 8 bit memory manipulation instruction RESET input clears CSIM10 to 00H Address FF80H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 CSIM10 CSIE10 TRMD10 0 DIR10 0 0 0 CSOT10 CSIE10 Operation contro...

Page 316: ...bol 7 6 5 4 3 2 1 0 CSIM10 CSIE10 TRMD10 0 DIR10 0 0 0 CSOT10 CSIE10 Operation control in 3 wire serial I O mode 0 Stops operation SI10 P11 RXD0 SO10 P12 and SCK10 P10 TXD0 pins can be used as general purpose port pins 1 Enables operation SI10 P11 RXD0 SO10 P12 and SCK10 P10 TXD0 pins are at active level TRMD10Note 2 Transmit receive mode control 0Note 3 Receive mode transmission disabled 1 Transm...

Page 317: ...I10 input timing 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 SCK10 SO10 SI10 input timing 3 1 1 D7 D6 D5 D4 D3 D2 D1 D0 SCK10 SO10 SI10 input timing 4 CKS102 CKS101 CKS100 CSI10 count clock selection 0 0 0 fX 2 5 MHz 0 0 1 fX 22 2 5 MHz 0 1 0 fX 23 1 25 MHz 0 1 1 fX 24 625 kHz 1 0 0 fX 25 312 5 kHz 1 0 1 fX 26 156 25 kHz 1 1 0 fX 27 78 13 kHz 1 1 1 External clock input to SCK10 Cautions 1 Do not write CSIC10 du...

Page 318: ...Bit 2 PM12 of port mode register 1 Cleared to 0 Bit 0 PM10 of port mode register 1 Cleared to 0 Bit 2 P12 of port 1 Cleared to 0 Bit 0 P10 of port 1 Set to 1 2 Receive mode with transmission disabled a To use externally input clock as system clock SCK10 Bit 1 PM11 of port mode register 1 Set to 1 Bit 0 PM10 of port mode register 1 Set to 1 b To use internal clock as system clock SCK10 Bit 1 PM11 o...

Page 319: ...register 10 CSIM10 is 0 Reception is started when data is read from serial I O shift register 10 SIO10 After communication has been started bit 0 CSOT10 of CSIM10 is set to 1 When communication of 8 bit data has been completed a communication completion interrupt request flag CSIIF10 is set and CSOT10 is cleared to 0 Then the next communication is enabled Caution Do not access the control register...

Page 320: ...igure 15 4 Timing in 3 Wire Serial I O Mode 2 2 2 Transmission reception timing Type 2 TRMD10 1 DIR10 0 CKP10 0 DAP10 1 ABH 56H ADH 5AH B5H 6AH D5H SCK10 SOTB10 SIO10 CSOT10 CSIIF10 SO10 SI10 input AAH AAH 55H communication data 55H is written to SOTB10 Read write trigger INTCSI10 ...

Page 321: ...O10 SI10 capture CSIIF10 CSOT10 b Type 2 CKP10 0 DAP10 1 D7 D6 D5 D4 D3 D2 D1 D0 SCK10 SO10 Writing to SOTB10 or reading from SIO10 SI10 capture CSIIF10 CSOT10 c Type 3 CKP10 1 DAP10 0 D7 D6 D5 D4 D3 D2 D1 D0 SCK10 SO10 Writing to SOTB10 or reading from SIO10 SI10 capture CSIIF10 CSOT10 d Type 4 CKP10 1 DAP10 1 D7 D6 D5 D4 D3 D2 D1 D0 SCK10 SO10 Writing to SOTB10 or reading from SIO10 SI10 capture...

Page 322: ...bit of the receive data is stored in the SIO10 register via the SI10 pin The second and subsequent bits are latched by the SIO10 register to the output latch at the next falling or rising edge of SCK10 and the data is output from the SO10 pin 2 When CKP10 0 DAP10 1 or CKP10 1 DAP10 1 SCK10 SOTB10 SIO10 SO10 Writing to SOTB10 or reading from SIO10 First bit 2nd bit 3rd bit Output latch The first bi...

Page 323: ...ue of the last bit Figure 15 7 Output Value of SO10 Pin Last Bit 1 Type 1 when CKP10 0 and DAP10 0 or CKP10 1 DAP10 0 SCK10 SOTB10 SIO10 SO10 Writing to SOTB10 or reading from SIO10 Next request is issued Last bit Output latch 2 Type 2 when CKP10 0 and DAP10 1 or CKP10 1 DAP10 1 SCK10 SOTB10 SIO10 SO10 Last bit Writing to SOTB10 or reading from SIO10 Next request is issued Output latch ...

Page 324: ...riority interrupts are generated If two or more interrupts with the same priority are generated simultaneously each interrupt is serviced according to its predetermined priority see Table 16 1 A standby release signal is generated Eight external interrupt requests and 15 internal interrupt requests are provided as maskable interrupts 2 Software interrupt This is a vectored interrupt generated by e...

Page 325: ...000 when compare register is specified TI010 pin valid edge detection when capture register is specified 0020H 15 INTTM010 Match between TM00 and CR010 when compare register is specified TI000 pin valid edge detection when capture register is specified 0022H 16 INTAD End of A D conversion 0024H 17 INTSR0 End of UART0 reception or reception error generation 0026H 18 INTWTI Watch timer reference tim...

Page 326: ...troller Vector table address generator Standby release signal B External maskable interrupt INTP0 to INTP6 Internal bus Interrupt request IF MK IE PR ISP Priority controller Vector table address generator Standby release signal External interrupt edge enable register EGP EGN Edge detector IF Interrupt request flag IE Interrupt enable flag ISP In service priority flag MK Interrupt mask flag PR Prio...

Page 327: ...le flag ISP In service priority flag MK Interrupt mask flag PR Priority specification flag KRM Key return mode register 16 3 Registers Controlling Interrupt Functions The following 6 types of registers are used to control the interrupt functions Interrupt request flag register IF0L IF0H IF1L Interrupt mask flag register MK0L MK0H MK1L Priority specification flag register PR0L PR0H PR1L External in...

Page 328: ...PMK4 PPR4 INTP5 PIF5 PMK5 PPR5 INTSRE6 SREIF6 SREMK6 SREPR6 INTSR6 SRIF6 IF0H SRMK6 MK0H SRPR6 PR0H INTST6 STIF6 STMK6 STPR6 INTCSI10 DUALIF0Note DUALMK0 DUALPR0 INTST0 INTTMH1 TMIFH1 TMMKH1 TMPRH1 INTTMH0 TMIFH0 TMMKH0 TMPRH0 INTTM50 TMIF50 TMMK50 TMPR50 INTTM000 TMIF000 TMMK000 TMPR000 INTTM010 TMIF010 TMMK010 TMPR010 INTAD ADIF IF1L ADMK MK1L ADPR PR1L INTSR0 SRIF0 SRMK0 SRPR0 INTWTI WTIIF WTIM...

Page 329: ...g Registers IF0L IF0H IF1L Address FFE0H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 IF0L SREIF6 PIF5 PIF4 PIF3 PIF2 PIF1 PIF0 LVIIF Address FFE1H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 IF0H TMIF010 TMIF000 TMIF50 TMIFH0 TMIFH1 DUALIF0 STIF6 SRIF6 Address FFE2H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 IF1L 0Note PIF6 WTIF KRIF TMIF51 WTIIF SRIF0 ADIF XXIFX Interrupt request flag 0 No interrup...

Page 330: ...anipulation instruction RESET input sets these registers to FFH Figure 16 3 Format of Interrupt Mask Flag Registers MK0L MK0H MK1L Address FFE4H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 MK0L SREMK6 PMK5 PMK4 PMK3 PMK2 PMK1 PMK0 LVIMK Address FFE5H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 MK0H TMMK010 TMMK000 TMMK50 TMMKH0 TMMKH1 DUALMK0 STMK6 SRMK6 Address FFE6H After reset FFH R W Symbol 7 6 ...

Page 331: ...16 bit memory manipulation instruction RESET input sets these registers to FFH Figure 16 4 Format of Priority Specification Flag Registers PR0L PR0H PR1L Address FFE8H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PR0L SREPR6 PPR5 PPR4 PPR3 PPR2 PPR1 PPR0 LVIPR Address FFE9H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PR0H TMPR010 TMPR000 TMPR50 TMPRH0 TMPRH1 DUALPRO STPR6 SRPR6 Address FFEAH After re...

Page 332: ... Register EGN Address FF48H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 EGP 0 EGP6 EGP5 EGP4 EGP3 EGP2 EGP1 EGP0 Address FF49H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 EGN 0 EGN6 EGN5 EGN4 EGN3 EGN2 EGN1 EGN0 EGPn EGNn INTPn pin valid edge selection n 0 to 6 0 0 Interrupt disabled 0 1 Falling edge 1 0 Rising edge 1 1 Both rising and falling edges Table 16 3 shows the ports corresponding to EGPn a...

Page 333: ...ly saved into a stack and the IE flag is reset to 0 If a maskable interrupt request is acknowledged the contents of the priority specification flag of the acknowledged interrupt are transferred to the ISP flag The PSW contents are also saved into the stack with the PUSH PSW instruction They are restored from the stack with the RETI RETB and POP PSW instructions RESET input sets PSW to 02H Figure 1...

Page 334: ...um TimeNote When PR 0 7 clocks 32 clocks When PR 1 8 clocks 33 clocks Note If an interrupt request is generated just before a divide instruction the wait time becomes longer Remark 1 clock 1 fCPU fCPU CPU clock If two or more maskable interrupt requests are generated simultaneously the request with a higher priority level specified in the priority specification flag is acknowledged first If two or...

Page 335: ...uest held pending Interrupt request held pending Interrupt request held pending Interrupt request held pending Interrupt request held pending Vectored interrupt servicing Any high priority interrupt request among those simultaneously generated Any high priority interrupt request among those simultaneously generated with PR 0 IF Interrupt request flag MK Interrupt mask flag PR Priority specificatio...

Page 336: ...terrupt servicing program CPU processing IF PR 1 IF PR 0 6 clocks 25 clocks Remark 1 clock 1 fCPU fCPU CPU clock 16 4 2 Software interrupt request acknowledgement A software interrupt request is acknowledged by BRK instruction execution Software interrupts cannot be disabled If a software interrupt request is acknowledged the contents are saved into the stacks in the order of the program status wo...

Page 337: ...priority lower than that of the interrupt currently being serviced is generated during interrupt servicing it is not acknowledged for multiple interrupt servicing Interrupt requests that are not enabled because interrupts are in the interrupt disabled state or because they have a lower priority are held pending When servicing of the current interrupt ends the pending interrupt request is acknowled...

Page 338: ...nowledged the EI instruction must always be issued to enable interrupt request acknowledgement Example 2 Multiple interrupt servicing does not occur due to priority control Main processing INTxx servicing INTyy servicing INTxx PR 0 INTyy PR 1 EI RETI IE 0 IE 0 EI 1 instruction execution RETI IE 1 IE 1 Interrupt request INTyy issued during servicing of interrupt INTxx is not acknowledged because it...

Page 339: ...EI 1 instruction execution RETI RETI INTxx PR 0 INTyy PR 0 IE 0 IE 0 IE 1 IE 1 Interrupts are not enabled during servicing of interrupt INTxx EI instruction is not issued therefore interrupt request INTyy is not acknowledged and multiple interrupt servicing does not take place The INTyy interrupt request is held pending and is acknowledged following execution of one main processing instruction PR ...

Page 340: ...IF0L IF0H IF1L MK0L MK0H MK1L PR0L PR0H and PR1L registers Caution The BRK instruction is not one of the above listed interrupt request hold instructions However the software interrupt activated by executing the BRK instruction causes the IE flag to be cleared to 0 Therefore even if a maskable interrupt request is generated during execution of the BRK instruction the interrupt request is not ackno...

Page 341: ... in 1 bit units KRM2 Controls KR2 signal in 1 bit units KRM3 Controls KR3 signal in 1 bit units KRM4 Controls KR4 signal in 1 bit units KRM5 Controls KR5 signal in 1 bit units KRM6 Controls KR6 signal in 1 bit units KRM7 Controls KR7 signal in 1 bit units 17 2 Configuration of Key Interrupt The key interrupt consists of the following hardware Table 17 2 Configuration of Key Interrupt Item Configur...

Page 342: ...RM KRM7 Does not detect key interrupt signal Detects key interrupt signal KRMn 0 1 Key interrupt mode control KRM KRM6 KRM5 KRM4 KRM3 KRM2 KRM1 KRM0 Address FF6EH After reset 00H R W Symbol 7 6 5 4 3 2 0 Cautions 1 If any of the KRM0 to KRM7 bits used is set to 1 set bits 0 to 7 PU70 to PU77 of the corresponding pull up resistor register 7 PU7 to 1 2 If KRM is changed the interrupt request flag ma...

Page 343: ...quest it enables intermittent operations to be carried out However because a wait time is required to secure the oscillation stabilization time after the STOP mode is released select the HALT mode if it is necessary to start processing immediately upon interrupt request generation In either of these two modes all the contents of registers flags and data memory just before the standby mode is set a...

Page 344: ...k is selected as CPU clock when STOP instruction is executed Ring OSC clock X1 input clock X1 input clock is selected as CPU clock when STOP instruction is executed STOP mode release STOP mode Operation stopped 17 fR Clock switched by software Ring OSC clock X1 input clock HALT status oscillation stabilization time set by OSTS X1 input clock ...

Page 345: ...8 bit memory manipulation instruction When reset is released reset by RESET input POC LVI clock monitor and WDT STOP instruction MSTOP 1 and MCC 1 clear OSTC to 00H Figure 18 2 Format of Oscillation Stabilization Time Counter Status Register OSTC Address FFA3H After reset 00H R Symbol 7 6 5 4 3 2 1 0 OSTC 0 0 0 MOST11 MOST13 MOST14 MOST15 MOST16 MOST11 MOST13 MOST14 MOST15 MOST16 Oscillation stabi...

Page 346: ...µs 0 1 0 213 fX 819 2 µs 0 1 1 214 fX 1 64 ms 1 0 0 215 fX 3 27 ms 1 0 1 216 fX 6 55 ms Other than above Setting prohibited Cautions 1 If the STOP mode is entered and then released while the Ring OSC clock is being used as the CPU clock set the oscillation stabilization time as follows Desired OSTC oscillation stabilization time Oscillation stabilization time set by OSTS The X1 oscillation stabili...

Page 347: ... stopped 8 bit timer event counter 50 Operable Operable only when TI50 is selected as the count clock 8 bit timer event counter 51 Operable Operable only when TI51 is selected as the count clock 8 bit timer H0 Operable Operable only when TO50 is selected as the count clock during 8 bit timer event counter 50 operation 8 bit timer H1 Operable Operable only when fR 2 7 is selected as the count clock...

Page 348: ...rable only when TO50 is selected as the count clock during 8 bit timer event counter 50 operation 8 bit timer H1 Operable Operable only when the X1 input clock is selected as the count clock Operable only when fR 2 7 is selected as the count clock Operation stopped Watch timer Operable Operable only when subsystem clock is selected Ring OSC cannot be stoppedNote 2 Operable Operable Watchdog timer ...

Page 349: ... is disabled the next address instruction is executed Figure 18 4 HALT Mode Release by Interrupt Request Generation HALT instruction Wait Wait Operating mode HALT mode Operating mode Oscillation X1 input clock Ring OSC clock or subsystem clock CPU clock Standby release signal Interrupt request Remarks 1 The broken lines indicate the case when the interrupt request which has released the standby mo...

Page 350: ... time 211 fX to 216 fX Ring OSC clock 17 fR 2 When Ring OSC clock or subsystem clock is used as CPU clock HALT instruction RESET signal Ring OSC clock or subsystem clock Operating mode HALT mode Reset period Operation stopped Operating mode Oscillates Oscillation stopped Oscillates CPU clock Ring OSC clock 17 fR Ring OSC clock or subsystem clock Remarks 1 fX X1 input clock oscillation frequency 2 ...

Page 351: ...ation is stopped Clock supply to the CPU is stopped CPU Operation stopped Port latch Status before STOP mode was set is retained 16 bit timer event counter 00 Operation stopped 8 bit timer event counter 50 Operable only when TI50 is selected as the count clock 8 bit timer event counter 51 Operable only when TI51 is selected as the count clock 8 bit timer H0 Operable only when TO50 is selected as t...

Page 352: ...TOP Mode Release by Interrupt Request Generation 1 When X1 input clock is used as CPU clock Operating mode Operating mode Oscillates Oscillates STOP instruction STOP mode Wait set by OSTS Standby release signal Oscillation stabilization wait status Oscillation stopped X1 input clock CPU clock Oscillation stabilization time set by OSTS X1 input clock X1 input clock 2 When Ring OSC clock is used as ...

Page 353: ... clock X1 input clock Oscillation stabilization time 211 fX to 216 fX Ring OSC clock 17 fR Oscillation stopped 2 When Ring OSC clock is used as CPU clock STOP instruction RESET signal Ring OSC clock Operating mode STOP mode Reset period Operation stopped Operating mode Oscillates Oscillation stopped Oscillates CPU clock Ring OSC clock 17 fR Ring OSC clock Table 18 5 Operation After STOP Mode Relea...

Page 354: ...or during the oscillation stabilization time just after reset release except for P130 which is low level output When a high level is input to the RESET pin the reset is released and program execution starts using the Ring OSC clock after the CPU clock operation has stopped for 17 fR s A reset generated by the watchdog timer and clock monitor sources is automatically released after the reset and pr...

Page 355: ... reset signal CLMRESB Clock monitor reset signal RESET POCRESB Power on clear circuit reset signal LVIRESB Low voltage detector reset signal Reset signal Reset signal Reset signal to LVIM LVIS register Clear Set Set Clear Clear Set Caution An LVI circuit internal reset does not reset the LVI circuit Remarks 1 LVIM Low voltage detection register 2 LVIS Low voltage detection level selection register...

Page 356: ...n stop 17 fR Normal operation Reset processing Ring OSC clock CPU clock Caution A watchdog timer internal reset resets the watchdog timer Figure 19 4 Timing of Reset in STOP Mode by RESET Input Delay Delay Hi ZNote Normal operation X1 RESET Internal reset signal Port pin Stop status Oscillation stop STOP instruction execution Reset period Oscillation stop Operation stop 17 fR Normal operation Rese...

Page 357: ...ister OSTC 00H Timer counter 00 TM00 0000H Capture compare registers 000 010 CR000 CR010 0000H Mode control register 00 TMC00 00H Prescaler mode register 00 PRM00 00H Capture compare control register 00 CRC00 00H 16 bit timer event counter 00 Timer output control register 00 TOC00 00H Timer counters 50 51 TM50 TM51 00H Compare registers 50 51 CR50 CR51 00H Timer clock selection registers 50 51 TCL...

Page 358: ...ection register 6 CKSR6 00H Baud rate generator control register 6 BRGC6 FFH Serial interface UART6 Asynchronous serial interface control register 6 ASICL6 16H Transmit buffer register 10 SOTB10 Undefined Serial I O shift register 10 SIO10 00H Serial operation mode register 10 CSIM10 00H Serial interface CSI10 Serial clock selection register 10 CSIC10 00H Key interrupt Key return mode register KRM...

Page 359: ...nternal reset request is not generated or RESF is cleared 1 Internal reset request is generated CLMRF Internal reset request by clock monitor CLM 0 Internal reset request is not generated or RESF is cleared 1 Internal reset request is generated LVIRF Internal reset request by low voltage detector LVI 0 Internal reset request is not generated or RESF is cleared 1 Internal reset request is generated...

Page 360: ... under the following conditions In STOP mode and during the oscillation stabilization time When the X1 input clock is stopped by software when MSTOP 1 or MCC 1 During the oscillation stabilization time after reset is released When the Ring OSC clock is stopped Remark MSTOP Bit 7 of the main OSC control register MOC 20 2 Configuration of Clock Monitor Clock monitor consists of the following hardwar...

Page 361: ... 7 0 CLME 0 1 Symbol CLM Address FFA9H After reset 00H R W 6 0 Disables clock monitor operation Enables clock monitor operation 5 0 4 0 3 0 Enables disables clock monitor operation 2 0 1 0 0 CLME Cautions 1 Once bit 0 CLME is set to 1 it cannot be cleared to 0 except by RESET input or the internal reset signal 2 If the reset signal is generated by the clock monitor CLME is cleared to 0 and bit 1 C...

Page 362: ...topped Remark MSTOP Bit 7 of the main OSC control register MOC Table 20 2 Operation Status of Clock Monitor When CLME 1 CPU Operation Clock Operation Mode X1 Input Clock Status Ring OSC Clock Status Clock Monitor Status Oscillating STOP mode Stopped StoppedNote Oscillating RESET input StoppedNote Stopped Oscillating Operating X1 input clock HALT mode Oscillating StoppedNote Stopped STOP mode RESET...

Page 363: ...are 2 Clock monitor status after STOP mode is released CLME 1 is set when CPU clock operates on X1 input clock and before entering STOP mode Clock monitor status Monitoring Monitoring stopped Monitoring CLME Ring OSC clock X1 input clock CPU operation Normal operation STOP Oscillation stabilization time Normal operation Oscillation stopped Oscillation stabilization time set by OSTS register When b...

Page 364: ... stopped in STOP mode and during the oscillation stabilization time 4 Clock monitor status after RESET input CLME 1 is set after RESET input and during X1 input clock oscillation stabilization time CPU operation Clock monitor status CLME Ring OSC clock X1 input clock Reset Oscillation stopped Oscillation stabilization time Normal operation Clock supply stopped Normal operation Ring OSC clock Monit...

Page 365: ...itor status CLME RESET Ring OSC clock X1 input clock Reset Oscillation stabilization time Normal operation Clock supply stopped Normal operation Ring OSC clock Monitoring Monitoring stopped Monitoring 17 clocks Set to 1 by software RESET input clears bit 0 CLME of the clock monitor mode register CLM to 0 and stops the clock monitor operation When CLME is set to 1 by software at the end of the osci...

Page 366: ...ion voltage VPOC 3 5 V 0 2 V Caution If an internal reset signal is generated in the POC circuit the reset control flag register RESF is cleared to 00H Remark This product incorporates multiple hardware functions that generate an internal reset signal A flag that indicates the reset cause is located in the reset control flag register RESF for when an internal reset signal is generated by the watch...

Page 367: ...er on Clear Circuit Detection voltage source VPOC Internal reset signal VDD VDD 21 3 Operation of Power on Clear Circuit In the power on clear circuit the supply voltage VDD and detection voltage VPOC are compared and when VDD VPOC an internal reset signal is generated Figure 21 2 Timing of Internal Reset Signal Generation in Power on Clear Circuit Time Supply voltage VDD POC detection voltage VPO...

Page 368: ...oltage fluctuation is 50 ms or less in vicinity of POC detection voltage Yes Power on clear The Ring OSC clock is set as the CPU clock when the reset signal is generated The cause of reset power on clear WDT LVI or clock monitor can be identified by the RESF register Change the CPU clock from the Ring OSC clock to the X1 input clock Check the stabilization of oscillation of the X1 input clock by u...

Page 369: ...ssing After Release of Reset 2 2 Checking reset cause Yes No Check reset cause Power on clear external reset generated Reset processing by watchdog timer Reset processing by clock monitor Reset processing by low voltage detector No No WDTRF of RESF register 1 CLMRF of RESF register 1 LVIRF of RESF register 1 Yes Yes ...

Page 370: ... software Operable in STOP mode When the low voltage detector is used to reset bit 0 LVIRF of the reset control flag register RESF is set to 1 if reset occurs For details of RESF refer to CHAPTER 19 RESET FUNCTION 22 2 Configuration of Low Voltage Detector The block diagram of the low voltage detector is shown below Figure 22 1 Block Diagram of Low Voltage Detector LVIS1 LVIS0 LVION LVIE Detection...

Page 371: ...inary User s Manual U16315EJ1V0UD 371 22 3 Registers Controlling Low Voltage Detector The low voltage detector is controlled by the following registers Low voltage detection register LVIM Low voltage detection level selection register LVIS ...

Page 372: ...g 0 Supply voltage VDD detection voltage VLVI or when operation is disabled 1 Supply voltage VDD detection voltage VLVI Notes 1 Bit 0 is read only 2 LVION LVIE and LVIMD are cleared to 0 at a reset other than an LVI reset These are not cleared to 0 at an LVI reset 3 When LVION is set to 1 operation of the comparator in the LVI circuit is started Use software to instigate a wait of at least 0 2 ms ...

Page 373: ...IS 0 LVIS0 1 LVIS1 2 LVIS2 3 0 4 0 5 0 6 0 7 0 Symbol LVIS Address FFBFH After reset 00H R W LVIS2 LVIS1 LVIS0 Detection level 0 0 0 VLVI0 4 3 V 0 2 V 0 0 1 VLVI1 4 1 V 0 2 V 0 1 0 VLVI2 3 9 V 0 2 V 0 1 1 VLVI3 3 7 V 0 2 V 1 0 0 VLVI4 3 5 V 0 2 V Note 1 0 1 VLVI5 3 3 V 0 15 V Note 1 1 0 VLVI6 3 1 V 0 15 V Note 1 1 1 Setting prohibited Note When the detection voltage of the POC circuit is specified...

Page 374: ...les reference voltage generator operation 4 Use software to instigate a wait of at least 2 ms 5 Set bit 7 LVION of LVIM to 1 enables LVI operation 6 Use software to instigate a wait of at least 0 2 ms 7 Confirm that supply voltage VDD detection voltage VLVI at bit 0 LVIF of LVIM 8 Set bit 1 LVIMD of LVIM to 1 generates internal reset signal when supply voltage VDD detection voltage VLVI Cautions 1...

Page 375: ...tware Not cleared Not cleared Not cleared Not cleared Not cleared Not cleared Cleared by software 2 1 5 7 8 Time Clear Clear Clear Clear 3 4 2 ms or longer 6 0 2 ms or longer LVIMK flag set by software LVIE flag set by software LVION flag set by software LVIMD flag set by software Note LVIRF is bit 0 of the reset control flag register RESF For details of RESF refer to CHAPTER 19 RESET FUNCTION Rem...

Page 376: ...ION of LVIM to 1 enables LVI operation 6 Use software to instigate a wait of at least 0 2 ms 7 Confirm that supply voltage VDD detection voltage VLVI at bit 0 LVIF of LVIM 8 Clear the interrupt request flag of LVI LVIIF to 0 9 Release the interrupt mask flag of LVI LVIMK 10 Execute the EI instruction when vector interrupts are used Caution If use POC is selected by a mask option procedures 3 and 4...

Page 377: ... POC detection voltage VPOC 2 7 V Time LVIF flag INTLVI LVIIF flag Internal reset signal 2 1 5 7 8 Cleared by software 3 4 2 ms or longer 9 Cleared by software 6 0 2 ms or longer LVIMK flag set by software LVIE flag set by software LVION flag set by software Remark 1 to 9 in Figure 22 5 above correspond to 1 to 9 in the description of when starting operation in 22 4 2 When used as interrupt ...

Page 378: ...stem may be repeatedly reset and released from the reset status In this case the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking action 1 below 2 When used as interrupt Interrupt requests may be frequently generated Take action 2 below In this system take the following actions Action 1 When used as reset After releasing the reset sig...

Page 379: ...rom the Ring OSC clock to the X1 input clock Check the stabilization of oscillation of the X1 input clock by using the OSTC register TMIFH1 1 Interrupt request is generated Initialization of ports 8 bit timer H1 can operate with the Ring OSC clock Source fR 240 kHz 27 compare 100 53 ms fR Ring OSC clock oscillation frequency No Note 1 Reset Checking cause of resetNote 2 Check stabilization of osci...

Page 380: ...sing After Release of Reset 2 2 Checking reset cause Yes No Check reset cause Power on clear external reset generated Reset processing by watchdog timer Reset processing by clock monitor Reset processing by low voltage detector No Yes WDTRF of RESF register 1 CLMRF of RESF register 1 LVIRF of RESF register 1 Yes No ...

Page 381: ...e LVI detection voltage disable interrupts DI wait for the supply voltage fluctuation period check that supply voltage VDD detection voltage VLVI with the LVIF flag and then enable interrupts EI Figure 22 7 Example of Software Processing of LVI Interrupt If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage Check that supply voltage VDD detection voltage VLVI TMIFH1 1...

Page 382: ...g the reset period In STOP mode In HALT mode when the CPU is operating on the subsystem clock Figure 23 1 shows the block diagram of the periphery of the regulator Figure 23 1 Block Diagram of Regulator Periphery EVDD system I O buffer Internal digital circuits Bidirectional level shifter A D converter Flash memory PD78F0124 only Regulator X1 Ring sub oscillator VDD REGC VPP 0 1 F AVREF EVDD µ µ R...

Page 383: ...rated in 1 bit units Pull up resistors are not available for the flash memory versions Flash memory versions that support the mask options of the mask ROM versions are as follows Table 24 1 Flash Memory Versions Supporting Mask Options of Mask ROM Versions Mask Option POC Circuit Ring OSC Flash Memory Version Cannot be stopped µPD78F0124M1 POC cannot be used Can be stopped by software µPD78F0124M2...

Page 384: ... 8 KB µPD780122 16 KB µPD780123 24 KB µPD780124 32 KB Internal high speed RAM capacity 1024 bytesNote µPD780121 512 bytes µPD780122 512 bytes µPD780123 1024 bytes µPD780124 1024 bytes IC pin None Available VPP pin Available None Electrical specifications Refer to CHAPTER 27 ELECTRICAL SPECIFICATIONS TARGET VALUES Note The same capacity as the mask ROM versions can be specified by means of the inte...

Page 385: ...al Memory Size Switching Register IMS Address FFF0H After reset CFH R W Symbol 7 6 5 4 3 2 1 0 IMS RAM2 RAM1 RAM0 0 ROM3 ROM2 ROM1 ROM0 RAM2 RAM1 RAM0 Internal high speed RAM capacity selection 0 1 0 512 bytes 1 1 0 1024 bytes Other than above Setting prohibited ROM3 ROM2 ROM1 ROM0 Internal ROM capacity selection 0 0 1 0 8 KB 0 1 0 0 16 KB 0 1 1 0 24 KB 1 0 0 0 32 KB Other than above Setting prohi...

Page 386: ...ble 25 3 For the selection of the communication mode a format like the one shown in Figure 25 2 is used The communication mode is selected according to the number of VPP pulses shown in Table 25 3 Table 25 3 Communication Mode List Communication Mode Number of Channels Pin UsedNote Number of VPP Pulses SCK10 TxD0 P10 SI10 RxD0 P11 SO10 P12 0 3 wire serial I O 1 SCK10 TxD0 P10 SI10 RxD0 P11 SO10 P1...

Page 387: ...verify Compares entire memory contents and input data Batch erase Erases the entire memory contents Batch blank check Checks the erase status of the entire memory High speed write Performs writing to flash memory according to write start address and number of write data bytes Continuous write Performs successive write operations using the data input with high speed write operation Status Checks th...

Page 388: ...erial I O Mode VPP VDD RESET SCK SO SI GND VPP VDD EVDD AVREF RESET SCK10 SI10 SO10 VSS EVSS AVSS Flashpro III Flashpro IV PD78F0124 µ Figure 25 4 Connection of Flashpro III Flashpro IV in 3 Wire Serial I O Mode Using Handshake VPP VDD RESET SCK SO SI GND VPP VDD EVDD AVREF RESET SCK10 SI10 SO10 HS HS P15 VSS EVSS AVSS Flashpro III Flashpro IV PD78F0124 µ Caution Be sure to connect the REGC pin of...

Page 389: ...andshake VPP VDD RESET SO SI GND VPP VDD EVDD AVREF RESET RxD0 TxD0 HS HS P15 VSS EVSS AVSS Flashpro III Flashpro IV PD78F0124 µ Figure 25 7 Connection of Flashpro III Flashpro IV in UART UART6 Mode VPP VDD RESET SO SI GND VPP VDD EVDD AVREF RESET RxD6 TxD6 VSS EVSS AVSS Flashpro III Flashpro IV PD78F0124 µ Caution Be sure to connect the REGC pin of the µ µ µ µPD78F0124 in either of the following ...

Page 390: ...iring Adapter for Flash Memory Writing in 3 Wire Serial I O Mode GND VDD LVDD VDD2 SI SO SCK CLKOUT RESET VPP RESERVE HS WRITER INTERFACE VDD 2 7 to 5 5 V GND 52 51 50 49 48 47 46 45 44 43 42 14 15 16 17 18 19 20 21 21 23 24 39 38 37 36 35 34 33 32 31 30 29 1 2 3 4 5Note 6 7 8 9 10 11 12 13 28 27 41 40 25 26 PD78F0124 µ Note Be sure to connect the REGC pin in either of the following two ways Conne...

Page 391: ...DD LVDD VDD2 SI SO SCK CLKOUT RESET VPP RESERVE HS WRITER INTERFACE VDD 2 7 to 5 5 V GND 52 51 50 49 48 47 46 45 44 43 42 14 15 16 17 18 19 20 21 21 23 24 39 38 37 36 35 34 33 32 31 30 29 1 2 3 4 5Note 6 7 8 9 10 11 12 13 28 27 41 40 25 26 PD78F0124 µ Note Be sure to connect the REGC pin in either of the following two ways Connect to GND via 0 1 µF capacitor Connect directly to VDD ...

Page 392: ...2 SI SO SCK CLKOUT RESET VPP RESERVE HS WRITER INTERFACE VDD 2 7 to 5 5 V GND 52 51 50 49 48 47 46 45 44 43 42 14 15 16 17 18 19 20 21 21 23 24 39 38 37 36 35 34 33 32 31 30 29 1 2 3 4 5Note 6 7 8 9 10 11 12 13 28 27 41 40 25 26 PD78F0124 µ Note Be sure to connect the REGC pin in either of the following two ways Connect to GND via 0 1 µF capacitor Connect directly to VDD ...

Page 393: ...LVDD VDD2 SI SO SCK CLKOUT RESET VPP RESERVE HS WRITER INTERFACE VDD 2 7 to 5 5 V GND 52 51 50 49 48 47 46 45 44 43 42 14 15 16 17 18 19 20 21 21 23 24 39 38 37 36 35 34 33 32 31 30 29 1 2 3 4 5Note 6 7 8 9 10 11 12 13 28 27 41 40 25 26 PD78F0124 µ Note Be sure to connect the REGC pin in either of the following two ways Connect to GND via 0 1 µF capacitor Connect directly to VDD ...

Page 394: ...2 SI SO SCK CLKOUT RESET VPP RESERVE HS WRITER INTERFACE VDD 2 7 to 5 5 V GND 52 51 50 49 48 47 46 45 44 43 42 14 15 16 17 18 19 20 21 21 23 24 39 38 37 36 35 34 33 32 31 30 29 1 2 3 4 5Note 6 7 8 9 10 11 12 13 28 27 41 40 25 26 PD78F0124 µ Note Be sure to connect the REGC pin in either of the following two ways Connect to GND via 0 1 µF capacitor Connect directly to VDD ...

Page 395: ...l When using a label be sure to write the and symbols For operand register identifiers r and rp either function names X A C etc or absolute names names in parentheses in the table below R0 R1 R2 etc can be used for specification Table 26 1 Operand Identifiers and Specification Methods Identifier Specification Method r rp sfr sfrp X R0 A R1 C R2 B R3 E R4 D R5 L R6 H R7 AX RP0 BC RP1 DE RP2 HL RP3 ...

Page 396: ...lag AC Auxiliary carry flag Z Zero flag RBS Register bank select flag IE Interrupt request enable flag NMIS Non maskable interrupt servicing flag Memory contents indicated by address or register contents in parentheses XH XL Higher 8 bits and lower 8 bits of 16 bit register Logical product AND Logical sum OR Exclusive logical sum exclusive OR Inverted data addr16 16 bit immediate data or label jdi...

Page 397: ... HL B A 1 6 7 m HL B A A HL C 1 6 7 n A HL C MOV HL C A 1 6 7 m HL C A A r Note 3 1 2 A r A saddr 2 4 6 A saddr A sfr 2 6 A sfr A addr16 3 8 10 n m A addr16 A DE 1 4 6 n m A DE A HL 1 4 6 n m A HL A HL byte 2 8 10 n m A HL byte A HL B 2 8 10 n m A HL B 8 bit data transfer XCH A HL C 2 8 10 n m A HL C Notes 1 When the internal high speed RAM area is accessed or for an instruction with no data acces...

Page 398: ...2 8 9 n A CY A HL B ADD A HL C 2 8 9 n A CY A HL C A byte 2 4 A CY A byte CY saddr byte 3 6 8 saddr CY saddr byte CY A r Note 4 2 4 A CY A r CY r A 2 4 r CY r A CY A saddr 2 4 5 A CY A saddr CY A addr16 3 8 9 n A CY A addr16 CY A HL 1 4 5 n A CY A HL CY A HL byte 2 8 9 n A CY A HL byte CY A HL B 2 8 9 n A CY A HL B CY 8 bit operation ADDC A HL C 2 8 9 n A CY A HL C CY Notes 1 When the internal hig...

Page 399: ... 4 5 n A CY A HL CY A HL byte 2 8 9 n A CY A HL byte CY A HL B 2 8 9 n A CY A HL B CY SUBC A HL C 2 8 9 n A CY A HL C CY A byte 2 4 A A byte saddr byte 3 6 8 saddr saddr byte A r Note 3 2 4 A A r r A 2 4 r r A A saddr 2 4 5 A A saddr A addr16 3 8 9 n A A addr16 A HL 1 4 5 n A A HL A HL byte 2 8 9 n A A HL byte A HL B 2 8 9 n A A HL B 8 bit operation AND A HL C 2 8 9 n A A HL C Notes 1 When the int...

Page 400: ...A HL A HL byte 2 8 9 n A A HL byte A HL B 2 8 9 n A A HL B XOR A HL C 2 8 9 n A A HL C A byte 2 4 A byte saddr byte 3 6 8 saddr byte A r Note 3 2 4 A r r A 2 4 r A A saddr 2 4 5 A saddr A addr16 3 8 9 n A addr16 A HL 1 4 5 n A HL A HL byte 2 8 9 n A HL byte A HL B 2 8 9 n A HL B 8 bit operation CMP A HL C 2 8 9 n A HL C Notes 1 When the internal high speed RAM area is accessed or for an instructio...

Page 401: ...L 3 0 A3 0 HL 7 4 HL 3 0 ADJBA 2 4 Decimal Adjust Accumulator after Addition BCD adjustment ADJBS 2 4 Decimal Adjust Accumulator after Subtract CY saddr bit 3 6 7 CY saddr bit CY sfr bit 3 7 CY sfr bit CY A bit 2 4 CY A bit CY PSW bit 3 7 CY PSW bit CY HL bit 2 6 7 n CY HL bit saddr bit CY 3 6 8 saddr bit CY sfr bit CY 3 8 sfr bit CY A bit CY 2 4 A bit CY PSW bit CY 3 8 PSW bit CY Bit manipulate M...

Page 402: ...it saddr bit 2 4 6 saddr bit 1 sfr bit 3 8 sfr bit 1 A bit 2 4 A bit 1 PSW bit 2 6 PSW bit 1 SET1 HL bit 2 6 8 n m HL bit 1 saddr bit 2 4 6 saddr bit 0 sfr bit 3 8 sfr bit 0 A bit 2 4 A bit 0 PSW bit 2 6 PSW bit 0 CLR1 HL bit 2 6 8 n m HL bit 0 SET1 CY 1 2 CY 1 1 CLR1 CY 1 2 CY 0 0 Bit manipulate NOT1 CY 1 2 CY CY Notes 1 When the internal high speed RAM area is accessed or for an instruction with...

Page 403: ...W 1 2 SP 1 PSW SP SP 1 PUSH rp 1 4 SP 1 rpH SP 2 rpL SP SP 2 PSW 1 2 PSW SP SP SP 1 R R R POP rp 1 4 rpH SP 1 rpL SP SP SP 2 SP word 4 10 SP word SP AX 2 8 SP AX Stack manipulate MOVW AX SP 2 8 AX SP addr16 3 6 PC addr16 addr16 2 6 PC PC 2 jdisp8 Unconditional branch BR AX 2 8 PCH A PCL X BC addr16 2 6 PC PC 2 jdisp8 if CY 1 BNC addr16 2 6 PC PC 2 jdisp8 if CY 0 BZ addr16 2 6 PC PC 2 jdisp8 if Z 1...

Page 404: ...jdisp8 if A bit 1 then reset A bit PSW bit addr16 4 12 PC PC 4 jdisp8 if PSW bit 1 then reset PSW bit BTCLR HL bit addr16 3 10 12 n m PC PC 3 jdisp8 if HL bit 1 then reset HL bit B addr16 2 6 B B 1 then PC PC 2 jdisp8 if B 0 C addr16 2 6 C C 1 then PC PC 2 jdisp8 if C 0 Conditional branch DBNZ saddr addr16 3 8 10 saddr saddr 1 then PC PC 3 jdisp8 if saddr 0 SEL RBn 2 4 RBS1 0 n NOP 1 2 No Operatio...

Page 405: ...r16 1 None A ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP ROR ROL RORC ROLC r MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP INC DEC B C DBNZ sfr MOV MOV saddr MOV ADD ADDC SUB SUBC AND OR XOR ...

Page 406: ...rp MOVW MOVW addr16 MOVW SP MOVW MOVW Note Only when rp BC DE HL 3 Bit manipulation instructions MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 BT BF BTCLR Second Operand First Operand A bit sfr bit saddr bit PSW bit HL bit CY addr16 None A bit MOV1 BT BF BTCLR SET1 CLR1 sfr bit MOV1 BT BF BTCLR SET1 CLR1 saddr bit MOV1 BT BF BTCLR SET1 CLR1 PSW bit MOV1 BT BF BTCLR SET1 CLR1 HL bit MOV1 BT BF BTCLR SET1 CLR1 ...

Page 407: ...ch instructions CALL CALLF CALLT BR BC BNC BZ BNZ BT BF BTCLR DBNZ Second Operand First Operand AX addr16 addr11 addr5 addr16 Basic instruction BR CALL BR CALLF CALLT BR BC BNC BZ BNZ Compound instruction BT BF BTCLR DBNZ 5 Other instructions ADJBA ADJBS BRK RET RETI RETB SEL NOP EI DI HALT STOP ...

Page 408: ...On chip pull up resistor 0 3 to VDD 0 3Note 1 V Input voltage VI3 VPP in flash programming mode µPD78F0124 only 0 3 to 10 5 V Output voltage VO 0 3 to VDD 0 3Note 1 V Analog input voltage VAN AVSS 0 3 to AVREF 0 3Note 1 and 0 3 to VDD 0 3Note 1 V Per pin 10 mA P00 to P03 P10 to P14 P70 to P77 30 mA Output current high IOH Total of all pins 60 mA P15 to P17 P30 to P33 P60 to P63 P120 P130 P140 30 m...

Page 409: ...tten When supply voltage rises VPP must exceed VDD 10 µs or more after VDD has reached the lower limit value 2 7 V of the operating voltage range 15 µs if the supply voltage is dropped by the regulator see a in the figure below When supply voltage drops VDD must be lowered 10 µs or more after VPP falls below the lower limit value 2 7 V of the operating voltage range of VDD see b in the figure belo...

Page 410: ...y oscillator characteristics Refer to AC Characteristics for instruction execution time 2 When the REGC pin is connected to VSS via a 0 1 µF capacitor 3 Connect the REGC pin directly to VDD Cautions 1 When using the X1 oscillator wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance Keep the wiring length as short as possib...

Page 411: ...using the subsystem clock oscillator wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance Keep the wiring length as short as possible Do not cross the wiring with the other signal lines Do not route the wiring near a signal line through which a high fluctuating current flows Always make the ground point of the oscillator c...

Page 412: ... P77 4 0 V VDD 5 5 V 30 mA Total of P15 to P17 P30 to P33 P60 to P63 P120 P130 P140 4 0 V VDD 5 5 V 30 mA Output current low IOL All pins 2 7 V VDD 4 0 V 10 mA VIH1 P12 P13 P15 0 7VDD VDD V VIH2 P00 to P03 P10 P11 P14 P16 P17 P30 to P33 P70 to P77 P120 P140 RESET 0 8VDD VDD V VIH3 P20 to P27Note 0 7AVREF AVREF V VIH4 P60 P61 0 7VDD VDD V VIH5 P62 P63 0 7VDD 12 V Input voltage high VIH6 X1 X2 XT1 X...

Page 413: ...P70 to P77 P120 P130 P140 RESET 3 µA ILIH1 VI AVREF P20 to P27 3 µA ILIH2 VI VDD X1 X2 XT1 XT2 20 µA Input leakage current high ILIH3 VI 12 V P62 P63 N ch open drain 3 µA ILIL1 P00 to P03 P10 to P17 P20 to P27 P30 to P33 P60 P61 P70 to P77 P120 P130 P140 RESET 3 µA ILIL2 X1 X2 XT1 XT2 20 µA Input leakage current low ILIL3 VI 0 V P62 P63 N ch open drain 3Note µA Output leakage current high ILOH VO ...

Page 414: ...eral functions are operating 1 6 mA VDD 5 0 V 10 0 7 2 1 mA IDD3 Ring OSC operating modeNote 4 VDD 3 0 V 10 0 4 1 2 mA VDD 5 0 V 10 115 230 µA IDD4 32 768 kHz crystal oscillation operating modeNotes 4 6 VDD 3 0 V 10 95 190 µA VDD 5 0 V 10 30 60 µA IDD5 32 768 kHz crystal oscillation HALT modeNotes 4 6 VDD 3 0 V 10 6 18 µA POC OFF RING OFF 0 1 30 µA POC OFF RING ON 14 58 µA POC ONNote 5 RING OFF 3 ...

Page 415: ...pheral functions are operating 1 6 mA VDD 5 0 V 10 0 3 0 9 mA IDD3 Ring OSC operating modeNote 4 VDD 3 0 V 10 0 19 0 57 mA VDD 5 0 V 10 45 90 µA IDD4 32 768 kHz crystal oscillation operating modeNotes 4 6 VDD 3 0 V 10 25 50 µA VDD 5 0 V 10 30 60 µA IDD5 32 768 kHz crystal oscillation HALT modeNotes 4 6 VDD 3 0 V 10 6 18 µA POC OFF RING OFF 0 1 30 µA POC OFF RING ON 14 58 µA POC ONNote 5 RING OFF 3...

Page 416: ...m 0 1Note 3 µs TI000 TI010 input high level width low level width tTIH0 tTIL0 2 7 V VDD 4 0 V 2 fsam 0 2Note 3 µs 4 0 V VDD 5 5 V 10 TI50 TI51 input frequency fTI5 2 7 V VDD 4 0 V 5 MHz 4 0 V VDD 5 5 V 50 ns TI50 TI51 input high level width low level width tTIH5 tTIL5 2 7 V VDD 4 0 V 100 ns Interrupt input high level width low level width tINTH tINTL 1 µs 4 0 V VDD 5 5 V 50 ns Key return input low...

Page 417: ...a 0 1 µ µ µ µF capacitor 5 0 1 0 2 0 0 4 0 2 0 1 Supply voltage VDD V Cycle time T CY s 0 10 0 1 0 2 0 3 0 4 0 5 0 6 0 5 5 2 7 3 3 Guaranteed operation range 20 0 16 0 0 238 µ b When REGC pin is directly connected to VDD 5 0 1 0 2 0 0 4 0 2 0 1 Supply voltage VDD V Cycle time T CY s 0 10 0 1 0 2 0 3 0 4 0 5 0 6 0 5 5 2 7 3 3 Guaranteed operation range 20 0 16 0 0 238 µ ...

Page 418: ... MAX Unit 4 0 V VDD 5 5 V 200 ns 3 3 V VDD 4 0 V 240 ns SCK10 cycle time tKCY1 2 7 V VDD 3 3 V 400 ns SCK10 high low level width tKH1 tKL1 tKCY1 2 10 ns SI10 setup time to SCK10 tSIK1 30 ns SI10 hold time from SCK10 tKSI1 30 ns Delay time from SCK10 to SO10 output tKSO1 C 100 pFNote 30 ns Note C is the load capacitance of the SCK10 and SO10 output lines d 3 wire serial I O mode slave mode SCK10 ex...

Page 419: ... Timing Test Points Excluding X1 Input 0 8VDD 0 2VDD Test points 0 8VDD 0 2VDD Clock Timing X1 input VIH6 MIN VIL6 MAX 1 fXP tXPL tXPH 1 fXT tXTL tXTH XT1 input VIH6 MIN VIL6 MAX TI Timing TI00 TI010 tTIL0 tTIH0 TI50 TI51 1 fTI5 tTIL5 tTIH5 Interrupt Request Input Timing INTP0 to INTP6 tINTL tINTH ...

Page 420: ...FICATIONS TARGET VALUES Preliminary User s Manual U16315EJ1V0UD 420 RESET Input Timing RESET tRSL Serial Transfer Timing 3 wire serial I O mode SI10 SO10 tKCYm tKLm tKHm tSIKm tKSIm Input data tKSOm Output data SCK10 Remark m 1 2 ...

Page 421: ...AVREF 5 5 V 14 100 µs Conversion time tCONV 2 7 V AVREF 4 0 V 17 100 µs 4 0 V AVREF 5 5 V 0 4 FSR Zero scale errorNotes 1 2 2 7 V AVREF 4 0 V 0 6 FSR 4 0 V AVREF 5 5 V 0 4 FSR Full scale errorNotes 1 2 2 7 V AVREF 4 0 V 0 6 FSR 4 0 V AVREF 5 5 V 2 5 LSB Integral non linearity errorNote 1 2 7 V AVREF 4 0 V 4 5 LSB 4 0 V AVREF 5 5 V 1 5 LSB Differential non linearity errorNote 1 2 7 V AVREF 4 0 V 2 ...

Page 422: ... V VDD 0 V 2 7 V 0 0015 1500 ms Power supply rise time tPTH VDD 0 V 3 3 V 0 002 1800 ms Response delay time 1Note tPTHD When power supply rises after reaching detection voltage MAX 3 0 ms Response delay time 2Note tPD When power supply falls VDD 1 7 V 1 0 ms Minimum pulse width tPW 0 2 ms Note Time required from voltage detection to reset release POC Circuit Timing Supply voltage VDD Time Detectio...

Page 423: ...IT1 0 1 0 2 ms Notes 1 Time required from voltage detection to interrupt output or RESET output 2 Time required from setting LVIE to 1 to reference voltage stabilization when POC OFF is selected by the POC mask option 3 Time required from setting LVION to 1 to operation stabilization Remarks 1 VLVI0 VLVI1 VLVI2 VLVI3 VLVI4 VLVI5 VLVI6 2 VPOCn VLVIm n 0 1 m 0 to 6 LVI Circuit Timing Supply voltage ...

Page 424: ... When step write time 50 µs 1 word 1 byte 48 520 µs Number of rewrites per chipNote 7 Cerwr 1 erase 1 write after erase 1 rewrite 20 Times Notes 1 The recommended setting value of the step erase time is 0 2 s 2 The prewrite time before erasure and the erase verify time writeback time are not included 3 The recommended setting value of the writeback time is 50 ms 4 Writeback is executed once by the...

Page 425: ...PP tDP 10 µs Release time from VPP to RESET tPR 10 µs VPP pulse input start time from RESET tRP 2 ms VPP pulse high low level width tPW 8 µs VPP pulse input end time from RESET tRPE 20 ms VPP pulse low level input voltage VPPL 0 8VDD 1 2VDD V VPP pulse high level input voltage VPPH 9 7 10 0 10 3 V Flash Write Mode Setting Timing VDD VDD 0 V VDD RESET input 0 V VPPH 0 V VPP VPPL tRP tPR tDP tPW tPW...

Page 426: ...S N S J detail of lead end R K M I S L T P Q G F H 52 PIN PLASTIC LQFP 10x10 ITEM MILLIMETERS A B D G 12 0 0 2 10 0 0 2 0 13 1 1 I 12 0 0 2 J C 10 0 0 2 H 0 32 0 06 0 65 T P 1 0 0 2 K L 0 5 F 1 1 N P Q 0 10 1 4 0 1 0 05 T 0 25 S 1 5 0 1 U 0 6 0 15 S52GB 65 8ET 2 M 0 17 0 03 0 05 R 3 4 3 A B C D U ...

Page 427: ...ed illegal data may be passed if an access to the CPU conflicts with an access to the peripheral hardware When accessing the peripheral hardware that may cause a conflict therefore the CPU repeatedly executes processing until the correct data is passed As a result the CPU does not start the next instruction processing but waits If this happens the number of execution clocks of an instruction incre...

Page 428: ...DM 5 flag 0 ADCR Read 1 to 5 clocks when ADM 5 flag 1 1 to 9 clocks when ADM 5 flag 0 A D converter Calculating maximum number of wait clocks 1 fMACRO 2 1 fCPU 1 The result after the decimal point is truncated if it is less than tCPUL after it has been multiplied by 1 fCPU and is rounded up if it exceeds tCPUL fMACRO Macro operating frequency When bit 5 FR2 of ADM 1 fX 2 when bit 5 FR2 of ADM 0 fX...

Page 429: ...e a wait MOV A sfr 3 A D converter Table 29 2 Number of Wait Clocks and Number of Execution Clocks on Occurrence of Wait A D Converter On execution of MOV ADM A MOV ADS A or MOV A ADCR When fX 10 MHz tCPUL 50 ns Value of Bit 5 FR2 of ADM Register fCPU Number of Wait Clocks Number of Execution Clocks fX 9 clocks 14 clocks fX 2 5 clocks 10 clocks fX 22 3 clocks 8 clocks fX 23 2 clocks 7 clocks 0 fX ...

Page 430: ... shows the development tool configuration Support for PC98 NX series Unless otherwise specified products supported by IBM PC AT TM compatibles are compatible with PC98 NX series computers When using PC98 NX series computers refer to the explanation for IBM PC AT compatibles Windows Unless otherwise specified Windows means the following OSs Windows 3 1 Windows 95 98 2000 Windows NT TM Ver 4 0 ...

Page 431: ...ource file Device file Language Processing Software Flash memory write adapter In Circuit Emulator Power supply unit Emulation probe Conversion socket or conversion adapter Target system Host Machine PC Interface adapter PC card interface etc Emulation board On chip flash memory version Flash Memory Write Environment Flash programmer Performance board Remark The item in the broken line box differs...

Page 432: ...n to the 78K 0 Series are combined in this package SP78K0 78K 0 Series software package Part number µS SP78K0 Remark in the part number differs depending on the host machine and OS used µS SP78K0 Host Machine OS Supply Medium AB17 Windows Japanese version BB17 PC 9800 series IBM PC AT compatibles Windows English version CD ROM ...

Page 433: ...hen using CC78K0 in PC environment This C compiler package is a DOS based application It can also be used in Windows however by using the Project Manager included in assembler package on Windows CC78K0 C compiler package Part number µS CC78K0 This file contains information peculiar to the device This device file should be used in combination with a tool RA78K0 CC78K0 SM78K0 ID78K0 NS and ID78K0 al...

Page 434: ...3 Windows Japanese version BB13 PC 9800 series IBM PC AT compatibles Windows English version 3 5 inch 2HD FD 3P16 HP9000 series 700 HP UX Rel 10 10 DAT 3K13 3 5 inch 2HD FD 3K15 SPARCstation SunOS Rel 4 1 4 Solaris Rel 2 5 1 1 4 inch CGMT A 3 Flash Memory Writing Tools Flashpro III part number FL PR3 PG FP3 Flashpro IV part number FL PR4 PG FP4 Flash programmer Flash programmer dedicated to microc...

Page 435: ... card interface This is PC card and interface cable required when using a notebook type computer as the IE 78K0 NS A host machine PCMCIA socket compatible IE 70000 PC IF C Interface adapter This adapter is required when using an IBM PC AT compatible computer as the IE 78K0 NS A host machine ISA bus compatible IE 70000 PCI IF A Interface adapter This adapter is required when using a computer with a...

Page 436: ...ivalent visually and operationally to Windows or OSF MotifTM It also has an enhanced debugging function for C language programs and thus trace results can be displayed on screen at C language level by using the windows integration function which links a trace result with its source program disassembled display and memory display In addition by incorporating function expansion modules such as a tas...

Page 437: ...ber µS RX78013 Caution To purchase the RX78K0 first fill in the purchase application form and sign the user agreement Remark and in the part number differ depending on the host machine and OS used µS RX78013 Product Outline Maximum Number for Use in Mass Production 001 Evaluation object Do not use for mass produced product 100K 0 1 million units 001M 1 million units 010M Mass production object 10 ...

Page 438: ...BRGC6 280 305 C Capture compare control register 00 CRC00 135 Clock monitor mode register CLM 361 Clock output selection register CKS 220 Clock selection register 6 CKSR6 279 304 E 8 bit timer compare register 50 CR50 164 8 bit timer compare register 51 CR51 164 8 bit timer counter 50 TM50 164 8 bit timer counter 51 TM51 164 8 bit timer H carrier control register 1 TMCYC1 185 8 bit timer H compare...

Page 439: ...ort 12 P12 95 Port 13 P13 96 Port 14 P14 97 Port 2 P2 90 Port 3 P3 91 Port 6 P6 93 Port 7 P7 94 Port mode register 0 PM0 98 138 Port mode register 1 PM1 98 170 Port mode register 12 PM12 98 Port mode register 14 PM14 98 222 Port mode register 3 PM3 98 170 Port mode register 6 PM6 98 Port mode register 7 PM7 98 Power fail comparison mode register PFM 231 Power fail comparison threshold register PFT...

Page 440: ...ation mode register 10 CSIM10 313 315 316 16 bit timer capture compare register 000 CR000 131 16 bit timer capture compare register 010 CR010 132 16 bit timer counter 00 TM00 131 16 bit timer mode control register 00 TMC00 133 16 bit timer output control register 00 TOC00 135 T Timer clock selection register 50 TCL50 165 Timer clock selection register 51 TCL51 165 Transmit buffer register 10 SOTB1...

Page 441: ...lock output selection register 220 CKSR6 Clock selection register 6 279 304 CLM Clock monitor mode register 361 CMP00 8 bit timer H compare register 00 181 CMP01 8 bit timer H compare register 01 181 CMP10 8 bit timer H compare register 10 181 CMP11 8 bit timer H compare register 11 181 CR000 16 bit timer capture compare register 000 131 CR010 16 bit timer capture compare register 010 132 CR50 8 b...

Page 442: ...son mode register 231 PFT Power fail comparison threshold register 231 PM0 Port mode register 0 98 138 PM1 Port mode register 1 98 170 PM12 Port mode register 12 98 PM14 Port mode register 14 98 222 PM3 Port mode register 3 98 170 PM6 Port mode register 6 98 PM7 Port mode register 7 98 PR0H Priority specification flag register 0H 331 PR0L Priority specification flag register 0L 331 PR1L Priority s...

Page 443: ...8 bit timer counter 51 164 TMC00 16 bit timer mode control register 00 133 TMC50 8 bit timer mode control register 50 167 TMC51 8 bit timer mode control register 51 167 TMCYC1 8 bit timer H carrier control register 1 185 TMHMD0 8 bit timer H mode register 0 182 TMHMD1 8 bit timer H mode register 1 182 TOC00 16 bit timer output control register 00 135 TXB6 Transmit buffer register 6 274 TXS0 Transm...

Page 444: ...Preliminary User s Manual U16315EJ1V0UD 444 MEMO ...

Page 445: ...Fax 86 21 6841 1137 Address North America NEC Electronics Inc Corporate Communications Dept Fax 1 800 729 9288 1 408 588 6130 Europe NEC Electronics Europe GmbH Market Communication Dept Fax 49 211 6503 274 South America NEC do Brasil S A Fax 55 11 6462 6829 Taiwan Asian Nations except Philippines NEC Electronics Singapore Pte Ltd Fax 886 2 2719 5951 Fax 65 250 3583 Japan NEC Semiconductor Technic...

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NEC 78K0/KD1 Series, User Manual

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Summary of Contents for 78K0/KD1 Series

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