Preliminary User’s Manual U16315EJ1V0UD
15
LIST OF FIGURES (1/7)
Figure No.
Title
Page
2-1
Pin I/O Circuit List ....................................................................................................................................... 44
3-1
Memory Map (
µ
PD780121) ......................................................................................................................... 47
3-2
Memory Map (
µ
PD780122) ......................................................................................................................... 48
3-3
Memory Map (
µ
PD780123) ......................................................................................................................... 49
3-4
Memory Map (
µ
PD780124) ......................................................................................................................... 50
3-5
Memory Map (
µ
PD78F0124)....................................................................................................................... 51
3-6
Data Memory Addressing (
µ
PD780121) ..................................................................................................... 54
3-7
Data Memory Addressing (
µ
PD780122) ..................................................................................................... 55
3-8
Data Memory Addressing (
µ
PD780123) ..................................................................................................... 56
3-9
Data Memory Addressing (
µ
PD780124) ..................................................................................................... 57
3-10
Data Memory Addressing (
µ
PD78F0124) ................................................................................................... 58
3-11
Format of Program Counter ........................................................................................................................ 59
3-12
Format of Program Status Word ................................................................................................................. 59
3-13
Format of Stack Pointer............................................................................................................................... 61
3-14
Data to Be Saved to Stack Memory ............................................................................................................ 61
3-15
Data to Be Restored from Stack Memory.................................................................................................... 61
3-16
Configuration of General-Purpose Registers............................................................................................... 62
4-1
Port Types................................................................................................................................................... 78
4-2
Block Diagram of P00 and P03 ................................................................................................................... 81
4-3
Block Diagram of P01.................................................................................................................................. 82
4-4
Block Diagram of P02.................................................................................................................................. 83
4-5
Block Diagram of P10.................................................................................................................................. 84
4-6
Block Diagram of P11 and P14 ................................................................................................................... 85
4-7
Block Diagram of P12.................................................................................................................................. 86
4-8
Block Diagram of P13.................................................................................................................................. 87
4-9
Block Diagram of P15.................................................................................................................................. 88
4-10
Block Diagram of P16 and P17 ................................................................................................................... 89
4-11
Block Diagram of P20 to P27 ...................................................................................................................... 90
4-12
Block Diagram of P30 to P32 ...................................................................................................................... 91
4-13
Block Diagram of P33.................................................................................................................................. 92
4-14
Block Diagram of P60 to P63 ...................................................................................................................... 93
4-15
Block Diagram of P70 to P77 ...................................................................................................................... 94
4-16
Block Diagram of P120................................................................................................................................ 95
4-17
Block Diagram of P130................................................................................................................................ 96
4-18
Block Diagram of P140................................................................................................................................ 97
4-19
Format of Port Mode Register ..................................................................................................................... 98
4-20
Format of Pull-up Resistor Option Register............................................................................................... 100
4-21
Format of Input Switch Control Register (ISC) .......................................................................................... 101
5-1
Block Diagram of Clock Generator ............................................................................................................ 104
5-2
Subsystem Clock Feedback Resistor........................................................................................................ 105
5-3
Format of Processor Clock Control Register (PCC) .................................................................................. 106