CHAPTER 14 SERIAL INTERFACE UART6
Preliminary User’s Manual U16315EJ1V0UD
308
(4) Permissible baud rate range during reception
The permissible error from the baud rate at the transmission destination during reception is shown below.
Caution
Make sure that the baud rate error during reception is within the permissible error range, by
using the calculation expression shown below.
Figure 14-23. Permissible Baud Rate Range During Reception
FL
1 data frame (11
×
FL)
FLmin
FLmax
Transfer rate
of UART6
Start bit
Bit 0
Bit 1
Bit 7
Parity bit
Minimum permissible
transfer rate
Maximum permissible
transfer rate
Stop bit
Start bit
Bit 0
Bit 1
Bit 7
Parity bit
Latch timing
Stop bit
Start bit
Bit 0
Bit 1
Bit 7
Parity bit
Stop bit
As shown in Figure 14-23, the latch timing of the receive data is determined by the counter set by baud rate
generator control register 6 (BRGC6) after the start bit has been detected. If the last data (stop bit) meets this
latch timing, the data can be correctly received.
Assuming that 11-bit data is received, the theoretical values can be calculated as follows.
FL = (Brate)
−
1
Brate: Baud rate of UART6
k:
Set value of BRGC6
FL:
1-bit data length
Margin of latch timing: 2 clocks
Minimum permissible transfer rate: FLmin = 11
×
FL
−
×
FL = FL
k
−
2
2k
21k + 2
2k