CHAPTER 14 SERIAL INTERFACE UART6
Preliminary User’s Manual U16315EJ1V0UD
304
(2) Generation of serial clock
A serial clock can be generated by using clock selection register 6 (CKSR6) and baud rate generator control
register 6 (BRGC6).
Select the clock to be input to the 8-bit counter by using bits 3 to 0 (TPS63 to TPS60) of CKSR6.
Bits 7 to 0 (MDL67 to MDL60) of BRGC6 can be used to select the division value of the 8-bit counter.
(a) Clock selection register 6 (CKSR6)
This register selects the base clock of serial interface UART6.
CKSR6 can be set by an 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Remark
CKSR6 can be refreshed (the same value is written) by software during a communication
operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5
(RXE6) of ASIM6 = 1).
Address: FF56H After reset: 00H R/W
Symbol
7
6
5
4
3
2
1
0
CKSR6
0
0
0
0
TPS63
TPS62
TPS61
TPS60
TPS63
TPS62
TPS61
TPS60
Base clock (f
XCLK
)
0
0
0
0
f
X
(10 MHz)
0
0
0
1
f
X
/2 (5 MHz)
0
0
1
0
f
X
/2
2
(2.5 MHz)
0
0
1
1
f
X
/2
3
(1.25 MHz)
0
1
0
0
f
X
/2
4
(625 kHz)
0
1
0
1
f
X
/2
5
(312.5 kHz)
0
1
1
0
f
X
/2
6
(156.25 kHz)
0
1
1
1
f
X
/2
7
(78.13 kHz)
1
0
0
0
f
X
/2
8
(39.06 kHz)
1
0
0
1
f
X
/2
9
(19.53 kHz)
1
0
1
0
f
X
/2
10
(9.77 kHz)
1
0
1
1
TM50 output
Other
Setting prohibited
Caution
Make sure POWER6 = 0 when rewriting TPS63 to TPS60.
Remarks 1.
Figures in parentheses are for operation with f
X
= 10 MHz
2.
f
X
: X1 input clock oscillation frequency