NCR RealPOS 70, User Manual

Page: 259 / 306

Chapter 12: Cash Drawer Interface 12-19
· 32-bit configuration address port, occupying I/O addresses 0x0CF8 through
0x0CFB.
· 32-bit configuration data port, occupying I/O addresses 0x0CFC through
0x0CFF.
Accessing a PCI function's configuration port is a two step process:
· Write the target bus number, physical device number, function number
and doubleword number to the configuration address port
· Perform and I/O read from or a write to the configuration data port.
The ICH4 Configuration Address Register(CONFIG_ADDRESS) should be defined as
follows:
· Configuration Space Mapping enabled
· Bus number 0x0
· Device number 0x31
· Function number 0x00
· GPIO BASE Port offset address 0x58
The configuration address register at 0x0CF8 value for DWORD access:
- for GPI/O GPIO_BASE register 80007858
- for GPI/O GPIO_CNTL register 8000785C
Within the ICH4, the General Purpose I/O ports are addressed using an offset
from
the base address assigned by the BIOS. The offset to GP I/O ports is as
follows:
· GPIO_USE_SEL2: DWORD offset GPIO_BASE co 0x30
· GPIO_IO_SEL2: DWORD offset GPIO_BASE co 0x34
· GPIO_LVL2: DWORD offset GPIO_BASE co 0x38
Two GPO ports one GPI port of South Bridge VT686B are used to control cash
drawer. They are defined as below:
· GPIO 33 CD_SOL_A output 0, low turn off solenoid A. Output 1, high
Activates Solenoid A.
· GPIO 34 CD_SOL_B output 0, low turn off solenoid B. Output 1, high
Activates Solenoid B.
· GPIO 32 CD_SW_AB input 1, high Drawer(s) open. Input 0, low
Drawer(s) closed.
· GPIO 35 CD_ARM output 0, low Drawer(s) solenoid signals enabled. Output
1, high disabled.
There is only one cash drawer status signal CD_SW_AB. It is the status of
either cash drawer or
both cash drawers.
*/
//In the PCI device configuration space, query the
// GPIO Base Address Register (GPIOBASE) to determine the address for reading
// the GPI port assigned to the select register (m_nIOPort_select) and the
address
// we can read/write the solenoid bits and read the status bit (m_nIOPort).