App
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Appendix 2 Special Register List
APPENDICES
*14: The Universal model QCPU except the Q02UCPU.
*15: For the Q03UDCPU, Q04UDHCPU, Q06UDHCPU whose first 5 digits of the serial number are "10011" or earlier, the range is 1 to 9 (Default: 2) and when a
value other than 1 to 9 is set, operation is performed as if 9 is set.
Number
Name
Meaning
Explanation
Set by
(When Set)
Corres-
ponding
ACPU
D9
Corresponding
CPU
SD796
Maximum
number of
blocks used for
dedicated
instruction of
Multiple CPU
high speed
transmission
setting (for CPU
No.1)
Maximum number
of blocks used for
dedicated
instruction range 1
to 7 (Default: 2)
* When value
other than 1 to 7
is set, operation
is performed as if
7 is set.
• Specifies the maximum number of blocks used for the dedicated
instruction of Multiple CPU high speed transmission (target CPU = CPU
No.1). When the dedicated instruction of Multiple CPU high speed
transmission is executed to the CPU No.1, and the number of empty
blocks of the dedicated instruction transmission area is less than the
setting value of this register, SM796 is turned ON, which is used as the
interlock signal for consecutive execution of the dedicated instrucion of
Multiple CPU high speed transmission.
U (At 1 scan
after RUN)
New
QnU
*14*15
SD797
Maximum
number of
blocks used for
dedicated
instruction of
Multiple CPU
high speed
transmission
setting (for CPU
No.2)
• Specifies the maximum number of blocks used for the dedicated
instruction of Multiple CPU high speed transmission (target CPU = CPU
No.2). When the dedicated instruction of Multiple CPU high speed
transmission is executed to the CPU No.2, and the number of empty
blocks of the dedicated instruction transmission area is less than the
setting value of this register, SM797 is turned ON, which is used as the
interlock signal for consecutive execution of the dedicated instrucion of
Multiple CPU high speed transmission.
U (At 1 scan
after RUN)
New
QnU
*14*15
SD798
Maximum
number of
blocks used for
dedicated
instruction of
Multiple CPU
high speed
transmission
setting (for CPU
No.3)
• Specifies the maximum number of blocks used for the dedicated
instruction of Multiple CPU high speed transmission (target CPU = CPU
No.3). When the dedicated instruction of Multiple CPU high speed
transmission is executed to the CPU No.3, and the number of empty
blocks of the dedicated instruction transmission area is less than the
setting value of this register, SM798 is turned ON, which is used as the
interlock signal for consecutive execution of the dedicated instrucion of
Multiple CPU high speed transmission.
U (At 1 scan
after RUN)
New
QnU
*14*15
SD799
Maximum
number of
blocks used for
dedicated
instruction of
Multiple CPU
high speed
transmission
setting (for CPU
No.4)
• Specifies the maximum number of blocks used for the dedicated
instruction of Multiple CPU high speed transmission (target CPU = CPU
No.4). When the dedicated instruction of Multiple CPU high speed
transmission is executed to the CPU No.4, and the number of empty
blocks of the dedicated instruction transmission area is less than the
setting value of this register, SM799 is turned ON, which is used as the
interlock signal for consecutive execution of the dedicated instrucion of
Multiple CPU high speed transmission.
U (At 1 scan
after RUN)
New
QnU
*14*15