Mitsubishi Electric Apricot LS Pro, Hardware Technical Reference

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System Board
Contents
Chapter 1
Chapter 2
Chapter 3
Chapter 5
Chapter 6
Chapter 3
3/6 LS PRO HARDWARE TECHNICAL REFERENCE
3.3 SCAMP
The LS Pro system board is based on a VLSI VL82C311 single chip AT
compatible chipset. The VL82C311 integrates the following standard AT
system board peripheral logic in a single QFP package:
• two 8237A DMA controllers
• two 82C59A interrupt controllers
• 82C54 system timer
• 74LS612 memory mapper
• 82284 clock generator and ready interface
• 82288 bus controller
In addition to the logic listed above the VL82C311 also includes:
• memory controller
• bus steering logic
• parity generation and checking logic
• Port B and NMI logic
Memory The memory controller integrated in the VL82C311 can access the full 16Mbyte
controller address range of the processor. Memory is addressed in up to four banks of 2 or 8
Mbytes. Page mode operation and interleaving maximise system performance.
Full LIM 4.0 support is included with 36 mapping registers. ROM shadowing is
supported from 640k to 1M.
System control Port B is located at I/O location 0061h. The port may be used for: gate timer 2 (speaker);
port B speaker data; RAM parity check enable; enable I/O channel check; refresh detect; timer
2 out; I/O channel check; RAM parity check. The detailed function of each bit is
described in section 5.
Interrupt structure
The system board supports 16 levels of edge sensitive, maskable hardware
interrupts, including Non-Maskable Interrupts (NMI).
The interrupt control circuitry is functionally equivalent to two 8259A
programmable interrupt controllers. Each controller has eight interrupt inputs;
one interrupt input is used to cascade the controllers together. This leaves
fifteen inputs available for the processing system to use.
The output from the controllers goes to the INTR input on the processor. All
of the interrupts may be masked using the processor CLI instruction.