Mitsubishi Electric Apricot LS Pro, Hardware Technical Reference

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Error beep codes
Chapter 4
Appendix A
Appendix C
Pr
eface
C/2 LS PRO HARDWARE TECHNICAL REFERENCE
Chapter 6Chapter 4
Appendix C
If more than one beep code is heard, make a note of the sequence of beeps and refer
to the following table to determine the cause of the error. As an example, the beep
sequence ‘1-3-3’ represents: a single beep followed by a group of three beeps, followed
by another group of three beeps.
Beep sequence Error
1-1-3 CMOS RAM read/write test failure
1-1-4 BIOS ROM checksum failure
1-2-1 Programmable interval timer failure
1-2-2 DMA initialisation failure
1-2-3 DMA page register read/write test failure
1-3-1 RAM refresh verification failure
1-3-3 1st 64k RAM data line failure (multibit)
1-3-4 1st 64k RAM data odd/even logic failure
1-4-1 1st 64k RAM address line failure
1-4-2 1st 64k RAM parity failure
1-4-3 Fail-safe timer test in progress
1-4-4 Software NMI port test in progress
2-1-1 1st 64k RAM data line failure (bit 0)
2-1-2 1st 64k RAM data line failure (bit 1)
2-1-3 1st 64k RAM data line failure (bit 2)
2-1-4 1st 64k RAM data line failure (bit 3)
2-2-1 1st 64k RAM data line failure (bit 4)
2-2-2 1st 64k RAM data line failure (bit 5)
2-2-3 1st 64k RAM data line failure (bit 6)
2-2-4 1st 64k RAM data line failure (bit 7)
2-3-1 1st 64k RAM data line failure (bit 8)
2-3-2 1st 64k RAM data line failure (bit 9)
2-3-3 1st 64k RAM data line failure (bit A)
2-3-4 1st 64k RAM data line failure (bit B)
2-4-1 1st 64k RAM data line failure (bit C)
2-4-2 1st 64k RAM data line failure (bit D)
2-4-3 1st 64k RAM data line failure (bit E)
2-4-4 1st 64k RAM data line failure (bit F)
3-1-1 Slave DMA register failure
3-1-2 Master DMA register failure
3-1-3 Master interrupt mask register failure
3-1-4 Slave interrupt mask register failure
3-2-4 Keyboard controller failure
3-3-4 Screen memory failure
3-4-1 Screen initialisation failure
3-4-2 Screen retrace test failure