SmartTime Static Timing Analyzer User Guide
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Figure 31 · Add Maximum Delay Constraint
5. Click
OK
to exit the Add Constraint Dialog box.
6. Click
Save
in the Constraints Editor.
7. Exit the Constraints Editor.
8. Exit SmartTime.
9. Rerun Place and Route if the newly-added constraint that is added to a file (the Target file) is used for
Place and Route and Verify Timing.
10. Open SmartTime Maximum/Minimum Delay Analysis View.
From SmartTime to Chip Planner
Cross-probing allows you to select a design object in one application and display the selected object in
another application. Because Libero SoC allows you to cross-probe design objects from SmartTime to Chip
Planner, you can better understand how the two applications interact with each other. With cross-probing, a
timing path not meeting timing requirements can be fixed with relative ease when you see the less-than-
optimal placement of the design object (in terms of timing requirements) in Chip Planner. Cross-probing from
SmartTime to Chip Planner is available for the following design objects:
•
Macros
•
Ports
•
Nets/Paths
Note
: Cross-probing of design objects is available from SmartTime to Chip Planner but not vice versa.
Before you can cross-probe from SmartTime to Chip Planner, you must:
1. Complete the Place and Route step on the design.
2. Open both SmartTime and Chip Planner.
Summary of Contents for SmartTime
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Page 31: ...SmartTime Static Timing Analyzer User Guide 31 Advanced Timing Analysis ...
Page 37: ...SmartTime Static Timing Analyzer User Guide 37 Generating Timing Reports ...
Page 57: ...SmartTime Static Timing Analyzer User Guide 57 Timing Concepts ...
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Page 92: ...SmartTime Static Timing Analyzer User Guide 92 Dialog Boxes ...
Page 118: ...SmartTime Static Timing Analyzer User Guide 118 Tcl Commands ...