Microsemi SmartTime, User Manual

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SmartTime Static Timing Analyzer User Guide
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Static Timing Analysis Versus Dynamic Simulation
Static timing analysis (STA) offers an efficient technique for identifying timing violations in your design and
ensuring that it meets all your timing requirements. You can communicate timing requirements and timing
exceptions to the system by setting timing constraints. A static timing analysis tool will then check and report
setup and hold violations as well as violations on specific path requirements.
STA is particularly well suited for traditional synchronous designs. The main advantage of STA is that unlike
dynamic simulation, it does not require input vectors. It covers all possible paths in the design and does all
the above with relatively low run-time requirements. The major disadvantage of STA is that the STA tools do
not automatically detect false paths in their algorithms.
Delay Models
The first step in timing analysis is the computation of single component delays. These components could be
either a combinational gate or block or a single interconnect connecting two components.
Gates that are part of the library are pre-characterized with delays under different parameters, such as input-
slew rates or capacitive loads. Traditional models provide delays between each pair of I/Os of the gate and
between rising and falling edges.
The accuracy with which interconnect delays are computed depends on the design phase. These can be
estimated using a simple Wire Load Model (WLM) at the pre-layout phase, or a more complex Resistor and
Capacitor (RC) tree solver at the post-layout phase.
Timing Path Types
Path delays are computed by adding delay values across a chain of gates and interconnects. SmartTime
uses this information to check for timing violations. Traditionally, timing paths are presented by static timing
analysis tools in four categories or "sets":
•
Paths between sequential components internal to the design. SmartTime displays this category under
the Register to Register set of each displayed clock domain.
•
Paths that start at input ports and end at sequential components internal to the design. SmartTime
displays this category under the External Setup and External Hold sets of each displayed clock
domain.
•
Paths that start at sequential components internal to the design and end at output ports. SmartTime
displays this category under the Clock to Out set of each displayed clock domain.
•
Paths that start at input ports and end at output ports. SmartTime displays this category under the
Input to Output set.
Maximum Clock Frequency
Generally, you set clock constraints on clocks for which you have a specified requirement. The absence of
violations indicates that this clock will be able to run at least at the specified frequency. However, in the
absence of such requirements, you may still be interested in computing the maximum frequency of a specific
clock domain.
To obtain the maximum clock frequency, a static timing analysis tool computes the minimum period for each
path between two sequential elements. To compute the maximum period, the tool evaluates the maximum
data path delay and the minimum skew between the two elements, as well as the setup on the receiving
sequential element. It also considers the polarity of each sequential element. The maximum frequency is the
inverse of the largest value among the maximum period of all the paths in the clock domain. The path
responsible for limiting the frequency of a given clock is called the critical path.
Setup Check
The setup and hold check ensures that the design functions as specified at the required clock frequency.