SmartTime Static Timing Analyzer User Guide
79
Minimum Delay Analysis with Timing Analyzer - 32-Bit Shift
Register Example
The SmartTime Minimum Delay Analysis window identifies any hold violations that exist in the design.
To perform Minimum Delay Analysis:
1. From the SmartTime Analysis window, choose
Tools > Minimum Delay Analysis
. The Minimum
Delay Analysis View appears, as shown in the figure below.
Figure 55 · SmartTime Minimum Delay Analysis View- Summary
2. Expand
my_clk
to display Register to Register, External Hold, Clock to Output, Register to
Asynchronous, External Removal and Asynchronous to Register path sets.
3. Click
Register to Register
to display the reg to reg paths. The window displays a list of register to
register paths and detailed timing analysis for the selected path. Note that all slack value are positive,
indicating that there are no hold time violations.
4. Click to select the first path and observe the hold analysis calculation details, as shown in the figure
below.
Summary of Contents for SmartTime
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Page 15: ...SmartTime Static Timing Analyzer User Guide 15 SmartTime Timing Analyzer ...
Page 31: ...SmartTime Static Timing Analyzer User Guide 31 Advanced Timing Analysis ...
Page 37: ...SmartTime Static Timing Analyzer User Guide 37 Generating Timing Reports ...
Page 57: ...SmartTime Static Timing Analyzer User Guide 57 Timing Concepts ...
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Page 92: ...SmartTime Static Timing Analyzer User Guide 92 Dialog Boxes ...
Page 118: ...SmartTime Static Timing Analyzer User Guide 118 Tcl Commands ...