SmartTime Static Timing Analyzer User Guide
100
Set False Path Constraint Dialog Box
Use this dialog box to define specific timing paths as being false.
This constraint removes timing requirements on these false paths so that they are not considered during the
timing analysis. The path starting points are the input ports or register clock pins and path ending points are
the register data pins or output ports. This constraint disables setup and hold checking for the specified
paths.
Note:
The false path information always takes precedence over multiple cycle path information and
overrides maximum delay constraints.
To open the Set False Path Constraint dialog box (shown below) from the SmartTime Constraints Editor,
choose
Constraints > False Path
.
Figure 80 · Set False Path Constraint Dialog Box
From
Specifies the starting points for false path. A valid timing starting point is a clock, a primary input, an inout
port, or a clock pin of a sequential cell.
Through
Specifies a list of pins, ports, cells, or nets through which the disabled paths must pass.
Summary of Contents for SmartTime
Page 2: ......
Page 6: ......
Page 15: ...SmartTime Static Timing Analyzer User Guide 15 SmartTime Timing Analyzer ...
Page 31: ...SmartTime Static Timing Analyzer User Guide 31 Advanced Timing Analysis ...
Page 37: ...SmartTime Static Timing Analyzer User Guide 37 Generating Timing Reports ...
Page 57: ...SmartTime Static Timing Analyzer User Guide 57 Timing Concepts ...
Page 66: ...SmartTime Static Timing Analyzer User Guide 66 ...
Page 92: ...SmartTime Static Timing Analyzer User Guide 92 Dialog Boxes ...
Page 118: ...SmartTime Static Timing Analyzer User Guide 118 Tcl Commands ...