LAPIS Semiconductor ML610471, User Manual, Page: 92 / 281

ML610471/472/473/Q471/Q472/Q473 User's Manual
Chapter 6 Clock Generation Circuit
6-10
6.4 Specifying Port Registers
To enable the clock output function, each related port register bit needs to be set. See Chapter 15, "Port 2" for
detail about the port registers.
6.4.1 Functioning P21 (OUTCLK) as the high-speed clock output
Set P21MD bit (bit1 of P2MOD register) to “1” for specifying the high-speed clock output as the secondary function of
P21.
Register
name
P2MOD register (Address: 0F214H)
Bit 7 6 5 4 3 2
1
0
Bit name
- - - - - -
P21MD
P20MD
Setting
value
- - - - - -
1
*
Set the P21C1 bit (P2CON1 register's bit 1) to "1" and the P21C0 bit (P2CON0 register's bit 1) to "1" for specifying the
state mode of the P21 pin to CMOS output.
Register
name
P2CON1 register (Address: 0F213H)
Bit 7 6 5 4 3 2
1
0
Bit name
- - - - - -
P21C1
P20C1
Setting
value
- - - - - -
1
*
Register
name
P2CON0 register (Address: 0F212H)
Bit 7 6 5 4 3 2
1
0
Bit name
- - - - - -
P21C0
P20C0
Setting
value
- - - - - -
1
*
The P21D bit (P2D register bit 1) data can either be "0" or "1".
Register
name
P2D register (Address: 0F210H)
Bit 7 6 5 4 3 2
1
0
Bit name
- - - - - -
P21D
P20D
Setting
value
- - - - - -
**
*
- : Bit that does not exist
* : Bit not related to the high-speed clock function
** : Don’t care
Note:
P21 (Port 2) is an output-only port and does not have the register to select the data direction(input or output).
P21 is not available in 48-pin plastic TQFP.