LAPIS Semiconductor ML610471, User Manual, Page: 159 / 281

ML610471/472/473/Q471/Q472/Q473 User's Manual
Chapter 11 UART
11-18
11.3.5.1 Detection of Start Bit
The Start bit is sampled using the baud rate generator clock (LSCLK, LSCLK x 2, HSCLK) selected by the U0CK1 and
U0CK0 bits of the UARTn mode register 0 (UA0MOD0). Therefore, the start bit detection may be delayed for one cycle
of the baud rate generate clock at the maximum.
Figure 11-7 shows the start bit detection timing.
Figure 11-7 Start Bit Detection Timing (Positive Logic)
11.3.5.2 Sampling Timing
When the Start bit is detected, the received data that was input to the RXD0 is sampled almost at the center of the baud
rate, then loaded to the shift register.
The loading sampling timing of this shift register can be adjusted for one clock of the baud rate generator clock, using the
U0RSS bit of the UART0 mode register 0 (UA0MOD0).
Figure 11-8 shows the relationship between the U0RSS bit and the sampling timing.
(1) When the baud rate generator count value is "7" (odd)
(2) When the baud rate generator count value is "8" (even)
Figure 11-8 Relationship between UORSS Bit and Sampling Timing
Baud rate generator clock
RXD0
0 3 2 7 0 3 2 7
Sampling Timing
U0RSS=1 U0RSS=0
Count value = 8
Baud rate generator
Sampling by clock
RXD0
Maximum one-cycle delay
Start bit
Baud rate generator clock
RXD0
0 3 2 6 0 3 2 6
Sampling Timing
UnRSS=1 UnRSS=0
Count value = 7