LAPIS Semiconductor ML610471, User Manual, Page: 179 / 281

ML610471/472/473/Q471/Q472/Q473 User's Manual
Chapter 13 Port 2
13-6
13.3 Description of Operation
13.3.1 Output Port Function
For each pin of Port 2, any one of high-impedance output mode, P-channel open drain output mode, N-channel open
drain output mode, and CMOS output mode can be selected by setting the Port 2 control registers 0 and 1 (P2CON0 and
P2CON1). At a system reset, high-impedance output mode is selected as the initial state.
Depending of the value set in the Port 2 data register (P2D), a “L” level or “H” level signal is output to each pin of Port 2.
13.3.2 Secondary Function
Low-speed clock (LSCLK) output, High-speed clock (OUTCLK) output are assigned to Port 2 as a secondary function.
The secondary function can be used by setting the P20MD, P21MD bits of the Port 2 mode register (P2MOD) to “1”.