LAPIS Semiconductor ML610471, User Manual, Page: 76 / 281

ML610471/472/473/Q471/Q472/Q473 User's Manual
Chapter 5 Interrupt
5-14
5.3 Description of Operation
With the exception of the watchdog timer interrupt (WDTINT), interrupt enable/disable for 20 sources is controlled by
the master interrupt enable flag (MIE) and the individual interrupt enable registers (IE1 to 7). WDTINT is a
non-maskable interrupt.
When the interrupt conditions are satisfied, the CPU calls a branching destination address from the vector table
determined for each interrupt source and the interrupt shift cycle starts to branch to the interrupt processing routine.
Table 5-1 lists the interrupt sources.
Table 5-1 Interrupt Sources
Priority Interrupt source Symbol Vector table address
1 Watchdog timer interrupt WDTINT 0008H
2 P00 interrupt P00INT 0010H
3 P01 interrupt P01INT 0012H
4 P02 interrupt P02INT 0014H
5 P03 interrupt P03INT 0016H
6 UART 0 interrupt UA0INT 0040H
7
RC oscillation type A/D converter
interrupt
RADINT 004AH
8 Timer 2 interrupt TM2INT 0058H
9 Timer 3 interrupt TM3INT 005AH
10 TBC128Hz interrupt T128HINT 006AH
11 TBC32Hz interrupt T32HINT 006EH
12 TBC16Hz interrupt T16HINT 0070H
13 TBC2Hz interrupt T2HINT 0076H
Note:
- When multiple interrupts are generated concurrently, the interrupts are serviced according to this priority and
processing of low-priority interrupts is pending.
- Please define vector tables for all unused interrupts for fail safe.