LAPIS Semiconductor ML610471, User Manual, Page: 113 / 281

ML610471/472/473/Q471/Q472/Q473 User's Manual
Chapter 8 Capture
8-8
8.3 Description of Operation
The capture circuit starts the capture operation by setting the ECAP0 or ECAP1 bit of the capture control register
(CAPCON).
When the input trigger from the P00 or P01 pin selected by the external interrupt control register 0 or 1 (EXICON0 or
EXICON1) is generated and the P00 or P01 interrupt request flag (QP00 or QP01) is set to “1”, the T4KHZ to T32HZ
signals of the low-speed time base counter (LTBC) are captured in the capture data register 0 or 1 (CAPR0 or CAPR1)
on the next low-speed clock (LSCLK) falling edge and the at the same time, the capture flag (CAPF0 or CAPF1) of the
capture status register (CAPSTAT) is set to “1”.
When the capture flag (CAPF0, CAPF1) is “1”, the following capture operation stops.
The value, once captured by software into the capture data register 0 or 1 (CAPR0, CAPR1), is read to the CPU. Then,
in preparation for the next capture operation, the writing operation is performed to the applicable capture data register 0
or 1 (CAPR0, CAPR1)(write data is meaningless), the capture flag (CAPF0, CAPF1) is cleared to "0", then the next P00
or P01 interrupt is waited.
Figure 8-2 shows the timing of the capture operation.
Figure 8-2 Timing Diagram of Capture Operation
Note:
When CPU is operating on the high-speed clock (HSCLK), check that the capture flag (CAPF0, CAPF1) is set to "1"
after the P00 or P01 interrupt request is generated and then read capture data register 0 or 1 (CAPR0, CAPR1).
System clock
SYSCLK
CAPF0, CAPF1
QP00, QP01
Interrupt request flag
P00 and P01 pins
LTBC
(T4KHZ to T32HZ)
CAPR0, CAPR1
LSCLK
(32.768kHz)
N N+1
N+1
N+1
Write CAPR0, 1
(Writing
operation)
XX