LAPIS Semiconductor ML610471, User Manual, Page: 85 / 281

ML610471/472/473/Q471/Q472/Q473 User's Manual
Chapter 6 Clock Generation Circuit
6-3
6.2.2 Frequency Control Register 0 (FCON0)
Address: 0F002H
Access: R/W
Access size: 8/16 bit
Initial value: 33H
7 6 5 4 3 2 1 0
FCON0
— —
OUTC1 OUTC0
— —
SYSC1 SYSC0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 1 1 0 0 1 1
FCON0 is a special function register (SFR) to control the high-speed clock generation circuit and to select system clock.
[Description of Bits]
•
SYSC1, SYSC0 (bits 1, 0)
The SYSC1 and SYSC0 bits are used to select the frequency of the high-speed clock (HSCLK) used for system
clock and peripheral circuits (including high-speed time base counter). OSCLK, 1/2OSCLK, 1/4OSCLK, or
1/8OSCLK can be selected. The maximum operating frequency guaranteed for the system clock (SYSCLK) of
this LSI is 500 kHz.
At system reset, 1/8OSCLK is selected.
SYSC1 SYSC0
Description
0 0 OSCLK
0 1 1/2OSCLK
1 0 1/4OSCLK
1 1 1/8OSCLK (initial value)
•
OUTC1, OUTC0 (bits 5, 4)
The OUTC1 and OUTC0 bits are used to select the frequency of the high-speed output clock (OUTCLK) which
is output when the secondary function of the port is used. OSCLK, 1/2OSCLK, 1/4OSCLK, or 1/8OSCLK can
be selected.
At system reset, 1/8OSCLK is selected.
OUTC1 OUTC0
Description
0 0 OSCLK
0 1 1/2OSCLK
1 0 1/4OSCLK
1 1 1/8OSCLK (initial value)
Note:
OUTCLK is not available in 48-pin plastic TQFP.