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ML610471/472/473/Q471/Q472/Q473 User's Manual
Chapter 10 Watchdog Timer
10-5
10.3 Description of Operation
The WDT counter starts counting after the system reset has been released and the low-speed clock oscillation start..
The WDT counter can be cleared by writing "5AH" with the internal pointer (WDP) is "0", then writing "0A5H" with
the WDP "1".
The WDP is reset to “0” at the system reset or WDT counter overflow and is inverted every writing to WDTCON.
When the WDT counter cannot be cleared within the WDT counter overflow period (T
WOV
), a watchdog timer interrupt
(WDTINT) occurs. If the WDT counter is not cleared even by the software processing performed following the
watchdog timer interrupt and overflow occurs again, WDT reset occurs and the mode shifts to a system reset mode.
For the overflow period (T
WOV
) of the WDT counter, one of 125ms, 500ms, 2s, and 8s can be selected by the watchdog
mode register (WDTMOD).
Clear the WDT counter within the clear period of the WDT counter (T
WCL
) shown in Table 10-1.
Table 10-1 Clear Period of WDT Counter
WDT1 WDT0 T
WOV
T
WCL
0 0 125ms Approx. 121ms
0 1 500ms Approx. 496 ms
1 0 2000ms Approx. 1996 ms
1 1
8000ms Approx. 7996 ms