LAPIS Semiconductor ML610471, User Manual, Page: 102 / 281

ML610471/472/473/Q471/Q472/Q473 User's Manual
Chapter 7 Time Base Counter
7-8
7.3.2 High-Speed Time Base Counter
The high-speed time base counter is configured as a 4-bit 1/n counter (n = 1 to 16).
In the 4-bit 1/n counter, the divided clock (1/16 x HSCLK to 1/1 x HSCLK) selected by the high-speed time base
counter divide register (HTBDR) is generated as HTBCLK. HTBCLK is used as a timer and also as an operation clock
of PWM.
Figure 7-5 shows the output waveform of HTBCLK.
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Figure 7-5 Output Waveform of HTBCLK
High-Speed Time Base
Counter
Divide register
High-speed
HSCLK
1/n counter output
HTBCLK
1/1 1/2 1/3
0FH
0EH
0DH
HTBDR