LAPIS Semiconductor ML610471, User Manual, Page: 146 / 281

ML610471/472/473/Q471/Q472/Q473 User's Manual
Chapter 11 UART
11-5
11.2.4 UART0 Mode Register 0 (UA0MOD0)
Address: 0F292H
Access: R/W
Access size: 8/16 bit
Initial value: 00H
7 6 5 4 3 2 1 0
UA0MOD0
− −
U0RSS U0RSEL
−
U0CK1 U0CK0 U0IO
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
UA0MOD0 is a special function register (SFR) to set the transfer mode of the UART.
[Description of Bits]
•
U0IO (bit 0)
The U0IO bit is used to select transmit or receive mode.
U0IO Description
0 Transmit mode (initial value)
1 Receive mode
•
U0CK1, U0CK0 (bits 2, 1)
The U0CK1 and U0CK0 bits are used to select the clock to be input to the baud rate generator of the UART0.
U0CK1 U0CK0 Description
0 0 LSCLK (initial value)
0 1 LSCLK
×
2
1
＊
HSCLK
•
U0RSEL (bit 4)
The U0RSEL bit is used to select the received data input pin for the UART0.
In 48-pin plastic TQFP, P42 pin is not available. Please set the R0RSEL bit to “0”.
U0RSEL Description
0 Selects the P02 pin. (Initial value)
1 Selects the P42 pin.
•
U0RSS (bit 5)
U0RSS is the bit that selects the UART0 received data input sampling timing.
U0RSS Description
0 Value set in the UA0BRTH and UA0BRTL registers/2 (initial value)
1 Value set in the UA0BRTH and UA0BRTL registers/2-1
Note:
•Always set the UA0MOD0 register while communication is stopped, and do not rewrite it during communication.
•When specifying LSCLK X 2 for the clock, enable the operation of the low-speed double clock by setting bit 2
(ENMLT) of the frequency control register 1 (FCON1) to “1”.
•When selecting the P42 pin as the received data input pin, it is necessary to configure settings for the Port 4
secondary functions. For the secondary functions of Port 4, see Chapter 15, “Port 4”.