26
7.2.5 Pr.40 = 5, Speed input come from AI2 with Bi-direction control
In this mode, the voltage signal fed into
AI2 terminal will be used to determine the
output frequency and direction of the
inverter.
The input signal level determines the
direction of the output phase sequence.
If the input signal is positive maximum
level, the set frequency is equal to Pr.15
(UPPER LIMIT) in forward direction; and
if the input signal is zero, the set frequency
is equal to Pr.15 in reverse direction.
If the input is around half level, the
inverter will stop.
Note: Set jumper JP2 to match with the
input signal type and range. If necessary,
use Pr.91 and Pr.92 to modify the input
range.
7.2.6 Pr.40 = 6, Speed input come from Internal Up/Down Counter
7.2.7 Pr.40 = 7, Speed input come from Internal Up/Down Counter with Preload from Pr.00
Note: When start running; the minimum running frequency shall be Pr.16.
In tern al
U p /D o w n
C ou nte r
P re load
P r.0 0
C ou nte r ou tpu t
* 2
* 3
* 1
* 1. If P r.40 = 6, 7, 11, or 1 9, th e c o u n te r ou tpu t is u sed to determ in e th e o u tpu t fre q u en cy.
* 2. If P r.40 = 7 or 1 9, D a ta in P r.0 0 w ill p re lo ad in to the co u nter w hen P o w e r O n or a fte r R ese t.
* 3. If P r.40 = 19 , a fte r U p /D ow n ex e cu tio n , th e c o n ten t o f co un ter w ill w rite into P r.00 au to m atic ally.
* 4. T h ese sign a ls c o m e from D ig ita l In p ut (D Ix ) term in al. R e fe r to S e c.8 for d eta il desc rip tion.
U P
D O W N
H O LD
C LE A R
* 4
LO A D
F u nction al B lock D iagram o f th e In ternal U P /D O W N C o u nter
H z desire
P r.4 0 =6 ,7 ,11 or 1 9
Pr.15
Hz(using Up/Down Module)
LOAD
HOLD
CLEAR
UP
DOWN
UP/DOWN COUNTER OPERATION EXAMPLE
Pr.16
RUN
Hz (forward)
JP2 set to +5V
JP2 set to 20mA
Hz (forward)
+5V
0V
Pr.15
Pr.15
Pr.16
Pr.16
Hz (reverse)
2.5V
20mA
0V
Pr.15
Pr.15
Pr.16
Pr.16
Hz (reverse)
10mA