42
9.20 TMOB Timer Output B-type function (Refer to Section 8.11)
Refer to the Functional block diagram of Timer/Counter module in Sec.8.7 and the related descriptions in Sec.8.11.
9.21 STEP1 output indicating Auto running at step1 (Refer to Section 12.2)
9.22 STEP2 output indicating Auto running at step2 (Refer to Section 12.2)
9.23 STEP3 output indicating Auto running at step3 (Refer to Section 12.2)
9.24 STEP4 output indicating Auto running at step4 (Refer to Section 12.2)
9.25 STEP5 output indicating Auto running at step5 (Refer to Section 12.2)
9.26 STEP6 output indicating Auto running at step6 (Refer to Section 12.2)
9.27 STEP7 output indicating Auto running at step7 (Refer to Section 12.2)
9.28 STEP8 output indicating Auto running at step8 (Refer to Section 12.2)
9.29 STEP9 output indicating Auto running at step9 (Refer to Section 12.2)
9.30 STEP10 output indicating Auto running at step10 (Refer to Section 12.2)
9.31 Reserve
9.32 Q1 output of Flip/Flop-1 (Refer to Section 8.22)
DOx(32) is Q output of Flip/Flop-1.
9.33 /Q1 output of Flip/Flop-1 (Refer to Section 8.22)
DOx(33) is /Q output of Flip/Flop-1.
9.34 Q2 output of Flip/Flop-2 (Refer to Section 8.22)
DOx(34) is Q output of Flip/Flop-2.
9.35 /Q2 output of Flip/Flop-2 (Refer to Section 8.22)
DOx(32) is /Q output of Flip/Flop-2.
9.36~37 Reserve
9.38 Always ON
The output status of DOx(38) is always under
ON state
when selecting this mode.
This function is complement function of
NULL
function. Refer to Sec.9.0.
This function is useful when the inverter is controlled by a master computer, or under TEST mode.
The master computer can control these digital outputs for other peripheral, independent to the inverter operation.
9.39 reserve
9.40 /TMOA Complement function of TMOA
DOx(40) = /DOx(14)
9.41 /TMOB Complement function of TMOB
DOx(41) = /DOx(20)
9.42 TMOC Timer Output C-type function (Refer to Section 8.36)
9.43 /TMOC Complement function of TMOC
DOx(43) = /DOx(42)
9.44 X32CLK output clock rate = 32 * Pr.57 (HZ)
9.45 X16CLK output clock rate = 16 * Pr.57 (HZ)
9.46 X8CLK output clock rate = 8 * Pr.57 (HZ)
9.47 X4CLK output clock rate = 4 * Pr.57 (HZ)
9.48 X2CLK output clock rate = 2 * Pr.57 (HZ)
9.49 X1CLK output clock rate = 1 * Pr.57 (HZ)
DOx(44)~DOx(49) are used for generating an output clock.
The maximum output clock rate should limit within 3KHz.
This clock output is only available for DO1.
After select one of these functions, user must execute RESET in order to change DO1 into XnCLK function. On the
contrary, if change from XnCLK into other DOx function, also execute RESET after selection is changed.
9.50 IDC-LEVEL0
DOx(50) output will ON, if Idc>Pr.48.
Idc is current value in DC bus.
Note: this function is for PDA/PDH series only.
9.51 IDC-LEVEL1
DOx(51) is similar to DOx(50), but AI1 is used as the comparison level.
Actual comparison method is : Idc(%) > 150% * AI1
Note: this function is for PDA/PDH series only.
9.52 IDC-LEVEL2
DOx(52) is similar to DOx(50), but AI2 is used as the comparison level.
Actual comparison method is: Idc(%) > 150% * AI2
Note: this function is for PDA/PDH series only.
9.53 IDC-LEVEL3
DOx(53) is similar to DOx(50), but AI3 is used as the comparison level.
Actual comparison method is: Idc(%) > 150% * AI3
Note: this function is for PDA/PDH series only.