Intel Xeon 5600 Series, Specification Update

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Intel® Xeon® Processor 5600 Series 14
Specification Update, March 2010
Errata Summary
Table 3. Errata Summary Table (Sheet 1 of 4)
Errata
Number
Steppings
Status ERRATA
B-1
BD1 X No Fix
The Processor may Report a #TS Instead of a #GP Fault
BD2 X No Fix
REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page
Boundaries with Inconsistent Memory Types may use an Incorrect Data
Size or Lead to Memory-Ordering Violations
BD3 X No Fix
Code Segment Limit/Canonical Faults on RSM May be Serviced before Higher
Priority Interrupts/Exceptions and May Push the Wrong Address Onto the Stack
BD4 X No Fix Performance Monitor SSE Retired Instructions May Return Incorrect Values
BD5 X No Fix Premature Execution of a Load Operation Prior to Exception Handler Invocation
BD6 X No Fix MOV To/From Debug Registers Causes Debug Exception
BD7 X No Fix
Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR Image Leads to
Partial Memory Update
BD8 X No Fix Values for LBR/BTS/BTM will be Incorrect after an Exit from SMM
BD9 X No Fix Single Step Interrupts with Floating Point Exception Pending May Be Mishandled
BD10 X No Fix Fault on ENTER Instruction May Result in Unexpected Values on Stack Frame
BD11 X No Fix
IRET under Certain Conditions May Cause an Unexpected Alignment Check
Exception
BD12 X No Fix
General Protection Fault (#GP) for Instructions Greater than 15 Bytes May be
Preempted
BD13 X No Fix
General Protection (#GP) Fault May Not Be Signaled on Data Segment Limit
Violation above 4-G Limit
BD14 X No Fix
LBR, BTS, BTM May Report a Wrong Address when an Exception/Interrupt Occurs
in 64-bit Mode
BD15 X No Fix
MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance of a DTLB
Error
BD16 X No Fix Debug Exception Flags DR6.B0-B3 Flags May be Incorrect for Disabled Breakpoints
BD17 X No Fix MONITOR or CLFLUSH on the Local XAPIC's Address Space Results in Hang
BD18 X No Fix
Corruption of CS Segment Register During RSM While Transitioning From Real
Mode to Protected Mode
BD19 X No Fix A VM Exit on MWAIT May Incorrectly Report the Monitoring Hardware as Armed
BD20 X No Fix Performance Monitor Event SEGMENT_REG_LOADS Counts Inaccurately
BD21 X No Fix
#GP on Segment Selector Descriptor that Straddles Canonical Boundary May Not
Provide Correct Exception Error Code
BD22 X No Fix
Improper Parity Error Signaled in the IQ Following Reset When a Code Breakpoint is
Set on a #GP Instruction
BD23 X No Fix
An Enabled Debug Breakpoint or Single Step Trap May Be Taken after MOV SS/
POP SS Instruction if it is Followed by an Instruction That Signals a Floating Point
Exception
BD24 X No Fix IA32_MPERF Counter Stops Counting During On-Demand TM1