Intel® Xeon® Processor 5600 Series
31
Specification Update, March 2010
BD46.
ECC Errors Can Not be Injected on Back-to-Back Writes
Problem:
ECC errors should be injected on every write that matches the address set in the
MC_CHANNEL_{0,1,2}_ADDR_MATCH CSRs. Due to this erratum if there are two back-
to-back writes that match MC_CHANNEL_{0,1,2}_ADDR_MATCH, the 2nd write will not
have the error injected.
Implication:
The 2nd back-to-back write that matches MC_CHANNEL_{0,1,2}_ADDR_MATCH will
not have the ECC error properly injected. Setting
MC_CHANNEL_{0,1,2}_ADDR_MATCH to a specific address will reduce the chance of
being impacted by this erratum.
Workaround:
Only injecting errors to specific address should reduce the chance on being impacted by
this erratum.
Status:
For the steppings affected, see the
BD47.
Performance Monitor Counter INST_RETIRED.STORES May Count
Higher than Expected
Problem:
Performance Monitoring counter INST_RETIRED.STORES (Event: C0H) is used to track
retired instructions which contain a store operation. Due to this erratum, the processor
may also count other types of instructions including WRMSR and MFENCE.
Implication:
Performance Monitoring counter INST_RETIRED.STORES may report counts higher than
expected.
Workaround:
None identified.
Status:
For the steppings affected, see the
BD48.
Sleeping Cores May Not be Woken Up on Logical Cluster Mode
Broadcast IPI Using Destination Field Instead of Shorthand
Problem:
If software sends a logical cluster broadcast IPI using a destination shorthand of 00B
(No Shorthand) and writes the cluster portion of the Destination Field of the Interrupt
Command Register to all ones while not using all 1s in the mask portion of the
Destination Field, target cores in a sleep state that are identified by the mask portion of
the Destination Field may not be woken up. This erratum does not occur if the
destination shorthand is set to 10B (All Including Self) or 11B (All Excluding Self).
Implication:
When this erratum occurs, cores which are in a sleep state may not wake up to handle
the broadcast IPI. Intel has not observed this erratum with any commercially available
software.
Workaround:
Use destination shorthand of 10B or 11B to send broadcast IPIs.
Status:
For the steppings affected, see the
BD49.
Faulting Executions of FXRSTOR May Update State Inconsistently
Problem:
The state updated by a faulting FXRSTOR instruction may vary from one execution to
another.
Implication:
Software that relies on x87 state or SSE state following a faulting execution of
FXRSTOR may behave inconsistently.
Workaround:
Software handling a fault on an execution of FXRSTOR can compensate for execution
variability by correcting the cause of the fault and executing FXRSTOR again.
Status:
