Intel Xeon 5600 Series, Specification Update

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Intel® Xeon® Processor 5600 Series 17
Specification Update, March 2010
BD79 X No Fix APIC Timer CCR May Report 0 in Periodic Mode
BD80 X No Fix
LBR, BTM or BTS Records May have Incorrect Branch From Information After an
Intel Enhanced SpeedStep Technology Transition, T-states, C1E, or Adaptive
Thermal Throttling
BD81 X No Fix PEBS Records Not Created For FP-Assists Events
BD82 X No Fix
MSR_TURBO_RATIO_LIMIT MSR May Return Intel® Turbo Boost Technology Core
Ratio Multipliers for Non-Existent Core Configurations
BD83 X No Fix L1 Cache Uncorrected Errors May be Recorded as Correctable in 16K Mode
BD84 X No Fix
Extra APIC Timer Interrupt May Occur During a Write to the Divide Configuration
Register
BD85 X No Fix
PECI Reads of Machine Check MSRs in the Processor Core May Not Function
Correctly
BD86 X No Fix
The Combination of a Page-Split Lock Access And Data Accesses That Are Split
Across Cacheline Boundaries May Lead to Processor Livelock
BD87 X No Fix Package C6 Transitions May Cause Memory Bit Errors to be Observed
BD88 X No Fix
FP Data Operand Pointer May Be Incorrectly Calculated After an FP Access Which
Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit Address Size in 64-bit Mode
BD89 X No Fix
FP Data Operand Pointer May Be Incorrectly Calculated After an FP Access Which
Wraps a 64-Kbyte Boundary in 16-bit Code
BD90 X No Fix Spurious PROCHOT# Assertion During Warm Reset May Hang the Processor
Table 3. Errata Summary Table (Sheet 4 of 4)
Errata
Number
Steppings
Status ERRATA
B-1