Intel® Xeon® Processor 5600 Series
42
Specification Update, March 2010
BD84.
PECI Reads of Machine Check MSRs in the Processor Core May Not
Function Correctly
Problem:
PECI reads which target machine check MSRs in the processor core may either be
directed to a different core than intended or report that the data is not available.
Implication:
PECI reads of machine check MSRs in the processor core may return incorrect data or
incorrectly report that data is not available for the requested core.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the
BD85.
The Combination of a Page-Split Lock Access And Data Accesses That
Are Split Across Cacheline Boundaries May Lead to Processor Livelock
Problem:
Under certain complex micro-architectural conditions, the simultaneous occurrence of a
page-split lock and several data accesses that are split cacheline boundaries may lead
to processor livelock.
Implication:
Due to this erratum, a livelock may occur that can only be terminated by a processor
reset. Intel has not observed this erratum with any commercially available software.
Workaround:
None identified.
Status:
For the steppings affected, see the
BD86.
Package C6 Transitions May Cause Memory Bit Errors to be Observed
Problem:
During Package C6 transitions, internal signaling noise may cause the DDRx_CKE signal
to become asserted during self-refresh. These assertions may result in memory bit
errors upon exiting from the package C6 state. Due to this erratum the DDRx_CKE
signals can be driven during times in which the DDR3 JEDEC specification requires that
they are idle.
Implication:
DDRx_CKE signals can be driven during package C6 memory self-refresh creating an
invalid memory DRAM state. A system hang, memory ECC errors or unpredictable
system behavior may occur when exiting the package C6 state.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the
BD87.
FP Data Operand Pointer May Be Incorrectly Calculated After an FP
Access Which Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit
Address Size in 64-bit Mode
Problem:
The FP (Floating Point) Data Operand Pointer is the effective address of the operand
associated with the last non-control FP instruction executed by the processor. If an 80-
bit FP access (load or store) uses a 32-bit address size in 64-bit mode and the memory
access wraps a 4-Gbyte boundary and the FP environment is subsequently saved, the
value contained in the FP Data Operand Pointer may be incorrect.
Implication:
Due to this erratum, the FP Data Operand Pointer may be incorrect. Wrapping an 80-bit
FP load around a 4-Gbyte boundary in this way is not a normal programming practice.
Intel has not observed this erratum with any commercially available software.
Workaround:
If the FP Data Operand Pointer is used in a 64-bit operating system which may run code
accessing 32-bit addresses, care must be taken to ensure that no 80-bit FP accesses
are wrapped around a 4-Gbyte boundary.
Status:
