Intel® Xeon® Processor 5600 Series
33
Specification Update, March 2010
registers, then programming three event values 0x4300D2, 0x4300B1 and 0x4300B5
into the IA32_PERFEVTSELx MSRs, and finally continuing with new event programming
and restoring previous programming if necessary. Each performance counter,
IA32_PMCx, must have its corresponding IA32_PREFEVTSELx MSR programmed with at
least one of the event values and must be enabled in IA32_PERF_GLOBAL_CTRL MSR
(38FH) bits [3:0]. All three values must be written to either the same or different
IA32_PERFEVTSELx MSRs before programming the performance counters. Note that
the performance counter will not increment when its IA32_PERFEVTSELx MSR has a
value of 0x4300D2, 0x4300B1 or 0x4300B5 because those values have a zero UMASK
field (bits [15:8]).
Status:
For the steppings affected, see the
BD54.
Memory Thermal Throttling May Not Work as Expected in Lockstep
Channel Mode
Problem:
Thermal Throttling on a channel that is in lockstep mode affects all channels in order to
maintain lockstep requirements. If throttling parameters are modified at different times
during runtime, throttling on one channel is likely to be out of phase with throttling on
other channels. Throttling which is out of phase will result in more throttling than
anticipated. If the throttling duty cycle exceeds 50%, certain phase relationships can
result in persistent memory traffic blockage.
Implication:
Runtime modification of throttling parameters may result in a system hang.
Workaround:
Since Thermal Throttling on one channel affects all channels while in lockstep mode,
throttling should only be applied to one channel.
Status:
For the steppings affected, see the
BD55.
Simultaneous Accesses to the Processor via JTAG and PECI May Cause
Unexpected Behavior
Problem:
JTAG commands that are executed at the same time as a PECI (Platform Environment
Control Interface)
access may cause unexpected behavior. In addition the PECI
command may take longer to complete or may not complete.
Implication:
The processor could be left in an unexpected state and any software or firmware doing
PECI writes may time out.
Workaround:
Ensure that PECI commands are not executed while using JTAG.
Status:
For the steppings affected, see the
BD56.
Performance Monitor Event Offcore_response_0 (B7H) Does Not
Count NT Stores to Local DRAM Correctly
Problem:
When a IA32_PERFEVTSELx MSR is programmed to count the Offcore_response_0
event (Event:B7H), selections in the OFFCORE_RSP_0 MSR (1A6H) determine what is
counted. The following two selections do not provide accurate counts when counting NT
(Non-Temporal) Stores:
• OFFCORE_RSP_0 MSR bit [14] is set to 1 (LOCAL_DRAM) and bit [7] is set to 1
(OTHER): NT Stores to Local DRAM are not counted when they should have been.
OFFCORE_RSP_0 MSR bit [9] is set to (OTHER_CORE_HIT_SNOOP) and bit [7] is set to
1 (OTHER): NT Stores to Local DRAM are counted when they should not have been.
Implication:
The counter for the Offcore_response_0 event may be incorrect for NT stores.
Workaround:
None identified.
Status:
