Intel® Xeon® Processor 5600 Series
32
Specification Update, March 2010
BD50.
Failing DIMM ID May be Incorrect in the 2DPC Configuration When
Mirroring is Enabled
Problem:
When redundancy is lost in the 2DPC (2 DIMMs Per Channel) configuration,
MC_SMI_SPARE_DIMM_ERROR_STATUS CSR bits [13:12]
(REDUNDANCY_LOSS_FAILING_DIMM) may indicate the incorrect failing DIMM ID. The
2DPC configuration is indicated when MC_CHANNEL_{0,1}_DIMM_INIT_PARAMS CSR
bit [24] (THREE_DIMMS_PRESENT) is 0.
Implication:
The failing DIMM ID may be reported incorrectly in the 2DPC configuration when
mirroring is enabled. The 3DPC configuration is not affected.
Workaround:
Only use the value in bit [13] to determine the failing DIMM ID in the non-3PDC
configurations when mirroring is enabled. This workaround will show correct results for
both the 1DPC and 2DPC configurations.
Status:
For the steppings affected, see the
BD51.
ISSUEONCE Bit in MC_SCRUB_CONTROL Register Does Not Work
Correctly
Problem:
When ISSUEONCE (bit [25]) in the MC_SCRUB_CONTROL register (Device 3, Function
2, Offset 4CH) is set, the memory controller should issue one patrol scrub. Due to this
erratum, scrubbing requests continue to be issued.
Implication:
ISSUEONCE bit in MC_SCRUB_CONTROL register does not work correctly.
Workaround:
None identified.
Status:
For the steppings affected, see the
BD52.
Memory Aliasing of Code Pages May Cause Unpredictable System
Behavior
Problem:
The type of memory aliasing contributing to this erratum is the case where two
different logical processors have the same code page mapped with two different
memory types. Specifically, if one code page is mapped by one logical processor as
write-back and by another as uncacheable and certain instruction fetch timing
conditions occur, the system may experience unpredictable behavior.
Implication:
The type of memory aliasing contributing to this erratum is the case where two
different logical processors have the same code page mapped with two different
memory types. Specifically, if one code page is mapped by one logical processor as
write-back and by another as uncacheable and certain instruction fetch timing
conditions occur, the system may experience unpredictable behavior.
Workaround:
Code pages should not be mapped with uncacheable and cacheable memory types at
the same time.
Status:
For the steppings affected, see the
BD53.
Performance Monitor Counters May Count Incorrectly
Problem:
Under certain circumstances, a general purpose performance counter, IA32_PMC0-4
(C1H – C4H), may count at core frequency or not count at all instead of counting the
programmed event.
Implication:
The Performance Monitor Counter IA32_PMCx may not properly count the programmed
event. Due to the requirements of the workaround there may be an interruption in the
counting of a previously programmed event during the programming of a new event.
Workaround:
Before programming the performance event select registers, IA32_PERFEVTSELx MSR
(186H – 189H), the internal monitoring hardware must be cleared. This is
accomplished by first disabling, saving valid events and clearing from the select
