Intel® Xeon® Processor 5600 Series
36
Specification Update, March 2010
of load or store instructions retired. However, due to this erratum, they may
undercount.
Implication:
The performance monitor event INSTR_RETIRED and MEM_INST_RETIRED may reflect
a count lower than the actual number of events.
Workaround:
None identified.
Status:
For the steppings affected, see the
BD63.
A Page Fault May Not be Generated When the PS bit is set to "1" in a
PML4E or PDPTE
Problem:
On processors supporting Intel® 64 architecture, the PS bit (Page Size, bit 7) is
reserved in PML4Es and PDPTEs. If the translation of the linear address of a memory
access encounters a PML4E or a PDPTE with PS set to 1, a page fault should occur. Due
to this erratum, PS of such an entry is ignored and no page fault will occur due to its
being set.
Implication:
Software may not operate properly if it relies on the processor to deliver page faults
when reserved bits are set in paging-structure entries.
Workaround:
Software should not set bit 7 in any PML4E or PDPTE that has Present Bit (Bit 0) set to
"1".
Status:
For the steppings affected, see the
BD64.
Uncacheable Access to a Monitored Address Range May Prevent
Future Triggering of the Monitor Hardware
Problem:
It is possible that an address range which is being monitored via the MONITOR
instruction could be written without triggering the monitor hardware. A read from the
monitored address range which is issued as uncacheable (for example having the
CR0.CD bit set) may prevent subsequent writes from triggering the monitor hardware.
A write to the monitored address range which is issued as uncacheable, may not trigger
the monitor hardware and may prevent subsequent writes from triggering the monitor
hardware.
Implication:
The MWAIT instruction will not exit the optimized power state and resume program flow
if the monitor hardware is not triggered.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the
BD65.
Intel® Interconnect BIST (Intel® IBIST) Results May be Additionally
Reported After a GETSEC[WAKEUP] or INIT-SIPI Sequence
Problem:
BIST results should only be reported in EAX the first time a logical processor wakes up
from the Wait-For-SIPI state. Due to this erratum, Intel® Interconnect BIST (Intel®
IBIST)(Intelresults may be additionally reported after INIT-SIPI sequences and when
waking up RLP’s from the SENTER sleep state using the GETSEC[WAKEIUP] command.
Implication:
An INIT-SIPI sequence may show a non-zero value in EAX upon wakeup when a zero
value is expected. RLP’s waking up for the SENTER sleep state using the
GETSEC[WAKEUP] command may show a different value in EAX upon wakeup than
before going into the SENTER sleep state.
Workaround:
If necessary software may save the value in EAX prior to launching into the secure
environment and restore upon wakeup and/or clear EAX after the INIT-SIPI sequence.
Status:
