Intel® Xeon® Processor 5600 Series
38
Specification Update, March 2010
overly aggressive in demoting OS C-sate requests to a C-sate with higher power and
lower exit latency.
Implication:
This aggressive demotion can result in higher platform power under idle conditions.
Workaround:
None identified
Status:
For the steppings affected, see the
BD70.
LBRs May Not be Initialized During Power-On Reset of the Processor
Problem:
If a second reset is initiated during the power-on processor reset cycle, the LBRs (Last
Branch Records) may not be properly initialized.
Implication:
Due to this erratum, debug software may not be able to rely on the LBRs out of power-
on reset.
Workaround:
Ensure that the processor has completed its power-on reset cycle prior to initiating a
second reset.
Status:
For the steppings affected, see the
BD71.
Multiple Performance Monitor Interrupts are Possible on Overflow of
Fixed Counter 0
Problem:
The processor can be configured to issue a PMI (performance monitor interrupt) upon
overflow of the IA32_FIXED_CTR0 MSR (309H). A single PMI should be observed on
overflow of IA32_FIXED_CTR0, however multiple PMIs are observed when this erratum
occurs. This erratum only occurs when IA32_FIXED_CTR0 overflows and the processor
and counter are configured as follows:
• Intel Hyper-Threading Technology is enabled
• IA32_FIXED_CTR0 local and global controls are enabled
• IA32_FIXED_CTR0 is set to count events only on its own thread
(IA32_FIXED_CTR_CTRL MSR (38DH) bits[2] = ‘0)
• PMIs are enabled on IA32_FIXED_CTR0 (IA32_FIXED_CTR_CTRL MSR bit[3] = ‘1)
• Freeze_on_PMI feature is enabled (IA32_DEBUGCTL MSR (1D9H) bit[12] = ‘1)
Implication:
When this erratum occurs there may be multiple PMIs observed when
IA32_FIXED_CTR0 overflows.
Workaround:
Disable the FREEZE_PERFMON_ON_PMI feature in IA32_DEBUGCTL MSR (1D9H)
bit[12].
Status:
For the steppings affected, see the
BD72.
VM Exits Due to LIDR/LGDT/SIDT/SGDT Do Not Report Correct
Operand Size
Problem:
When a VM exit occurs due to a LIDT, LGDT, SIDT, or SGDT instruction with a 32-bit
operand, bit 11 of the VM-exit instruction information field should be set to 1. Due to
this erratum, this bit is instead cleared to 0 (indicating a 16-bit operand).
Implication:
Virtual-machine monitors cannot rely on bit 11 of the VM-exit instruction information
field to determine the operand size of the instruction causing the VM exit.
Workaround:
Virtual-machine monitor software may decode the instruction to determine operand
size.
Status:
