Intel® Xeon® Processor 5600 Series
21
Specification Update, March 2010
Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 1: Basic
Architecture, for information on the usage of the ENTER instructions. This erratum is
not expected to occur in ring 3. Faults are usually processed in ring 0 and stack switch
occurs when transferring to ring 0. Intel has not observed this erratum on any
commercially available software.
Workaround:
None identified.
Status:
For the steppings affected, see the
BD11.
IRET under Certain Conditions May Cause an Unexpected Alignment
Check Exception
Problem:
In IA-32e mode, it is possible to get an Alignment Check Exception (#AC) on the IRET
instruction even though alignment checks were disabled at the start of the IRET. This
can only occur if the IRET instruction is returning from CPL3 code to CPL3 code. IRETs
from CPL0/1/2 are not affected. This erratum can occur if the EFLAGS value on the
stack has the AC flag set, and the interrupt handler's stack is misaligned. In IA-32e
mode, RSP is aligned to a 16-byte boundary before pushing the stack frame.
Implication:
In IA-32e mode, under the conditions given above, an IRET can get a #AC even if
alignment checks are disabled at the start of the IRET. This erratum can only be
observed with a software generated stack frame.
Workaround:
Software should not generate misaligned stack frames for use with IRET.
Status:
For the steppings affected, see the
BD12.
General Protection Fault (#GP) for Instructions Greater than 15 Bytes
May be Preempted
Problem:
When the processor encounters an instruction that is greater than 15 bytes in length, a
#GP is signaled when the instruction is decoded. Under some circumstances, the #GP
fault may be preempted by another lower priority fault (for example, Page Fault (#PF)).
However, if the preempting lower priority faults are resolved by the operating system
and the instruction retried, a #GP fault will occur.
Implication:
Software may observe a lower-priority fault occurring before or in lieu of a #GP fault.
Instructions of greater than 15 bytes in length can only occur if redundant prefixes are
placed before the instruction.
Workaround:
None identified.
Status:
For the steppings affected, see the
BD13.
General Protection (#GP) Fault May Not Be Signaled on Data Segment
Limit Violation above 4-G Limit
Problem:
In 32-bit mode, memory accesses to flat data segments (base = 00000000h) that
occur above the 4G limit (0ffffffffh) may not signal a #GP fault.
Implication:
When such memory accesses occur in 32-bit mode, the system may not issue a #GP
fault.
Workaround:
Software should ensure that memory accesses in 32-bit mode do not occur above the
4G limit (0ffffffffh).
Status:
For the steppings affected, see the
BD14.
LBR, BTS, BTM May Report a Wrong Address when an Exception/
Interrupt Occurs in 64-bit Mode
Problem:
An exception/interrupt event should be transparent to the LBR (Last Branch Record),
BTS (Branch Trace Store) and BTM (Branch Trace Message) mechanisms. However,
