Intel® Xeon® Processor 5600 Series
41
Specification Update, March 2010
BD80.
PEBS Records Not Created For FP-Assists Events
Problem:
When a performance monitor counter is configured to count FP_ASSISTS (Event: F7H)
and to trigger PEBS (Precise Event Based Sampling), the processor does not create a
PEBS record when the counter overflows.
Implication:
FP_ASSISTS events cannot be used for PEBS.
Workaround:
None identified.
Status:
For the steppings affected, see the
BD81.
MSR_TURBO_RATIO_LIMIT MSR May Return Intel® Turbo Boost
Technology Core Ratio Multipliers for Non-Existent Core
Configurations
Problem:
MSR_TURBO_RATIO_LIMIT MSR (1ADH) is designed to describe the maximum Intel
Turbo Boost Technology potential of the processor. On some processors, a non-zero
Intel Turbo Boost Technology value will be returned for non-existent core
configurations.
Implication:
Due to this erratum, software using the MSR_TURBO_RATIO_LIMIT MSR to report Intel
Turbo Boost Technology processor capabilities may report erroneous results.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the
BD82.
L1 Cache Uncorrected Errors May be Recorded as Correctable in 16K
Mode
Problem:
When the L1 Cache is operating in 16K redundant parity mode and a parity error occurs
on both halves of the duplicated cache on the same cacheline, an uncorrectable error
should be logged. Due to this erratum, the uncorrectable error will be recorded as
correctable, however a machine check exception will be appropriately taken in this
case.
Implication:
Due to this erratum, the IA32_MCi_STATUS.UC bit will incorrectly contain a value of 0
indicating a correctable error.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the
BD83.
Extra APIC Timer Interrupt May Occur During a Write to the Divide
Configuration Register
Problem:
If the APIC timer Divide Configuration Register (Offset 03E0H) is written at the same
time that the APIC timer Current Count Register (Offset 0390H) reads 1H, it is possible
that the APIC timer will deliver two interrupts.
Implication:
Due to this erratum, two interrupts may unexpectedly be generated by an APIC timer
event.
Workaround:
Software should reprogram the Divide Configuration Register only when the APIC timer
interrupt is disarmed.
Status:
