Intel® Xeon® Processor 5600 Series
29
Specification Update, March 2010
be processed after C6 wakeup and after interrupts are re-enabled (EFLAGS.IF=1).
However, the pending interrupt event will not be cleared.
Implication:
Due to this erratum, an infinite stream of interrupts will occur on the core servicing the
external interrupt. Intel has not observed this erratum with any commercially available
software/system.
Workaround:
None identified.
Status:
For the steppings affected, see the
BD39.
Two xAPIC Timer Event Interrupts May Unexpectedly Occur
Problem:
If an xAPIC timer event is enabled and while counting down the current count reaches
1 at the same time that the processor thread begins a transition to a low power C-
state, the xAPIC may generate two interrupts instead of the expected one when the
processor returns to C0.
Implication:
Due to this erratum, two interrupts may unexpectedly be generated by an xAPIC timer
event.
Workaround:
None identified.
Status:
For the steppings affected, see the
BD40.
EOI Transaction May Not be Sent if Software Enters Core C6 During an
Interrupt Service Routine
Problem:
If core C6 is entered after the start of an interrupt service routine but before a write to
the APIC EOI register, the core may not send an EOI transaction (if needed) and further
interrupts from the same priority level or lower may be blocked.
Implication:
EOI transactions and interrupts may be blocked when core C6 is used during interrupt
service routines. Intel has not observed this erratum with any commercially available
software.
Workaround:
None identified.
Status:
For the steppings affected, see the
BD41.
FREEZE_WHILE_SMM Does Not Prevent Event From Pending PEBS
During SMM
Problem:
In general, a PEBS record should be generated on the first count of the event after the
counter has overflowed. However, IA32_DEBUGCTL_MSR.FREEZE_WHILE_SMM (MSR
1D9H, bit [14]) prevents performance counters from counting during SMM (System
Management Mode). Due to this erratum, if
1. A performance counter overflowed before an SMI
2. A PEBS record has not yet been generated because another count of the event has
not occurred
3. The monitored event occurs during SMM
then a PEBS record will be saved after the next RSM instruction.
When FREEZE_WHILE_SMM is set, a PEBS should not be generated until the event
occurs outside of SMM.
Implication:
A PEBS record may be saved after an RSM instruction due to the associated
performance counter detecting the monitored event during SMM; even when
FREEZE_WHILE_SMM is set.
Workaround:
None identified.
