Intel Xeon 5600 Series, Specification Update

Page: 16 / 46

Intel® Xeon® Processor 5600 Series 16
Specification Update, March 2010
BD52 X No Fix Memory Aliasing of Code Pages May Cause Unpredictable System Behavior
BD53 X No Fix Performance Monitor Counters May Count Incorrectly
BD54 X No Fix Memory Thermal Throttling May Not Work as Expected in Lockstep Channel Mode
BD55 X No Fix
Simultaneous Accesses to the Processor via JTAG and PECI May Cause
Unexpected Behavior
BD56 X No Fix
Performance Monitor Event Offcore_response_0 (B7H) Does Not Count NT Stores
to Local DRAM Correctly
BD57 X No Fix
EFLAGS Discrepancy on Page Faults and on EPT-Induced VM Exits after a
Translation Change
BD58 X No Fix
System May Hang if MC_CHANNEL_{0,1,2}_MC_DIMM_INIT_CMD.DO_ZQCL
Commands Are Not Issued in Increasing Populated DDR3 Rank Order
BD59 X No Fix
Package C3/C6 Transitions When Memory 2x Refresh is Enabled May Result in a
System Hang
BD60 X No Fix
Back to Back Uncorrected Machine Check Errors May Overwrite
IA32_MC3_STATUS.MSCOD
BD61 X No Fix
Corrected Errors With a Yellow Error Indication May be Overwritten by Other
Corrected Errors
BD62 X No Fix
Performance Monitor Events DCACHE_CACHE_LD and DCACHE_CACHE_ST
May Overcount
BD63 X No Fix
Performance Monitor Events INSTR_RETIRED and MEM_INST_RETIRED May
Count Inaccurately
BD64 X No Fix
A Page Fault May Not be Generated When the PS bit is set to "1" in a PML4E or
PDPTE
BD65 X No Fix
Uncacheable Access to a Monitored Address Range May Prevent Future Triggering
of the Monitor Hardware
BD66 X No Fix
Intel® Interconnect BIST (Intel® IBIST) Results May be Additionally Reported After
a GETSEC[WAKEUP] or INIT-SIPI Sequence
BD67 X No Fix Pending x87 FPU Exceptions (#MF) May be Signaled Earlier Than Expected
BD68 X No Fix VM Exits Due to “NMI-Window Exiting” May Be Delayed by One Instruction
BD69 X No Fix
Multiple Performance Monitor Interrupts are Possible on Overflow of
IA32_FIXED_CTR2
BD70 X No Fix
C-State Autodemotion May be too Aggressive Under Certain Configurations and
Workloads
BD71 X No Fix LBRs May Not be Initialized During Power-On Reset of the Processor
BD72 X No Fix
Multiple Performance Monitor Interrupts are Possible on Overflow of Fixed Counter
0
BD73 X No Fix VM Exits Due to LIDR/LGDT/SIDT/SGDT Do Not Report Correct Operand Size
BD74 X No Fix
Performance Monitoring Events STORE_BLOCKS.NOT_STA and
STORE_BLOCKS.STA May Not Count Events Correctly
BD75 X No Fix Storage of PEBS Record Delayed Following Execution of MOV SS or STI
BD76 X No Fix
Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not Count Some
Transitions
BD77 X No Fix The PECI Bus May be Tri-stated After System Reset
BD78 X No Fix LER MSRs May Be Unreliable
Table 3. Errata Summary Table (Sheet 3 of 4)
Errata
Number
Steppings
Status ERRATA
B-1