Intel® Xeon® Processor 5600 Series
40
Specification Update, March 2010
determines this asserted state as another PECI host initiating a transaction, it may
release control of the bus resulting in a permanent tri-state condition.
Implication:
Due to this erratum, the PECI host may incorrectly determine that it is not the bus
master and consequently PECI commands initiated by the PECI software layer may
receive incorrect/invalid responses.
Workaround:
To workaround this erratum the PECI host should pull the PECI bus low to initiate a
PECI transaction.
Status:
For the steppings affected, see the
BD77.
LER MSRs May Be Unreliable
Problem:
Due to certain internal processor events, updates to the LER (Last Exception Record)
MSRs, MSR_LER_FROM_LIP (1DDH) and MSR_LER_TO_LIP (1DEH), may happen when
no update was expected.
Implication:
The values of the LER MSRs may be unreliable.
Workaround:
None identified.
Status:
For the steppings affected, see the
BD78.
APIC Timer CCR May Report 0 in Periodic Mode
Problem:
In periodic mode the APIC timer CCR (current-count register) is supposed to be
automatically reloaded from the initial-count register when the count reaches 0,
consequently software would never be able to observe a value of 0. Due to this
erratum, software may read 0 from the CCR when the timer has counted down and is in
the process of re-arming.
Implication:
Due to this erratum, an unexpected value of 0 may be read from the APIC timer CCR
when in periodic mode.
Workaround:
None identified.
Status:
For the steppings affected, see the
BD79.
LBR, BTM or BTS Records May have Incorrect Branch From
Information After an Intel Enhanced SpeedStep Technology
Transition, T-states, C1E, or Adaptive Thermal Throttling
Problem:
The “Form” address associated with the LBR (Last Branch Record), BTM (Branch Trace
Message) or BTS (Branch Trace Store) may be incorrect for the first branch after an
EIST (Enchanced Intel® SpeedStep Technology) transition, T-states, C1E (C1
Enhanced), or Adaptive Thermal Throttling.
Implication:
When the LBRs, BTM or BTS are enabled, some records may have incorrect branch
“From” addresses for the first branch after an EIST transition, T-states, C1E, or
Adaptive Thermal Throttling.
Workaround:
None identified.
Status:
