Intel Xeon 5600 Series Specification Update Download

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Intel® Xeon® Processor 5600 Series

Specification Update, March 2010

Component Marking

The Intel® Xeon® Processor 5600 Series can be identified by the following component

markings:

Figure 1.

Processor Top-side Markings (Example)

Table 2.

Intel® Xeon® Processor 5600 Series Identification (Sheet 1 of 2)

S-Spec

Number

Steppin

CPUID

Core Frequency (GHz)

Intel QuickPath

Interconnect (GT/s) /

DDR3 (MHz) / DDR3L

(MHz)

Available

bins of Intel

Turbo Boost

Technology

Cache

Size

(MB)

TDP

(W)

Notes

SLBV5

B-1

0x000206C2

3.33 / 6.40 / 1333 / 1333

1/1/1/1/2/2

130

SLBV9

B-1

0x000206C2

2.93 / 6.40 / 1333 / 1333

2/2/2/2/3/3

130

SLBV7

B-1

0x000206C2

2.80 / 6.40 / 1333 / 1333

2/2/2/2/3/3

SLBVA

B-1

0x000206C2

3.06 / 6.40 / 1333 / 1333

na/na/2/2/3/

SLBV6

B-1

0x000206C2

2.80 / 6.40 / 1333 / 1333

2/2/2/2/3/3

SLBV3

B-1

0x000206C2

2.66 / 6.40 / 1333 / 1333

2/2/2/2/3/3

SLBVC

B-1

0x000206C2

2.66 / 5.86 / 1066 / 1066

na/na/1/1/2/

SLBVB

B-1

0x000206C2

2.53 / 5.86 / 1066 / 1066

2/2/2/2/3/3

SLBV4

B-1

0x000206C2

2.40 / 5.86 / 1066 /1066

na/na/1/1/2/

SLBV8

B-1

0x000206C2

2.26 / 5.86 / 1333 / 1333

2/2/3/3/4/4

SLBVD

B-1

0x000206C2

2.13 / 5.86 / 1066 / 1066

na/na/1/1/2/

SLBVJ

B-1

0x000206C2

1.86 / 4.80 / 1066 / 1066

Summary of Contents for Xeon 5600 Series

Page 1: ...Reference Number 323372 001 Intel Xeon Processor 5600 Series Specification Update March 2010 ...

Page 2: ... dates and figures specified are preliminary based on current expectations and are subject to change without notice All dates specified are target dates are provided for planning purposes only and are subject to change This document contains information on products in the design phase of development Do not finalize a design with this information Revised information will be published when the produ...

Page 3: ...es 3 Specification Update March 2010 Contents Revision History 5 Preface 6 Identification Information 8 Summary Table of Changes 11 Errata Summary 14 Specification Changes 44 Specification Clarifications 45 Documentation Changes 46 ...

Page 4: ...Intel Xeon Processor 5600 Series 4 Specification Update March 2010 ...

Page 5: ...Intel Xeon Processor 5600 Series 5 Specification Update March 2010 Revision History Doc ID Revision Description Date 323372 001 Initial Release March 2010 ...

Page 6: ...also contain information that was not previously published Affected Documents Related Documents Notes 1 Document is available publicly at http developer intel com Document Title Notes1 Intel Xeon Processor 5600 Series Datasheet Volume 1 2 323369 323370 Document Title Location Notes Intel 64 and IA 32 Architectures Software Developer s Manual Volume 1 Basic Architecture Volume 2A Instruction Set Re...

Page 7: ...lease of the specification Specification Clarifications describe a specification in greater detail or further highlight a specification s impact to a complex design situation These clarifications will be incorporated in any new release of the specification Documentation Changes include typographical errors omissions or incorrect information from the current published specifications These will be i...

Page 8: ...nd the generation field of the Device ID register accessible through Boundary Scan 5 The Model Number corresponds to bits 7 4 of the EDX register after RESET bits 7 4 of the EAX register after the CPUID instruction is executed with a 1 in the EAX register and the model field of the Device ID register accessible through Boundary Scan 6 The Stepping ID in bits 3 0 indicates the revision number of th...

Page 9: ...33 1333 1 1 1 1 2 2 12 130 2 SLBV9 B 1 0x000206C2 2 93 6 40 1333 1333 2 2 2 2 3 3 12 130 3 SLBV7 B 1 0x000206C2 2 80 6 40 1333 1333 2 2 2 2 3 3 12 95 4 SLBVA B 1 0x000206C2 3 06 6 40 1333 1333 na na 2 2 3 3 12 95 7 SLBV6 B 1 0x000206C2 2 80 6 40 1333 1333 2 2 2 2 3 3 12 95 5 SLBV3 B 1 0x000206C2 2 66 6 40 1333 1333 2 2 2 2 3 3 12 95 6 SLBVC B 1 0x000206C2 2 66 5 86 1066 1066 na na 1 1 2 2 12 80 8 ...

Page 10: ...r L5609 14 This is an Intel Xeon Processor E5645 15 This is an Intel Xeon Processor L5638 16 This is an Intel Xeon Processor L5618 17 The core frequency reported in the processor brand string is rounded to 2 decimal digits For example core frequency of 2 6666 repeating 6 is reported as 2 67 in brand string Core frequency of 2 1333 is reported as 2 13 in brand string SLBWZ B 1 0x000206C2 2 40 5 86 ...

Page 11: ...us Column No Fix There are no plans to fix this erratum Plan Fix This erratum may be fixed in a future stepping of the product Fixed This erratum has been fixed A change bar to the left of the table row indicates this erratum is either new or has been modified from the previous revision of this document A Intel Xeon processor 7000 sequence C Intel Celeron processor D Intel Xeon processor 2 80 GHz ...

Page 12: ...tel Core 2 Duo Solo Processor for Intel Centrino Duo Processor Technology AI Intel Core 2 Extreme processor X6800 and Intel Core 2 Duo desktop processor E6000 and E4000 sequence AJ Intel Xeon processor 5300 series AK Intel Core 2 Extreme quad core processor QX6000 sequence and Intel Core 2 Quad processor Q6000 sequence AL Intel Xeon processor 7100 series AM Intel Celeron processor 400 sequence AN ...

Page 13: ...r QX9775 AAE Intel Atom processor Z5xx series AAF Intel Atom processor 200 series AAG Intel Atom processor N series AAH Intel Atom processor 300 series AAI Intel Xeon processor 7400 series AAJ Intel Core i7 processor and Intel Core i7 Extreme Edition processor AAK Intel Xeon processor 5500 series AAL Intel Pentium Dual Core processor E5000 series BD Intel Xeon processor 5600 series ...

Page 14: ... Conditions May Cause an Unexpected Alignment Check Exception BD12 X No Fix General Protection Fault GP for Instructions Greater than 15 Bytes May be Preempted BD13 X No Fix General Protection GP Fault May Not Be Signaled on Data Segment Limit Violation above 4 G Limit BD14 X No Fix LBR BTS BTM May Report a Wrong Address when an Exception Interrupt Occurs in 64 bit Mode BD15 X No Fix MCi_Status Ov...

Page 15: ...d to Memory Ordering Violations BD37 X No Fix A String Instruction that Re maps a Page May Encounter an Unexpected Page Fault BD38 X No Fix Infinite Stream of Interrupts May Occur if an ExtINT Delivery Mode Interrupt is Received while All Cores in C6 BD39 X No Fix Two xAPIC Timer Event Interrupts May Unexpectedly Occur BD40 X No Fix EOI Transaction May Not be Sent if Software Enters Core C6 During...

Page 16: ...tely BD64 X No Fix A Page Fault May Not be Generated When the PS bit is set to 1 in a PML4E or PDPTE BD65 X No Fix Uncacheable Access to a Monitored Address Range May Prevent Future Triggering of the Monitor Hardware BD66 X No Fix Intel Interconnect BIST Intel IBIST Results May be Additionally Reported After a GETSEC WAKEUP or INIT SIPI Sequence BD67 X No Fix Pending x87 FPU Exceptions MF May be S...

Page 17: ...uring a Write to the Divide Configuration Register BD85 X No Fix PECI Reads of Machine Check MSRs in the Processor Core May Not Function Correctly BD86 X No Fix The Combination of a Page Split Lock Access And Data Accesses That Are Split Across Cacheline Boundaries May Lead to Processor Livelock BD87 X No Fix Package C6 Transitions May Cause Memory Bit Errors to be Observed BD88 X No Fix FP Data O...

Page 18: ...bytes as opposed to the original data size WP the data size of each write will now always be 8 bytes as opposed to the original data size and there may be a memory ordering violation WT there may be a memory ordering violation Workaround Software should avoid crossing page boundaries from WB or WC memory type to UC WP or WT memory type within a single REP MOVS or REP STOS instruction that will exe...

Page 19: ...from the load being prematurely executed or from the restart and subsequent re execution of that instruction by the exception handler If the target of the load is to uncached memory that has a system side effect restarting the instruction may cause unexpected system behavior due to the repetition of the side effect Particularly while CR0 TS bit 3 is set a MOVD MOVQ with MMX XMM register operands m...

Page 20: ...ing data if sent out as a BTM on the system bus will also be incorrect Note This issue would only occur when one of the 3 above mentioned debug support facilities are used Implication The value of the LBR BTS and BTM immediately after an RSM operation should not be used Workaround None identified Status For the steppings affected see the Summary Table of Changes BD9 Single Step Interrupts with Flo...

Page 21: ...e steppings affected see the Summary Table of Changes BD12 General Protection Fault GP for Instructions Greater than 15 Bytes May be Preempted Problem When the processor encounters an instruction that is greater than 15 bytes in length a GP is signaled when the instruction is decoded Under some circumstances the GP fault may be preempted by another lower priority fault for example Page Fault PF Ho...

Page 22: ...ncorrect for Disabled Breakpoints Problem When a debug exception is signaled on a load that crosses cache lines with data forwarded from a store and whose corresponding breakpoint enable flags are disabled DR7 G0 G3 and DR7 L0 L3 the DR6 B0 B3 flags may be incorrect Implication The debug exception DR6 B0 B3 flags may be incorrect for the load if the corresponding breakpoint enable flag in DR7 is d...

Page 23: ...hardware is triggered If the MWAIT instruction causes a VM exit this could cause its exit qualification to incorrectly report 0x1 In the recommended usage model for MONITOR MWAIT there is no write to the range armed by the MONITOR instruction between the MONITOR and the MWAIT Workaround Software should never write to the address range armed by the MONITOR instruction between the MONITOR and the su...

Page 24: ...ched Stack Segment and Stack Pointer If MOV SS POP SS is not followed by a MOV r e SP r e BP there may be a mismatched Stack Segment and Stack Pointer on any exception Intel has not observed this erratum with any commercially available software or system Workaround As recommended in the Intel 64 and IA 32 Intel Architectures Software Developer s Manual the use of MOV SS POP SS in conjunction with ...

Page 25: ...32_MCi_MISC may incorrectly contain the patrol scrub error information and the IA32_MCi_ADDR may not be correct Implication IA32_MCi_MISC and IA32_MCi_STATUS information may be inconsistent IA32_MCi_ADDR may be incorrect Workaround None identified Status For the steppings affected see the Summary Table of Changes BD27 The Memory Controller tTHROT_OPREF Timings May be Violated During Self Refresh E...

Page 26: ...ask bit set If there is no Interrupt Service Routine ISR set up for that vector the system will GP fault If the ISR does not do an End of Interrupt EOI the bit for the vector will be left set in the in service register and mask all interrupts at the same or lower priority Workaround Any vector programmed into an LVT entry must have an ISR associated with it even if that vector was programmed as ma...

Page 27: ... located at physical addresses that are mapped to WB memory type by the MTRRs Status For the steppings affected see the Summary Table of Changes BD34 B0 B3 Bits in DR6 For Non Enabled Breakpoints May be Incorrectly Set Problem Some of the B0 B3 bits breakpoint conditions detect flags bits 3 0 in DR6 may be incorrectly set for non enabled breakpoints when the following sequence happens 1 MOV or POP...

Page 28: ...lation for the page for example by clearing to 0 the present bit in one of the paging structure entries used to translate the page An iteration of a string instruction modifies the paging structures so that the translation is again a valid translation for the page e g by setting to 1 the bit that was cleared earlier A later iteration of the same string instruction loads from a linear address on th...

Page 29: ... interrupt service routine but before a write to the APIC EOI register the core may not send an EOI transaction if needed and further interrupts from the same priority level or lower may be blocked Implication EOI transactions and interrupts may be blocked when core C6 is used during interrupt service routines Intel has not observed this erratum with any commercially available software Workaround ...

Page 30: ...ion Due to this erratum any DR6 changes caused by a MOV SS r m or POP SS instruction may be cleared if the following instruction is a store Implication When this erratum occurs incorrect information may exist in DR6 This erratum will not be observed under normal usage of the MOV SS r m or POP SS instructions that is following them with an instruction that writes e r SP When debugging or when devel...

Page 31: ...Summary Table of Changes BD48 Sleeping Cores May Not be Woken Up on Logical Cluster Mode Broadcast IPI Using Destination Field Instead of Shorthand Problem If software sends a logical cluster broadcast IPI using a destination shorthand of 00B No Shorthand and writes the cluster portion of the Destination Field of the Interrupt Command Register to all ones while not using all 1s in the mask portion...

Page 32: ...liasing contributing to this erratum is the case where two different logical processors have the same code page mapped with two different memory types Specifically if one code page is mapped by one logical processor as write back and by another as uncacheable and certain instruction fetch timing conditions occur the system may experience unpredictable behavior Implication The type of memory aliasi...

Page 33: ...ng parameters may result in a system hang Workaround Since Thermal Throttling on one channel affects all channels while in lockstep mode throttling should only be applied to one channel Status For the steppings affected see the Summary Table of Changes BD55 Simultaneous Accesses to the Processor via JTAG and PECI May Cause Unexpected Behavior Problem JTAG commands that are executed at the same tim...

Page 34: ...cted see the Summary Table of Changes BD57 System May Hang if MC_CHANNEL_ 0 1 2 _MC_DIMM_INIT_CMD DO_ZQCL Commands Are Not Issued in Increasing Populated DDR3 Rank Order Problem ZQCL commands are used during initialization to calibrate DDR3 termination A ZQCL command can be issued by writing 1 to the MC_CHANNEL_ 0 1 2 _MC_DIMM_INIT_CMD DO_ZQCL Device 4 5 6 Function 0 Offset 15 bit 15 field and it ...

Page 35: ...d with IA32_MCi_STATUS MCACOD bits 15 0 with value of 000x_0001_xxxx_xx01 where x stands for zero or one and a yellow threshold based error status indication bits 54 53 equal to 10B may be overwritten by a corrected error with a no tracking indication 00B or green indication 01B Implication Corrected errors with a yellow threshold based error status indication may be overwritten by a corrected err...

Page 36: ... from the monitored address range which is issued as uncacheable for example having the CR0 CD bit set may prevent subsequent writes from triggering the monitor hardware A write to the monitored address range which is issued as uncacheable may not trigger the monitor hardware and may prevent subsequent writes from triggering the monitor hardware Implication The MWAIT instruction will not exit the ...

Page 37: ...d by one additional instruction Implication VMM software using NMI window exiting for NMI virutalization should generally be unaffected as the erratum causes at most a one instruction delay in the injection of a virtual NMI which is virtually asynchronous The erratum may affect VMMs relying on deterministic delivery of the affected VM exits Workaround None identified Status For the steppings affec...

Page 38: ...this erratum occurs This erratum only occurs when IA32_FIXED_CTR0 overflows and the processor and counter are configured as follows Intel Hyper Threading Technology is enabled IA32_FIXED_CTR0 local and global controls are enabled IA32_FIXED_CTR0 is set to count events only on its own thread IA32_FIXED_CTR_CTRL MSR 38DH bits 2 0 PMIs are enabled on IA32_FIXED_CTR0 IA32_FIXED_CTR_CTRL MSR bit 3 1 Fr...

Page 39: ...ratum if the counter overflow occurs after execution of either MOV SS or STI storage of the PEBS record is delayed by one instruction Implication When this erratum occurs software may observe storage of the PEBS record being delayed by one instruction following execution of MOV SS or STI The state information in the PEBS record will also reflect the one instruction delay Workaround None identified...

Page 40: ...C timer CCR current count register is supposed to be automatically reloaded from the initial count register when the count reaches 0 consequently software would never be able to observe a value of 0 Due to this erratum software may read 0 from the CCR when the timer has counted down and is in the process of re arming Implication Due to this erratum an unexpected value of 0 may be read from the API...

Page 41: ...ed see the Summary Table of Changes BD82 L1 Cache Uncorrected Errors May be Recorded as Correctable in 16K Mode Problem When the L1 Cache is operating in 16K redundant parity mode and a parity error occurs on both halves of the duplicated cache on the same cacheline an uncorrectable error should be logged Due to this erratum the uncorrectable error will be recorded as correctable however a machine...

Page 42: ...ult in memory bit errors upon exiting from the package C6 state Due to this erratum the DDRx_CKE signals can be driven during times in which the DDR3 JEDEC specification requires that they are idle Implication DDRx_CKE signals can be driven during package C6 memory self refresh creating an invalid memory DRAM state A system hang memory ECC errors or unpredictable system behavior may occur when exi...

Page 43: ...y is not a normal programming practice Intel has not observed this erratum with any commercially available software Workaround If the FP Data Operand Pointer is used in an operating system which may run 16 bit FP code care must be taken to ensure that no 80 bit FP access are wrapped around a 64 Kbyte boundary Status For the steppings affected see the Summary Table of Changes BD89 Spurious PROCHOT ...

Page 44: ...sic Architecture Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2A Instruction Set Reference Manual A M Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2B Instruction Set Reference Manual N Z Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3A System Programming Guide Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3B ...

Page 45: ...ic Architecture Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2A Instruction Set Reference Manual A M Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2B Instruction Set Reference Manual N Z Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3A System Programming Guide Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3B S...

Page 46: ...ntel 64 and IA 32 Architectures Software Developer s Manual Volume 3A System Programming Guide Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3B System Programming Guide All Documentation Changes will be incorporated into a future version of the appropriate Processor documentation Note Documentation changes for Intel 64 and IA 32 Architecture Software Developer s Manual volume...

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